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IDT CPS-8 Serial RapidIO Switch Manuals
Manuals and User Guides for IDT CPS-8 Serial RapidIO Switch. We have
1
IDT CPS-8 Serial RapidIO Switch manual available for free PDF download: User Manual
IDT CPS-8 User Manual (129 pages)
Central Packet Switch
Brand:
IDT
| Category:
Switch
| Size: 0.91 MB
Table of Contents
User Manual
1
Table of Contents
3
1 Device Overview
11
Device Description
11
Key Features
12
Additional Resources
12
Block Diagram
13
Figure 1.1 Block Diagram
13
Application Example: the Wireless Basestation
14
Figure 1.2 CPS Interconnect
14
Figure 1.3 Application Overview
14
Functional Overview
15
Functional Differences with PPS-Gen2 (80KSW0001)
15
2 Srio Ports
16
Srio Port Definition
16
Table 2.1 Port Numbering
16
Table 2.2 Port Configuration Examples
17
Trace Function
18
Figure 2.1 Trace Matching Criteria
19
Figure 2.2 Illustration of the Trace Function Within a Given Port
20
Packet Filtering
22
Software Assisted Error Recovery
22
3 Switch Description
24
Conceptual Functionality
24
Switching Block and Elements
24
Figure 3.1 CPS Switch Core Block Diagram
24
Figure 3.2 Input Buffer Diagram
25
Switch Description
25
Switching Scheduler and Priorities
26
Flow Control and Congestion Management
28
4 I2C Interface
29
Overview
29
Master/Slave Configuration
29
Temporary Master Mode
29
Table 4.1 EEPROM Register Address Map
31
Table 4.2 Register Map Example
33
Table 4.3 EEPROM Format Example
34
Slave Mode
35
Table 4.4 I2C Address Pins
35
Figure 4.1 Bit Transfer on the I2C Bus
36
Figure 4.2 START and STOP Signaling
36
Figure 4.3 Data Transfer
37
Figure 4.4 Acknowledgment
37
Figure 4.5 Master Addressing a Slave with a 7-Bit Address (Transfer Direction Is Not Changed)
37
Figure 4.6 Master Reads a Slave Immediately after the First Byte
37
Figure 4.7 Combined Format
38
Figure 4.8 Master Addresses a Slave-Receiver with 10-Bit Address
38
Figure 4.9 Master Addresses a Slave Transmitter with 10-Bit Address
38
Figure 4.10 Combined Format: Master Addresses a Slave with 10-Bit Address
38
Figure 4.11 Combined Format: Master Transmits Data to Two Slaves, both with 10-Bit Address
39
Figure 4.12 Write Protocol with 10-Bit Slave Address (ADS Is 1)
40
Figure 4.13 Read Protocol with 10-Bit Slave Address (ADS Is 1)
40
Figure 4.14 Write Protocol with 7-Bit Slave Address (ADS Is 0)
40
Figure 4.15 Read Protocol with 7-Bit Slave Address (ADS Is 0)
41
5 Error Management
42
Error Management Functional Architecture
42
Figure 5.1 Functional View of Error Management Block
42
Table 5.1 Error Sources and Codes
42
Table 5.2 I2C Errors and Codes -- Group Number 0X1
43
Table 5.3 JTAG Errors and Codes -- Group Number 0X2
44
Table 5.4 Maintenance Handler Errors and Codes -- Group Number 0X3
45
Table 5.5 Configuration Errors and Codes -- Group Number 0X5
46
Table 5.6 RIO SERDES Errors and Codes -- Group Number 0X6
47
Table 5.7 RIO Link Layer Errors and Codes -- Group Number 0X7
47
Table 5.8 RIO Link Protocol Errors and Codes -- Group Number 0X8
48
Table 5.9 RIO Logical and Transport Errors and Codes -- Group Number 0X9
49
Table 5.10 Port Write Payload Definition
52
Table 5.11 Maintenance Packet Format
52
6 JTAG & Boundary Scan
53
JTAG and AC Extest Compliance
53
Test Instructions
53
Table 6.1 Test Instructions
53
Device ID Register
54
Initialization and Reset
54
Configuration Register Access
54
Table 6.2 Configuration Registers
54
Boundary Scan
55
Figure 6.1 JTAG Write Access
55
Figure 6.2 JTAG Read Access
55
7 Reference Clock
56
Reference Clock Specification
56
Pll
56
Figure 7.1 Reference Clock Representative Circuit
56
Figure 7.2 Internal PLL Clock Generator
57
8 Programming the Device
58
Device Access
58
Table 8.1 RIO Defined Maintenance Packet with CPS as Destination
58
Table 8.2 RIO Defined Maintenance Response Packet Generated by CPS
59
Route Tables
60
Figure 8.1 Route Table Lookup Diagram
60
Table 8.3 Port Configuration
61
Table 8.4 Multicast Mask Register References for Multicast Mask Port CSR Usage
63
Table 8.5 Region Select
64
Table 8.6 Port Number References
64
Table 8.7 Multicast Mask References
65
Device Programming
66
Reset Configuration
68
Example of Programming
69
Optional API Calls
70
9 Reset & Initialization
71
Registers
71
Table 9.1 Port Configuration at Power up
71
Initialization Steps
72
Initialization of RIO Ports
72
RIO System Bring up
72
Serdes Initialization
72
Table 9.2 Default Speed Settings with SPD0 and SPD1
72
10 Registers
73
Rapidio Compliance
73
Register Type Field Definitions
73
Table 10.1 Register Types
73
Address Map
74
Table 10.2 CPS Memory Map
74
Rapid IO Registers
80
Table 10.3 DEV_IDENT_CAR 0X000000
80
Table 10.4 DEV_INF_CAR 0X000004
80
Table 10.5 ASSY_IDENT_CAR 0X000008
81
Table 10.7 PROC_ELEM_FEAT_CAR 0X000010
83
Table 10.8 SWITCH_PORT_INF_CAR 0X000014
83
Table 10.9 SRC_OPS_CAR 0X000018
84
Table 10.10 SW_MCAST_SUP_CAR 0X000030
85
Table 10.11 SW_RTE_TBL_LIM_CAR 0X000034
86
Table 10.12 SW_MULT_INF_CAR 0X000038
86
HOST_BASE_DEV_ID_LOCK_CSR 0X000068
86
STD_RTE_CONF_DESTID_SEL_CSR 0X000070
87
Table 10.14 COMPONENT_TAG_CSR 0X00006C
87
Table 10.16 STD_RTE_CONF_PORT_SEL_CSR 0X000074
88
STD_RTE_DEFAULT_PORT 0X000078
88
Table 10.18 MCAST_MASK_PORT 0X000080
89
MCAST_ASSOC_SEL_CSR 0X000084
89
Table 10.20 MCAST_ASSOC_OP_CSR 0X000088
90
Table 10.21 PORT_MAINT_BLOCK_HEAD 0X000100
90
PORT_LINK_TO_CTRL_CSR 0X000120
90
RIO Extended Feature Register
91
Table 10.24 RIO Extended Register Map
91
Table 10.25 PORT_0_LINK_MAINT_REQ_CSR 0X000140
92
PORT_0_LINK_MAINT_RESP_CSR 0X000144
92
Table 10.27 PORT_0_LOCAL_ACKID_CSR 0X000148
93
Table 10.28 PORT_0_ERR_STAT_CSR 0X000158
94
IDT Specific Srio Extended Feature Set
96
LOCAL_RTE_CONF_DESTID_SEL_CSR 0X010070
96
Routing Table Registers
97
Table 10.31 Routing Table Register
97
Table 10.32 Route Table Register 0Xe00000-0Xe1F7Fc
97
Trace Registers
98
Table 10.33 Trace Register Map
98
Table 10.34 Port_0_Trace_Value_1_Block_0 0Xe40000
99
Table 10.35 Port_0_Trace_Value_1_Block_1 0Xe40004
99
Table 10.36 Port_0_Trace_Value_1_Block_2 0Xe40008
100
Table 10.37 Port_0_Trace_Value_1_Block_3 0Xe4000C
100
Table 10.39 Port_0_Mask_Value_1_Block_0 0Xe40014
101
Table 10.38 Port_0_Trace_Value_1_Block_4 0Xe40010
101
Table 10.42 Port_0_Mask_Value_1_Block_3 0Xe40020
102
Table 10.40 Port_0_Mask_Value_1_Block_1 0Xe40018
102
Table 10.41 Port_0_Mask_Value_1_Block_2 0Xe4001C
102
Global Configuration Registers
103
Table 10.44 CPS_CONTROL 0Xf2000C
103
Table 10.43 Port_0_Mask_Value_1_Block_4 0Xe40024
103
Table 10.45 CONF_MOD_ERR_REPORT_ENABLE 0Xf20014
104
Table 10.46 AUXPORT_ERR_REPORT_ENABLE 0Xf20018
105
MAINT_ERR_REPORT_ENABLE 0Xf2001C
105
Table 10.48 RIO_DOMAIN 0Xf20020
105
Table 10.49 RIO_PORT_WRITE_INFO 0Xf20024
106
RIO_PORT_WRITE_SRCID 0Xf20028
106
Table 10.51 RIO_ASSY_IDENT_CAR 0Xf2002C
107
Table 10.52 RIO_ASSY_INF_CAR 0Xf20030
107
Table 10.53 PPS_SOFT_RESET 0Xf20040
107
Table 10.54 I2C_MASTER_CTRL 0Xf20050
108
Multicast Registers
110
Table 10.55 I2C_MASTER_STAT_CTRL 0Xf20054
110
Table 10.56 MULTICAST Register Map
110
Table 10.57 MULTICAST0 0Xf30000
111
Switching Port Registers
112
Table 10.58 Switching Port Register Map
112
Table 10.59 PORT_0_BUF_SIZE 0Xf40000
113
Table 10.60 PORT_0_OPS 0Xf40004
113
Table 10.61 PORT_0_ERR_REPORT_ENABLE 0Xf40008
115
Table 10.62 PORT_0_SWITCH_BUF_STATUS 0Xf4000C
116
Table 10.63 PORT_0_ACK_CNTR 0Xf40010
116
Table 10.64 PORT_0_NACK_CNTR 0Xf40014
117
PORT_0_SW_PKT_CNTR 0Xf4001C
117
PORT_0_TRACE_MATCH_CNTR_1 0Xf40020
117
PORT_0_TRACE_MATCH_CNTR_2 0Xf40024
117
Table 10.68 PORT_0_TRACE_MATCH_CNTR_3 0Xf40028
118
PORT_0_FILTER_MATCH_CNTR_1 0Xf40030
118
PORT_0_FILTER_MATCH_CNTR_2 0Xf40034
118
Error Registers
119
PORT_0_FILTER_MATCH_CNTR_3 0Xf40038
119
Table 10.74 ERR_CAP_REG 0Xfd0000
119
Table 10.75 ERR_LOG_RD 0Xfd0004
120
Table 10.76 SPECIAL_ERR Register Map
120
Table 10.77 SPECIAL_ERR_0 0Xfd0008
120
Table 10.78 ERR_FLAG 0Xfd0028
122
Table 10.79 ERR_COUNTER 0Xfd002C
122
Table 10.80 ERR_RESET 0Xfd0030
123
QUAD Control Registers
124
Table 10.81 QUAD_CTRL Control Register Map
124
Table 10.82 QUAD_0_CTRL 0Xff0000
124
QUAD_0_ERR_REPORT_EN 0Xff0004
126
Table 10.84 QUAD_CTRL_BROADCAST 0Xfff000
127
11 References
128
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