Dram Timing Control - Viglen VIG556M Manual

DRAM Timing Control

Phoenix – AwardBIOS CMOS Setup Utility
Performance Mode
DRAM Timing Control
x DRAM CAS Latency
x RAS Active Time(tRAS)
x RAS Precharge Time(tRP)
x RAS to CAS Delay(tRCD)
MA 1T/2T Select
↑↓→←:Move
Enter:Select
F5:Previous Values
Memory Timing
Allows the used to select the CAS latency time in HCLKs of 2, 2.5 or 3. The value is
set the factory depending on the DRAM installed. DO NOT change the values in this
field unless you have changed the DRAM or CPU.
V1.0
DRAM Clock/Timing Control
Enabled
By SPD
2.5T
6T
3T
3T
Auto
+/-/PU/PD:Value F10:Save
Figure 17: DRAM Timing Control
VIG556M Motherboard Manual
Item Help
Menu Level
ESC:Exit F1:General Help
F7: Optimized Defualts
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