Hdi_Controller 8466520A02_A (Sheet 1) - Motorola MTM700 Detailed Service Manual

Tetra mobile radio 380-430 mhz (mt912) 806-870 mhz (mt712)
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Transceiver 800MHz (PCB No. 8486079Z02_A): SCHEMATICS, PCBs and PARTS LISTS
SIM_CARD
1
BGA1
SIM_POWER
2
BGA2
SIM_RESET
BGA3
3
SIM_DATA
I/O
SENSE
5
BGA4
SIM_CLOCK
SAP
SPIA_MISO
SPIA_MOSI
SPIA_CLK
SPIA_CS0_ADD
SPIA_CS1_FN_PCIC
SPIA_CS2_ODCT
SPIA
SPIA_CS3_ESC
SPIA_CS4_ABA
SPIB_MISO
SPIB
SPIB_MOSI
SPIB_CLK
SPIB_CS1_UART
SPIB_CS2
V3_2.775V_FLTR
U0101
K6F8016U6A
4
C0101
C0100
A2
EN_OE
0.1uF
.01uF
1
EB0#
G5
EN_WE
3
EB1
A1
CS2#-SRAM
LB
EB0
B2
UB
6
OE
CS2_
B5
CS1
A6
CS2
1
A3
B6
A0
DO
2
A4
C5
A1
D1
C6
A5
A2
D2
D5
B3
A3
D3
5
B4
E5
A4
D4
6
F5
C3
A5
D5
7
F6
C4
A6
D6
8
G6
D4
A7
D7
9
B1
H2
A8
D8
H3
C1
A9
D9
11
H4
C2
A10
D10
H5
D2
A11
D11
13
G3
E2
A12
D12
14
G4
F2
A13
D13
15
F1
F3
A14
D14
G1
16
F4
A15
D15
E4
A16
G2
18
D3
A17
NC1
NC
19
H6
H1
A18
NC2
NC
BGA106
FR_GND
BGA29
EXT- PTT
GP1_IN_ACC3
BGA30
EXP_REQ (UART)
INTERRUPT
EXP_REQ
BGA32
ON_OFF_CONTROL
BGA41
INT4 - Option_Select_1
INPUTS
OPT_SEL_1
BGA42
INT5 - Option_Select_2
OPT_SEL_2
BGA43
LV_DETECT
TP 0112
BGA44
MOD
MTM700 Mobile Radio / Detailed Service Manual
SIM_BUS(5:1)
DSP_STD goes to CODEC/UCM/DGAN_Module
BGA5
D16
SAP_STD
STDA
DSP_SRD goes to CODEC/UCM/DGAN_Module
BGA6
D13
SAP_SRD
SRDA
Serial Audio Port Clock
C15
AUDIO
SAP_CLK
SCKA
SAP_TDMA Support for UCM
B16
CODEC
UCM_SAP_FSYNC
SC0A
BGA9
SAP_TDMA Support for Digianswer Modul e
A16
DGAN_SAP_FSYNC
SC1A
BGA10
Serial Audio Port Frame Sync CODEC Suppor t
A15
SAP_FSYNC
SC2A
BGA11
B9
MISOA
BGA12
C9
MOSIA
BGA13
A9
SPI_CKA
ADDAC
BGA14
D9
SPICS0A
LVFRACN+PCIC
DSP I-A
BGA15
E11
SPICS1A
BGA16
ODCT
E10
SPICS2A
BGA17
ESCORT
E9
SPICS3A
BGA18
ABACUS
F7
SPICS4A
BGA19
C11
MISOB
BGA20
D12
MOSIB
BGA21
D11
SPI_CKB
EXP_UART_2
D10
DSP I-B
SPICS0B
EXP_UART
BGA22
C10
SPICS1B
BGA23
SPARE
B10
SPICS2B
A10
BGA147
SPICS3B
E12
BGA156
SPICS4B
HST_Addr(0:21)
0
HST_DATA(0:15)
J2
ADDR0
J1
ADDR1
J4
ADDR2
V3_2.775V_FLTR
3
L5
ADDR3
4
K6
ADDR4
C0102
0.1uF
5
J6
ADDR5
6
H6
ADDR6
7
G6
ADDR7
8
H5
ADDR8
BGA107
TP 0115
C0103
9
G5
ADDR9
.01uF
10
F5
ADDR10
11
H4
ADDR11
U0102
12
EXT_VPP
H1
ADDR12
28F320C3
13
H2
ADDR13
5
D7
14
H3
EN_CE
ADDR14
4
F8
0
15
E5
EN_OE
ADDR15
1
3
B3
16
G3
EN_WE
ADDR16
2
B4
17
EB1#
DNP
G4
0
R0101
EN_RP
ADDR17
A5
3
NU
18
F4
EN_WP
ADDR18
4
1
19
F1
ADDR19
5
WR _
1
0
20
D8
E7
F2
R0102
A0
DQ0
ADDR20
6
2
2 Meg 6x1
1
21
0
C8
F7
F3
A1
DQ1
ADDR21
0
7
3
2
B8
D5
T1
A2
DQ2
D0
4
3
1
C7
E5
T2
A3
FLASH
DQ3
D1
9
5
A8
F4
4
2
T3
A4
DQ4
D2
10
6
5
3
B7
D3
R3
EIM
11
A5
DQ5
D3
7
6
4
C6
E3
P3
12
A6
DQ6
D4
8
7
5
A7
F2
T4
A7
DQ7
D5
13
9
8
6
A3
D6
R4
A8
DQ8
D6
14
10
9
7
C3
E6
P4
A9
DQ9
D7
15
11
B2
F6
10
8
P5
A10
DQ10
D8
12
11
9
A2
D4
N5
A11
DQ11
D9
12
10
C2
E4
P6
A12
DQ12
D10
14
13
11
A1
F3
R6
A13
DQ13
D11
B1
D2
14
12
T6
A14
DQ14
D12
15
13
C1
E2
N6
A15
DQ15
D13
17
14
D1
N7
A16
D14
18
15
B6
C4
P7
A17
NC1
D15
19
B5
A18
20
A6
A19
C5
A20
1
3
4
5
6
MEM_CNTL(6:1)
RESET_OUT
INT0 - PTT
INT1 - EXP_REQ
INT2 - ON_OFF_CONTROL CH
INT4 - Option_Select_1
INT5 - Option_Select_2
RESET Low_Voltage_Detector
TP0101
USE ONLY WITH NEXT GENRATION PATRIOT
USB_CTRL_SIGNALS
5
4
3
2
1
A14
STDB
B14
BGA64
SRDB
C13
BGA65
SCKB
B13
BGA66
BASEBAND
SC0B
JTAG AND TEST
SMART CARD
A13
CODEC PORT
SC1B
C14
BGA68
SC2B
A12
SCKB2
B12
BGA70
SRDB2
A5
TOUT0
C5
TOUT1
D5
TOUT2
C6
TOUT3
B6
TOUT4
A6
TOUT5
LAYER 1
D6
TOUT6
TIMER
D7
TOUT7
C7
TOUT8
B7
TOUT9
B8
TOUT10
A8
TOUT11
D8
TOUT12
E6
TOUT13
E7
REDCAP2
TOUT14
E8
TOUT15
17x17mm BGA
K2
CLOCK
CKIL
K4
CKIH
AND PLL
L2
CKOH
M3
CKO
R10
PCAP
T10
PVCC
P10
PGND
N10
U0100-1
P1GND
Internal Pulldown
F16
(Note: U0100-2 on next page)
MUX_CTL
F13
CTSA_MCU_DE
G13
RTSA_IC2A_RESET_IN
G14
RXA_IC1_TDI
G15
UART-A
TXA_TDO
L12
UART-B
CTSB
K12
RTSB
SBEP
J12
RXB
K11
TXB
J13
ROW7_RI_SCKA_TCK
J16
ROW6_DCD_SC2A_DSP_DE
N13
COLUMN0
R14
COLUMN1
R15
COLUMN2
T14
KEYPAD
COLUMN3
R16
COLUMN4
P16
COLUMN5
P15
COLUMN6_OC1
P14
COLUMN7
L15
ROW0
K13
ROW1
K14
ROW2
K15
ROW3
J14
ROW4
J15
ROW5_IC2B
EMU AND
DEBUG
INTERRUPTS
R13
RESET_IN
P13
RESET_OUT
T13
STO
RESET_OUT
RESET_OUT
MOD
R0103
22K

HDI_Controller 8466520A02_A (Sheet 1)

NOTE: The register used to receive data (from the DSP) in the ADDAG is called
a "Transmit Data Register" and has an STD Pin name. The Register used to
transmit data to the DSP is called the "Receive Data Register" and has an SRD Pin Name.
The only way this makes sense is if you think of the data flow with respect to the radio
as a whole and NOT as a ABACUS/ADDAG to DSP serial interface.
STD Send Transmit I/Q Data to ADDAG
ADD_STD
SRD Receive I/Q Data from ABACUS
SSI_DOUT
ADDAG Serial Port Clock for Transmit Data
ADD_TXCLK
AUDIO_ATTN_CTRL
BBP
ADDAG Frame SYNC
ADD_FSYNC
ABACUS Frame SYNC
SSI_FSYNC
ABACUS Serial Port Clock for Receive Data
SSI_CLKOUT
SRDB2
BGA71
BGA72
BGA73
BGA74
BGA75
BGA77
BGA78
BGA79
BGA80
BGA81
BGA82
BGA83
BGA84
32.768 kHz Input
BGA85
16.8 MHz Input
BGA86
PWM2_1.8V_FLTR
R0104
47
E0100
Gen Port Ctrl Reg (GPCR)
GPCR = xxxxxxxx x00xxx00
NU
C0104
FR_GND
.01uF
BGA108
SYMBOL
DNP
PVCC
PIN NAME
BGA95
CTS
RTS
BGA88
RX
BGA89
TX
BGA91
RSB_CTS
NOTE: RESETS FROM THE BOTTOM CONNECTOR WILL ONLY BE POSSIBLE IF
BGA93
RSB_RTS
MUX_CTRL =1 AND THE 8-WIRE INTERFACE IS THUS SET TO JTAG MODE
BGA94
RSB_RX
BGA45
RSB_TX
ROW7
BGA46
ROW6
BGA47
BGA48
INT7
GP2_OUT_ACC4
BGA49
KEY_FAIL_OUT
INT6
GP3_OUT_ACC6
BGA50
KEY_FAIL_IN
GP3_IN_ACC6
BGA51
GP4_IN_ACC9
BGA52
GP5_IN_ACC10
BGA53
GP6_OUT_ACC12
BGA113
PWM
DNP
GP6_IN_ACC12
BGA56
BGA57
RS232 ENABLE
BGA58
BGA59
TEMP_SENSE
BGA60
GP8_OUT_ACC14
BGA61
GP8_IN_ACC14
STO
BGA154
BGA24
GP9_IN_ACC15
BGA153
GP9_OUT_ACC15
8.2.2 - 19
V3_2.775V
R0121
22K
LO_Driver_En
AGC_1_FE
ADD_TXE
PA_BIAS
PCIC_AD_SWTCH
ANT_EN
LO2_OUT
TOUT8
AGC_0_FE
TOUT_11
AGC_2_IF
TOUT_13
TOUT_15
32KHz_CLK
32.768 kHz Input
REF16.8_FN
16.8 MHz Input
16.8 MHz Clock Output
16.8MHz_OUT
MUX_CTRL=0
MUX_CTRL=1
Gen Port Ctrl Reg (GPCR)
GPCR = xxxxxxxx x11xxx11
GPCR (Bit7)=0
GPCR (Bit7)=1
8-Wire RS232
4-Wire RS23
2
SB9600
JTAG
ESSI
ESSI
BUSY_OU T
TP0116
CTS
CTS
MCU_DE
RS232_CTS
RTS
RTS
BUSY_IN (IC2)
RESET_IN
TP0117
RS232_RTS
RX
RX
RX
TDI
TP0118
RS232_R X
TX
TX
TX
TDO
TP0119
RS232_TX
TP0120
MUX_CTRL
RI
SCKA
SCKA
TCK
TP0121
RS232_RI
DCD
SC2A
SC2A
DSP_DE
TP0122
RS232_DCD
TP0123
DTR
SRDA
SRDA
TMS
RS232_DTR
DSR
STDA
STDA
TRST
TP0124
RS232_DSR
RESET_ABACUS
SSI_SYNCB
RESET_ODCT_ADD
RESET_OUT
RESET_OUT
TX_DETECT(SLUMP DETECT)
TX_DETECT
SOFT_TURN_OFF
AUDIO_IN
AUDIO_SENSE
ZWG0130877-A

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