Cpld Specification; Cpld Memory Map; Chip Id1 Register (Chipid1) - NXP Semiconductors T2080RDB-PC User Manual

Chapter 3

CPLD Specification

This section explains the CPLD registers.

3.1 CPLD Memory Map

Offset
address
(hex)
0

Chip ID1 register (CHIPID1)

1 Chip ID2 register (CHIPID2)
2 Hardware version register (HWVER)
3 Software version register (SWVER)
10 Reset control register (RSTCON)
11 Flash control and status register (FLHCSR)
12 Thermal control and status register (THMCSR)
13 Panel LED control and status register (LEDCSR)
14 SFP+ control and status register (SFPCSR)
15 Miscellanies control and status register (MISCCSR)
16 Boot configuration override register (BOOTOR)
17 Boot configuration register 1 (BOOTCFG1)
18 Boot configuration register 2 (BOOTCFG2)
3.1.1 Chip ID1 register (CHIPID1 )
Address: 0h base + 0h offset = 0h
Bit 0
Read
Write
Reset 0
QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 0, 04/2016
Freescale Semiconductor, Inc.
memory map
Register name
1 2
1 0
Width
Access
(in bits)
8
8
8
8
8
8
8
8
8
8
8
8
8
3 4
CHIPID1
1 0
Section/
Reset value
page
R 55h 3.1.1/37
R AAh 3.1.2/38
R See section 3.1.3/38
R See section 3.1.4/39
w1c See section 3.1.5/39
R/W See section 3.1.6/40
R/W See section 3.1.7/40
R/W See section 3.1.8/41
R/W See section 3.1.9/41
R/W See section 3.1.10/42
R/W See section 3.1.11/43
R/W See section 3.1.12/43
R/W See section 3.1.13/43
5 6
1 0
7
1
37