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Summary of Contents for NXP Semiconductors TJA1100
- Page 1 TR1329 TJA1100 Customer Evaluation Board - User Guide Rev. 01.20 — 31 January 2018 User Manual Document information Info Content Title TJA1100 Customer Evaluation Board - User Guide Author(s) Steffen Lorenz; Simon Zhu Department Systems & Applications Keywords TJA1100, 100BASE-T1, Ethernet, PHY...
- Page 2 TR1329 NXP Semiconductors Systems & Applications Revision history Date Description 20160112 Initial version 20160816 Updated for board revision V6, with latest EMC filter and ESD protection Fig. 1, 2, 4, 5, 6, 7, 8 updated Section 4.1: schematics updated 20180131...
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Page 3: Fig 1. Customer Phy Board Top View
1. Introduction This document describes the usage of the TJA1100 Customer Evaluation Board. The Board supports the evaluation of the TJA1100 with providing (MII) a 40-pins standard header (including MII/SMI/control signals/power supplies. Details can be found in section 2.3.1) with 2,54mm pinning distance to a host controller board, the bus interface (MDI) including a srew terminal (SMKDS) connector as well as needed components for the power supply and operation. -
Page 4: Acronyms
TR1329 NXP Semiconductors Systems & Applications 1.1 Acronyms Table 1. Acronyms used in the document Acronym Description Battery Direct Current Ground Medium Access Controller Medium Dependent Interface Medium Independent Interface Physical Microcontroller TR1329 All information provided in this document is subject to legal disclaimers. -
Page 5: Fig 2. Pin 1 Location
2. Board Setup 2.1 PHY Assembly The TJA1100 is provided in a HVQFN-36 package (8x8sqmm). In case the TJA1100 on the customer evaluation board must be changed, please ensure the correct placement. The Pin 1 is located at the bottom right and is marked with a small white arrow (see Fig Fig 2. - Page 6 JP17 Configuration of PHYAD1 The TJA1100 can be configured as Master or Slave, as well as Managed or Autonomous operation. When the TJA1100 is configured for Autonomous operation, the PHY will automatically enter Normal mode and activate the link on power-on without further interaction with a host controller.
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Page 7: Fig 3. Bit Strapping Jumper Settings
TR1329 NXP Semiconductors Systems & Applications Fig 3. Bit Strapping Jumper Settings TR1329 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved. Rev. 01.20 — 31 January 2018 User Manual 7 of 19... -
Page 8: Fig 4. Bit Strapping Jumpers On Pcb
TR1329 NXP Semiconductors Systems & Applications Fig 4. Bit Strapping Jumpers on PCB TR1329 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved. Rev. 01.20 — 31 January 2018 User Manual... -
Page 9: Fig 5. Mii Connector Location And Pinning Order
TR1329 NXP Semiconductors Systems & Applications 2.3 Connectors & LEDs 2.3.1 MII Connector For the MII a double row, 40 pin 2.54x2.54mm male header P1 (Fig 5) is used. At the PCB (Fig 5Error! Reference source not found.) the pinning order is marked. - Page 10 TR1329 NXP Semiconductors Systems & Applications Table 6. MII Connector Pinning Signal Signal TJA1100_WAKE TJA1100_INH TJA1100_RSTN TJA1100_INT TJA1100_MDC TJA1100_MDIO TJA1100_EN TJA1100_TXER TJA1100_TXD0 TJA1100_TXD1 TJA1100_TXD2 TJA1100_TXD3 TJA1100_TXEN TJA1100_TXCLK TJA1100_RXCLK TJA1100_RXD0 TJA1100_RXD1 TJA1100_RXD2 TJA1100_RXD3 TJA1100_RXDV TJA1100_RXER TR1329 All information provided in this document is subject to legal disclaimers.
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Page 11: Fig 6. Mdi Pinning Order
TR1329 NXP Semiconductors Systems & Applications 2.3.2 MDI Connector For the MDI interface, a two position PCB terminal connector (SMKDS, 5/2-2.54) from Phoenix Contact is used, and the details are given in Fig 6. Fig 6. MDI Pinning Order TR1329 All information provided in this document is subject to legal disclaimers. -
Page 12: Fig 7. Leds On The Board
Description LED1 TJA1100 3V3 Power Supply Status (ON: 3V3 is present) LED2 TJA1100 Local Wake-up Status (Flashing: a Local Wake-up is detected) LED3 TJA1100 Battery Power Supply Status (ON: Battery is present) LED4 TJA1100 1V8 Digital Power Supply Status (ON: 1V8 is present) TR1329 All information provided in this document is subject to legal disclaimers. -
Page 13: Reference
TR1329 NXP Semiconductors Systems & Applications 3. Reference [1] TJA1100 Datasheet, Version 3, 23 May, 2017 TR1329 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved. Rev. 01.20 — 31 January 2018... -
Page 14: Appendix
TR1329 NXP Semiconductors Systems & Applications 4. Appendix 4.1 The TJA1100 Customer Evaluation Board Schematics TR1329 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved. Rev. 01.20 — 31 January 2018... - Page 15 TR1329 NXP Semiconductors Systems & Applications TR1329 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved. Rev. 01.20 — 31 January 2018 User Manual 15 of 19...
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Page 16: Legal Information
Semiconductors products in order to avoid a default of the applications and In no event shall NXP Semiconductors be liable for any indirect, incidental, the products or of the application or use by customer’s third party punitive, special or consequential damages (including - without limitation - customer(s). -
Page 17: Table Of Contents
TR1329 NXP Semiconductors Systems & Applications 6. List of figures Fig 1. Customer PHY Board Top View ......3 Fig 2. Pin 1 Location ........... 5 Fig 3. Bit Strapping Jumper Settings ......7 Fig 4. Bit Strapping Jumpers on PCB ......8 Fig 5. -
Page 18: List Of Tables
TR1329 NXP Semiconductors Systems & Applications 7. List of tables Table 1. Acronyms used in the document ....... 4 Table 2. Bit Strapping PHY-address ....... 6 Table 3. Bit Strapping Master/Slave Configuration ..6 Table 4. Bit Strapping Managed/autonomous Operation 6 Table 5. -
Page 19: Contents
MII Connector ............. 9 2.3.2 MDI Connector ..........11 2.3.3 LEDs ..............12 Reference ............13 Appendix ............14 The TJA1100 Customer Evaluation Board Schematics............14 Legal information ..........16 Definitions ............16 Disclaimers............16 Licenses ............16 Patents ............. 16 Trademarks ............
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