Feature Connector (J28) - Kontron mITX-BDW-U Manual

Max. 0.5 A PWR
Note:
The mITX-BDW-U on-board LVDS connector supports single and dual channel, 18/24 bit SPWG
panels up to a resolution of 1600x1200 or 1920x1080 and with limited frame rate up to 1920x1200.
Signal Description – LVDS Flat Panel Connector:
SIGNAL
LVDS A0..A3
LVDS ACLK
LVDS B0..B3
LVDS BCLK
BKLTCTL
BKLTEN#
VDD ENABLE
LCDVCC
DDC CLK
Notes:
Windows API will be available to operate the BKLTCTL signal. Some Inverters have a limited
voltage range 0- 2.5V for this signal: If voltage is > 2.5V the Inverter might latch up. Some Inverters
generates noise on the BKLTCTL signal, causing the LVDS transmission to fail (corrupted picture
on the display). By adding a 1Kohm resistor in series with this signal, mounted at the Inverter end
of the cable kit, the noise is limited and the picture is stable.
If the Backlight Enable is required to be active high then, check the following BIOS Chipset setting:
Backlight Signal Inversion = Enabled.
09.12.

FEATURE CONNECTOR (J28)

IOH/
NOT PULL
E U/D
IOL
2 2M/ -
25/25
-
mA
25/25
-
mA
MITX-BDW-U (KTD-NO886-B)
GND 39
TYPE SIGNAL
CASE_
I
OPEN#
O S5#
O PWR_OK
www.kontron.com
40 GND
DESCRIPTION
LVDS A Channel data
LVDS A Channel clock
LVDS B Channel data
LVDS B Channel clock
Backlight control (1), PWM signal to implement
voltage in the range 0-3.3 V
Backlight Enable signal (active low) (2)
Output Display Enable.
VCC supply to the display. 5 V or 3.3 V (1 A Max.)
selected in BIOS setup menu. Power sequencing
depends on LVDS panel selection. (Shared with
eDP connector)
DDC Channel Clock
PIN SIGNAL
1 2
SMBC
3 4
SMBD
5 6
EXT_BAT
PWR Max. 0.5 A
IOH/
TYP PULL
E U/D
IOL
/4 mA 10K/
/4 mA 10K/
PWR - -
NOT
E
1
1
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