Differential Sma Clocks; User Leds (Active High) - Xilinx Virtex-II Pro ML320 User Manual

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7. Differential SMA Clocks

There are four pairs of 50Ω SMA connectors that can be used (with 100Ω termination) to
connect to an external function generator. These connect to the FPGA pins as shown in
Table
Table 7: Differential Clock Pin Connections
ML320
Label
Clock Name
J21 CLK_BREF2_TOP_P
J23 CLK_BREF2_TOP_N
J42 CLK_BREF_BOT_P
J41 CLK_BREF_BOT_N
J16 CLK_DIFF_TOP_P
J19 CLK_DIFF_TOP_N
J47 CLK_DIFF_BOT_P
J48 CLK_DIFF_BOT_N

8. User LEDs (Active High)

There are 16 or 20 active-high LEDs, as shown in
user I/O pins on the FPGA. These LEDs can be used to indicate status or any other
purpose the user sees fit.
Table 8: User LEDs - LED Row 1
18 www.xilinx.com
1-800-255-7778
7. These SMA connectors can also be used as eight single-ended clock inputs.
Pin Clock Name
D12 CLK_BREF_TOP_N
C12 CLK_BREF_TOP_P
W11 CLK_BREF2_BOT_N
Y11 CLK_BREF2_BOT_P
E11 CLK_DIFF_TOP_N
F11 CLK_DIFF_TOP_P
V12 CLK_DIFF_BOT_P
U12 CLK_DIFF_BOT_N
LED ROW 1
DS15 V17
DS13 V16
DS12 W16
DS11 Y16
DS10 U14
DS9 V14
DS8 W14
DS14 W13
DS26
DS27
ML321
Pin
C14
B14
AD13
AE13
D13
E13
AB14
AC14
Table 8
ML320 ML321
AC19
AD19
AE19
AF19
Y18
AA18
AC20
AA20
AA19
Y19
Virtex-II Pro ML320, ML321, ML323 Platform
UG033 (v2.1) P/N 0402071 March 19, 2004
ML323
Clock Name
CLK_BREF_TOP_N J18
CLK_BREF_TOP_P H18
CLK_BREF2_BOT_N AK17
CLK_BREF2_BOT_P AL17
CLK_DIFF_TOP_N D17
CLK_DIFF_TOP_P E17
CLK_DIFF_BOT_P AH18
CLK_DIFF_BOT_N AJ18
and Table 9, page 19, connected to
ML323
AG25
AH25
AK27
AL27
AH26
AK29
AK28
AF25
AE24
AF24
Pin