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scalable IA-32-based server, which has become a well-accepted and tested
solution in medium to large enterprises.
A replacement to the xSeries 380, the first xSeries server with a 64-bit
architecture targeted, tested, and proven by software and hardware
developers.
Unlike competitors without such background, IBM put many years of
invaluable experience with 64-bit technology (IBM pSeries™ and zSeries™
servers) into the development of the x450.
All of these advantages make the xSeries 450 production enterprise-level server
a viable alternative to RISC-based architectures, while protecting many years of
investments and knowledge gained from IA-32 platform development.
Intel expects the Itanium Architecture to be a product base for the next 25 years
or more.
The Itanium 2 processor used in the x450 is based on the
Instruction Computing
technologies, features, and capabilities that make it ideal for the high-end server
and workstation markets. EPIC allows users to take advantage of its large
memory addressability and parallel execution capabilities. The chip also supports
intelligent prediction and speculation of events to deduce redundancy and
improve performance. The Itanium's floating point engine enhances performance
for complex computations that are required for data-mining, scientific, and
technical applications.
The Itanium 2 processor is the second in a family of Intel enterprise-class
processors. For more information about the Intel Itanium 2 processor, see:
http://www.intel.com/products/server/processors/server/itanium2/
Intel Itanium Architecture-based microprocessors have the following features:
Advanced parallelism
High performance requires parallel execution, which is either very limited or
hardly achieved in today's architecture. The traditional PC systems are not
designed for parallelism, which is critical for current demanding applications
(for example databases and application servers).
Today's processors using limited parallelism are often 60% idle. When source
code is compiled on today's systems, the result of the compilation is
sequential machine code. A regular (non-Itanium processor family) compiler
takes sequential code and examines and optimizes it for parallelism but then
has to regenerate sequential code, but in such a way that the processor can
re-extract the parallelization from it. The processor will then be required to
read this implied parallelism from the machine code, re-build it, and execute it.
IBM ^ xSeries 450 Planning and Installation Guide
36
(EPIC) architecture, which incorporates a number of new
Explicitly Parallel
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