IBM xSeries 450 Planning And Installation Manual page 26

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Figure 1-6 Dual-pumped frontside bus
This increases the performance of the frontside bus. The end result is an
effective burst throughput of 6.4 GBps (128-bit wide data path running at 400
MHz), which can have a substantial impact, especially on TCP/IP-based LAN
traffic. This is opposed to the Itanium processor, which had a burst throughput
of only 2.1 GBps (64-bit wide data path running at 266 MHz).
Explicitly Parallel Instruction Computing (EPIC)
EPIC technology, developed by Intel and HP, leads to more efficient, faster
processors because it eliminates numerous processing inefficiencies in
current processors and attacks the perennial data bottleneck problems by
increasing parallelism, rather than simply boosting the raw "clock" speed of
the processor.
Specifically, in today's 32-bit processors, much of the instruction
scheduling--the order in which computing instructions are executed--is done
on the chip itself, leading to a great deal of overhead and slowing down overall
processor performance. Moreover, today's processors are plagued by
instruction flow problems since the processor often has to stop what it's doing
and reconstruct the instruction flow due to inherent inefficiencies in instruction
handling.
EPIC makes the instruction scheduling more intelligent and handles much of
the scheduling off-chip, in the compiler program, before feeding "parallelized"
instructions to the Itanium 2 processor for execution. The parallelized
instructions allow the chip to process a number of instructions simultaneously,
increasing performance. A compiler prepares instructions for execution on the
processor.
The Itanium 2 architecture is based on EPIC technology and has the following
features:
– Provides faster online transaction processing
– Has the capability to execute multiple instructions simultaneously,
processing more data and allowing more users
Enables faster calculations and data analysis
Allows for faster storage and movement of large models (CAD, CAE)
Speeds up simulation and rendering times
IBM ^ xSeries 450 Planning and Installation Guide
12
200 MHz clock

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