Block Diagram Video - Philips EL1.1U Service Manual

Block Diagrams, Test Point Overviews, and Waveforms

Block Diagram Video

VIDEO
B03
B02B MAIN TUNER MPIF MAIN:
1T04
TD1336/FGHP
12 IF-ANA IF-ANA 2
IF-OUT
7T13
LA7795T-E
1T01
MAIN HYBRID 14 1 2 7
7
IF-1
TUNER
15 6
14 8 3
IF-2
in out
SAW 44MHz
AGC COTROL
4
FM-T 7T12
13
IF-AGC
4
B02A
CHANNNEL DECODER
7T22
NXT2004
CVBSOUTIF-MAIN
DTV CABLE AND FAT-IF-AGC-MAIN
34
TERRESTRIAL
38 AUX-IF-AGC AV1_CVBS
RECEIVER
N.C.
8 FAT-ADC-INN
QAM 8VSB
7
ADC ADC FAT-ADC-INP
Demodulator
FEC
AV2_Y-CVBS
B07C
48 FM-TRAP
AV2_C
Micro-
B07C
GPIO
7 IRQ-FE-MAIN
Controller
B05A
QPSK
ADC
Demodulator
29
AV7_Y-CVBS
B07C
1T11
30 25M14
MPEG_DATA
TO
DV1F-DATA(0-7) B05C
VIPER
D SIDE I/O
1002
(1302) 1M36
(1304) 1M36
FRONT_Y-CVBS_IN 2 2
FRONT_Y-CVBS
VIDEO
4 4 FRONT_C
1001
(1301)
1
3
FRONT_C_IN
S VIDEO 5
4
B07A HDMI +SUPPLY
2
1I06
( ) 26" - 32"
B07C
ANALOG I/O
1I04
PR1
PR
B07b
PB1
PB B07b
AV1
Y1
HDMI
Y
B07b
CONNECTOR
AV7_Y-CVBS
VIDEO 1B02
B03a
IN
1I03
PR
PR B07b
PB
PB
B07b
AV2
Y
Y B07b
AV1_CVBS
VIDEO
B03a
IN
1I02
(1I00)
N.C.
AV2_Y-CVBS
VIDEO N.C.
B03a
B07A
AV3
B07A
1I01 B07A
1
B07A
3
AV2_C
S VIDEO 5 B07A
B03a
4 B07A
2
B07A
B07A
EL1.1U AA
7A00
PNX3000HL
B03B
B03C IF
1A10
SUPPLY
7 107 VIFINP
SOUND GROUP
LPF
TRAP DELAY
108 VIFINN
8
SUPPLY
QSS
QSSOUT
99 SIFINP
BPF LPF
DIGITAL
100 SIFINN
BLOCK
TO AM INTERNAL
LPF AUDIO SWITCH
7A11
EF 3A17
CVBSOUTIF
5 120
CVBS-OUTA
B03A
CVBS/Y RIM LPF
SOURCE SELECTION
CVBS-OUTB
C L A M P
C-PRIM
123 CVBS-IF
MPIF
126
CVBS1
1
CVBS2
12 CVBS_DTV
STROBE1N 60
A
+ DATA
4 CVBS|Y3 STROBE1P 61
D
LPF
LINK
DATA1N 62
5 C3 1
Yyuv
2FH
DATA1P 63
8 CVBS|Y4
9 C4
STROBE3N
15 Y_COMB A STROBE3P
DATA
CLAMP
LINK
D
16 C_COMB
DATA3N
3
2nd
SIF DATA3P
25 R|PR|V_1
CVBS SEC A/D
Yyuv
YUV
26 G|Y|Y_1 2Fh
RGB
A
Yyuv STROBE2N
LEVEL
27 B|PB|U_1
D
ADAPT
U STROBE2P
U,V DATA
CLAMP
INV.
30 R|PR|V_2
A LINK
PAL
V DATA2N
2
D
31 G|Y|Y_2
DATA2P
MONO SEC.
32 B|PB|U_2
CLP PRIM
TIMING
CLP SEC
CIRCUIT
CLP yuv
B07B HDMI: I/O + CONTROL
7B50
TDA9975HS
1
ARX2+ 180
RX2+A
3 ARX2- 179
RX2-A
HDMI
4 ARX1+ 174
RX1+A
6 Termination
ARX1- 173
Video
RX1-A
resistance
7
ARX0+ 168 output
RX0+A control
formatter
9 ARX0- 167
RX0-A
10 ARXC+ 162
RXC+A
12
ARXC- 161
RXC-1
15 ARX-DCC-SCL
16 ARX-DCC-SDA
19 7B20
ARX-HOTPLUG
HPD-HIRATE
B05A
VHREF
RX2+B
timing
Upsample
RX2-B generator
RX1+B Derepeater
Termination
RX2-B resistance
control
RX0+B
HDMI
HDCP
RX0-B
receiver
RXC+B
I2C slave
RXC-B
interface
HSCL B
HSDA B
Line time
measuremebt
Activity
H-SYNC-VGA 131
Sync
HSYNC
detection &
V-SYNC-VGA 128
seperator
VSYNC
sync selec.
Y 90
Y1 88
G/Y Slicers
Clocks
PR 96 generator
PR1 94 R/PR
Y 81
ADC
Y1 79 G/Y
PB 68
PB1 66 B/PB
6. EN 40
B04 PNX 2015:
7J00
PNX2015E
B04C TUNNELBUS
PNX2015
14
+5V
28
35
SCL-DMA North tunnel
44
43 SDA-DMA
19
N.C.
B04A AUDIO/VIDEO
22
N.C.
Memory
based scaler
R4
STROBE1N-MAIN
AVP1_DLK1SN
STROBE1P-MAIN
R3 AVP1_DLK1SP AVIP-1
DATA1N-MAIN R2
AVP1_DLK1DN
DATA1P-MAIN R1
AVP1_DLK1DP
50 STROBE3N-MAIN
N4 AVP1_DLK3SN
COLUMBUS
51 STROBE3P-MAIN N3
AVP1_DLK3SP
3D Comb
52 DATA3N-MAIN N2 filter and
AVP1_DLK3DN
noice
53
DATA3P-MAIN N1 reduction
AVP1_DLK3DP
55 STROBE2N-MAIN
P4 AVP1_DLK2SN
56 STROBE2P-MAIN P3 AVIP-2
AVP1_DLK2SP
57 DATA2N-MAIN P2
AVP1_DLK2DN
123 DATA2P-MAIN
P1 AVP1_DLK2DP
46 HV-PRM-MAIN M3
AVP1_HVINFO1
40 CLK-MPIF M4
MPIF_CLK
AV2_FBL L2
Video MPEG
AVP2_HSYNCFBL2
N.C.
decoder
AV6_VSYNC G2
AVP2_VSYNC2
N.C.
B04B DV I/O INTERFACE
DV4_DATA_0 T0 9
DV4-DATA(0-7)
VIP
DV5-DATA(0-7)
DV5_DATA_0 T0 9
2 DV4-CLK AK8
1 DV-HREF AH9
DV-HREF
DV-VREF AJ9
201
DV-VREF
207 DV-FREF AK9
DV-FREF
144 SDA-MM-BUS1
143 SCL-MM-BUS1
B04E PNX 2015: STANDBY
B4E
& CONTROL
STANDBY
7LA7
M25P05
SPI-SDO AK10
5
B04D
6 SPI-CLK AH10
512K STANDBY DDR INTERFACE
1 SPI-CSB AG10
PROCESSOR
FLASH
SPI-WP
3 AJ27
See
Block digram
Control
AJ12
1LA0
16M
AH12
B05
VIPER:
7V00
PNX8550
B05C B05B
TUNNELBUS MAIN MEMORY
TUN-VIPER-RX-DATA
VIPER
TUN-VIPER-TX-DATA
Tunnel Memory
South tunnel
controller
TUN-VIPER-RX-DATA
TUN-VIPER-RX-DATA
TUN-VIPER-TX-CLKN
TUN-VIPER-TX-CLKP
DVD
CSS
B05C
2D DE
AUDIO/VIDEO
2-Layer
secondary
VO-2
video out
Dual SD
AF30 DV2A-CLK Temporal
DV2_CLK single HD C4
noise redux
AK28 DV3F-CLK
MPE2 decoder
DV3_CLK
A2
From 250Mhz
B02A MIPS32
CPU
CHANNEL
DECODER
Scaler and
de-interlacer
MUX
DV1_DATA(0-9) DV1F-DATA(0-7)
1SD+1HD
YUV
5 Layer
Video Video in
primary
TS
DV2_DATA(0-9)
video out
router
HD/VGA/
Dual
656
con
acces
DV3_DATA(0-9) DV3F-DATA (0-7)
J29 MP-OUT-HS
RGB_HSYNC
VO-1
J28 MP-OUT-VS DV-OUT-VS
RGB_VSYNC
J30 MP-CLKOUT DV-CLK-IN
RGB_CLK_IN
J27 MP-OUT-FFIELD
RGB_UD
K26 MP-OUT-DE DV-OUT-DE
RGB_DE
RIN (0-9) MP-ROUT(0-9) DV-ROUT
GIN (0-9) MP-GOUT(0-9) DV-GOUT
BIN (0-9) MP-BOUT(0-9) DV-BOUT
B04G
LVDS_TX
B26 TXPNXA-
LVDS_AN
TXPNXA+
C26
LVDS_AP
A25 TXPNXB-
LVDS_BN
B25 TXPNXB+
LVDS_BP
D25 TXPNXC-
LVDS_CN
E25 TXPNXC+
LVDS_CP
TXPNXCLK-
C23
LVDS_CLKN
D23 TXPNXCLK+
LVDS_CLKP
TXPNXD-
B24
LVDS_DN
C24 TXPNXD+
LVDS_DP
E24 TXPNXE-
LVDS_EN
F24 TXPNXE+
LVDS_EP
7L50
K4D261638F
PMX-MA(0-12)
PMX-MA
DDR
Memory
PNX-MDATA SDRAM
PNX-MDATA
controller
(0-15)
128Mx16
PNX-MCLK-P
A17 45
MCLK_P
PNX-MCLK-N
A16 46
MCLK_N
B05B VIPER: MAIN MEMORY
7V01
K4D551638F
DDR
SDRAM 1
8Mx16
MM_DATA
7V02
K4D551638F
DDR
MM_A(0-12)
SDRAM 2
8Mx16
1H00
27M
B06 B04G
VIDEO-DAC
7G40
ADV7123KSTZ140
VIDEO
DV-ROUT
DAC
DV-GOUT
1D50
DV-BOUT
34 1
AV-ROUT
2
32 AV-GOUT
3
28 AV-BOUT
ANALOG
OUTPUT
(Reserved for PTV)
12
24
11
(Reserved for PTV)
VIPER/PNX 2015:
DISPLAY INTERFACE
1P06 (26" LCD)
1G50
1 1
VDISP
2 2
3 3
4 4
12 10
5J50
13 12
15 13
5J52
16 15
18 18
5J54
19 20
LVDS
CONNECTOR
TO SCREEN
21 21
5J56
22 23
24 26
5J58
25 28
27
5J60
28
7
CTRL-DISP1
8
CTRL-DISP2
ONLY
9 9
CTRL-DISP3 FHP SETS
CTRL-DISP4 10
30 29
SCL-I2C4
31 30
SDA-I2C4
G_16290_006.eps
020206