Block Diagram Video - Philips 51PP9200D/37 Service Manual

Block Diagrams, Test Point Overviews, and Waveforms

Block Diagram Video

VIDEO
B2B MAIN TUNER B3 MPIF MAIN:
1T04 1A10
TD1336/FGHP
12 IF-ANA IF-ANA 2
IF-OUT
7T13
LA7795T-E
1T01
MAIN HYBRID
14 1 7 2 7
IF-1
TUNER
15 8 6
14 3
IF-2
in out
SAW 44MHz
AGC COTROL
4
7T12
FM-T
13
IF-AGC 7A11
4
B2A
CHANNNEL DECODER
7T22
NXT2004
CVBSOUTIF-MAIN
DTV CABLE AND FAT-IF-AGC-MAIN
34
TERRESTRIAL
38 AUX-IF-AGC AV1_CVBS
RECEIVER
N.C.
8 FAT-ADC-INN
QAM 8VSB
7
ADC ADC FAT-ADC-INP
Demodulator
FEC
AV2_Y-CVBS
B07C
48 FM-TRAP
AV2_C
Micro- B07C
GPIO
7
IRQ-FE-MAIN
Controller
B05A
QPSK
ADC
Demodulator
29
AV7_Y-CVBS
B07C
1T11
25M14
30
MPEG_DATA
TO
DV1F-DATA(0-7) B05C
VIPER
G
SIDE AV
1301
1305 1M36
FRONT_Y-CVBS_IN 2 2 FRONT_Y-CVBS
VIDEO
4 4
FRONT_C
1302
1
3
S VIDEO 5 FRONT_C_IN
4
B7A HDMI +SUPPLY
2
1I06
B7C
ANALOG I/O
1I04
10
PR1
PR
B07b 12
15
PB1
PB
B07b 16
AV1
Y1
19
HDMI
Y
B07b
CONNECTOR
AV7_Y-CVBS
VIDEO 1B02
B03a
IN
1I03
PR
PR
B07b
PB
PB
B07b
AV2
Y
Y
B07b
AV1_CVBS
VIDEO
B03a
IN
1I00
N.C.
AV2_Y-CVBS
N.C.
VIDEO B03a
B07A
AV3
B07A
1I01 B07A
1
B07A
3
AV2_C
S VIDEO 5 B07A
B03a
4
B07A
2
B07A
B07A
EBJ1.0U
7A00
PNX3000HL
B3C IF B3B
SUPPLY
7 107 VIFINP
SOUND GROUP
LPF
TRAP DELAY
108 VIFINN
8
SUPPLY
QSS QSSOUT
99 SIFINP
BPF
LPF
DIGITAL
SIFINN
100
BLOCK
TO AM INTERNAL
AUDIO SWITCH
LPF
EF 3A17
5 120 CVBSOUTIF
CVBS-OUTA
B3A
CVBS/Y RIM LPF
SOURCE SELECTION
CVBS-OUTB
C L A M P
C-PRIM
123 CVBS-IF
MPIF
126
CVBS1
1
CVBS2
12 CVBS_DTV
STROBE1N 60
A
+
DATA STROBE1P 61
4 CVBS|Y3
D
LPF
LINK
1 DATA1N 62
5 C3
Yyuv
2FH
DATA1P 63
8 CVBS|Y4
9 C4
STROBE3N
15 Y_COMB
A STROBE3P
CLAMP DATA
D LINK
16 C_COMB
DATA3N
3
2nd
SIF DATA3P
25 R|PR|V_1
A/D
CVBS SEC
Yyuv
YUV
26 G|Y|Y_1 2Fh
RGB
A
Yyuv STROBE2N
LEVEL
27 B|PB|U_1
D
ADAPT
U U,V DATA STROBE2P
CLAMP
INV.
30 R|PR|V_2
A LINK
PAL
V DATA2N
2
31 G|Y|Y_2 D
DATA2P
MONO SEC.
32 B|PB|U_2
CLP PRIM
TIMING
CLP SEC
CIRCUIT
CLP yuv
B7B HDMI: I/O + CONTROL
7B50
TDA9975HS
1
ARX2+ 180
RX2+A
3
ARX2- 179
RX2-A
HDMI
4 ARX1+ 174
RX1+A
6 ARX1- 173 Termination
Video
RX1-A
resistance
7 ARX0+
168 output
RX0+A control
9 formatter
ARX0- 167
RX0-A
ARXC+ 162
RXC+A
ARXC- 161
RXC-1
ARX-DCC-SCL
ARX-DCC-SDA
7B20
ARX-HOTPLUG
HPD-HIRATE
B5A
VHREF
RX2+B
timing
Upsample
RX2-B generator
RX1+B Derepeater
Termination
RX2-B resistance
control
RX0+B
HDMI
HDCP
RX0-B
receiver
RXC+B
I2C slave
RXC-B
interface
HSCL B
HSDA B
Line time
measuremebt
H-SYNC-VGA 131 Activity
HSYNC Sync
detection &
128
V-SYNC-VGA seperator
VSYNC sync selec.
Y 90
Y1 88
G/Y Slicers
Clocks
PR 96 generator
PR1 94 R/PR
Y 81 ADC
Y1 79 G/Y
PB
68
B/PB
PB1 66
6. 29
B4
PNX 2015:
7J00
PNX2015E
B4C TUNNELBUS
PNX2015
14
+5V
28
35
SCL-DMA North tunnel
44
43
SDA-DMA
19
N.C.
B4A AUDIO/VIDEO
22
N.C.
Memory
based scaler
R4
STROBE1N-MAIN AVP1_DLK1SN
STROBE1P-MAIN R3 AVIP-1
AVP1_DLK1SP
DATA1N-MAIN R2
AVP1_DLK1DN
R1
DATA1P-MAIN
AVP1_DLK1DP
50 STROBE3N-MAIN N4
AVP1_DLK3SN
COLUMBUS
51 STROBE3P-MAIN
N3 AVP1_DLK3SP
3D Comb
52 DATA3N-MAIN filter and
N2 AVP1_DLK3DN
noice
53 DATA3P-MAIN N1 reduction
AVP1_DLK3DP
55 STROBE2N-MAIN
P4 AVP1_DLK2SN
56 STROBE2P-MAIN P3 AVIP-2
AVP1_DLK2SP
DATA2N-MAIN
57 P2 AVP1_DLK2DN
123 DATA2P-MAIN P1
AVP1_DLK2DP
HV-PRM-MAIN M3
46
AVP1_HVINFO1
40 CLK-MPIF M4
MPIF_CLK
AV2_FBL L2
Video MPEG
AVP2_HSYNCFBL2
N.C.
decoder
AV6_VSYNC G2
AVP2_VSYNC2
N.C.
B4B DV I/O INTERFACE
DV4_DATA_0 T0 9
DV4-DATA(0-7)
VIP
DV5-DATA(0-7)
DV5_DATA_0 T0 9
2 DV4-CLK
AK8
1 DV-HREF AH9
DV-HREF
DV-VREF
201 AJ9
DV-VREF
207 DV-FREF AK9
DV-FREF
SDA-MM-BUS1
144
143 SCL-MM-BUS1
B4E
PNX 2015: STANDBY
B4E
& CONTROL
STANDBY
7LA7
M25P05
SPI-SDO AK10
5
B4D
SPI-CLK
6 AH10
512K STANDBY
DDR INTERFACE
1 SPI-CSB AG10 PROCESSOR
FLASH
SPI-WP AJ27
3
See
Block digram
Control
AJ12
1LA0
16M
AH12
B5 VIPER:
7V00
PNX8552
B5C B5B
MAIN MEMORY
TUNNELBUS
TUN-VIPER-RX-DATA
VIPER
TUN-VIPER-TX-DATA
Tunnel Memory
South tunnel
controller
TUN-VIPER-RX-DATA
TUN-VIPER-RX-DATA
TUN-VIPER-TX-CLKN
TUN-VIPER-TX-CLKP
DVD
CSS
B5C
2D DE
AUDIO/VIDEO
2-Layer
secondary
VO-2
video out
Dual SD
AF30 DV2A-CLK Temporal
DV2_CLK single HD C4
noise redux
AK28 DV3F-CLK
MPE2 decoder
DV3_CLK
A2
From 250Mhz
B2A MIPS32
CPU
CHANNEL
DECODER
Scaler and
de-interlacer
MUX
DV1_DATA(0-9) DV1F-DATA(0-7)
1SD+1HD
YUV
5 Layer
Video Video in
primary
TS
DV2_DATA(0-9) video out
router
HD/VGA/
Dual
656
con
acces
DV3_DATA(0-9) DV3F-DATA (0-7)
J29 MP-OUT-HS
RGB_HSYNC
VO-1
J28 MP-OUT-VS DV-OUT-VS
RGB_VSYNC
J30 MP-CLKOUT DV-CLK-IN
RGB_CLK_IN
J27 MP-OUT-FFIELD
RGB_UD
MP-OUT-DE
K26 DV-OUT-DE
RGB_DE
RIN (0-9) MP-ROUT(0-9) DV-ROUT
GIN (0-9) MP-GOUT(0-9) DV-GOUT
BIN (0-9) MP-BOUT(0-9) DV-BOUT
M3
HOP
7600
TDA9332H/N3
1612
1 R 30
2 G 31
LVDS_TX
3
B 32
B26
LVDS_AN
C26
LVDS_AP
A25
LVDS_BN R_OSD 35
B25
LVDS_BP
G_OSD 36
D25
LVDS_CN 37
B_OSD
E25
LVDS_CP
C23
M4
LVDS_CLKN CONVERGENCE
D23
LVDS_CLKP PROCESSOR
7600
3306
RED_uP
B24 TDA9332H/N3
LVDS_DN
3307
C24
M2 GRN_uP
LVDS_DP
PAINTER
3309
BLUE_uP
E24
LVDS_EN CONVERGENCE
RED_ST
16
F24
LVDS_EP
EF
GRN_ST 17
7L50
BLUE_ST 16
K4D261638F
PMX-MA(0-12)
PMX-MA
DDR
SYNC_H 27
Memory
SDRAM
PNX-MDATA
controller PNX-MDATA
SYNC_V
28
(0-15) 128Mx16
A17 PNX-MCLK-P 45
MCLK_P
A16 PNX-MCLK-N 46
MCLK_N
B5B VIPER: MAIN MEMORY
7V01
K4D551638F
DDR
SDRAM 1
8Mx16
MM_DATA
7V02
K4D551638F
DDR
MM_A(0-12)
SDRAM 2
8Mx16
1H00
27M
B6 B4G
VIDEO-DAC
7G40
ADV7123KSTZ140
VIDEO
DV-ROUT
DAC
DV-GOUT
1D50
DV-BOUT
34 1
AV-ROUT
2
32 AV-GOUT
3
28 AV-BOUT
12
24
11
1702
7702
HOP
EF To 1210
40 2
D
CRT R
TV DISPLAY
7712 1710
PROCESSOR To 1210
EF
41 2
D
CRT G
7712 1720
To 1210
EF
2
42
D
CRT B
M5
CONVERGENCE OUTPUT
7044 7045
STK392 STK392 1005
RV-OUT 1
RV
RV-RET 2
TO RED
3
RH-OUT
YOKE
RH
PROCESSOR 4
RH-RET
1006
1
GV-OUT
GV
2
GV-RET
TO GRN
GH-OUT 3
YOKE
GH
GH-RET 4
1007
1
BV-OUT
BV
2
BV-RET
TO BLUE
3
BH-OUT
YOKE
BH
BH-RET 4
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