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EN 140
9.
9.3.12 Diagram B7B, TDA9975H (IC 7B50)
Block Diagram
REF
G/Pb
B/Pb1
B/Pb2
B/Pb3
I²C
BIAS
BIAS
CONTROL
REF
G/Y
G/Y1
G/Y2
G/Y3
I²C
REF
R/Pr
R/Pr1
R/Pr2
R/Pr3
I²C
CLAMP
GAIN
LINE TIME
MCLK
MEASUREMENT
COAST
SOG/Y1
SYNC
SOG/Y2
SLICERS
SOG/Y3
H(C)SYNC1
H(C)SYNC2
H(C)SYNC3
VSYNC1
VSYNC2
VSYNC3
VAI
RXA0+
RXA0-
2
RXB0+
RXB0-
2
RXA1+
RXA1-
2
RXB1+
RXB1-
2
RXA2+
RXA2-
2
RXB2+
RXB2-
2
RXAC+
RXAC-
2
RXBC+
RXBC-
2
TERMINATION
RESISTANCE
CONTROL
Pin Configuration
EL1.1U
Circuit Descriptions, Abbreviation List, and IC Data Sheets
I²C
AGC
ADC
10
I²C
CLAMP
B/Pb CHANNEL
G/Y CHANNEL
10
R/Pr CHANNEL
10
I²C
I²C
(CLKPIX)
(CLKFOR)
(CLKOUT)
I²C
AVI CLOCKS
GENERATOR
(COAST)
I²C
I²C
I²C
TDA9975
I²C
I²C
I²C
PARALLEL
8
RECOVERY
I²C
PARALLEL
RECOVERY
I²C
PARALLEL
RECOVERY
I²C
HDCP
I²C
CIPHER
I²C
I²C
MEMORY
HDMI RECEIVER
Figure 9-14 Internal block diagram and pin configuration
10/12
I²C
I²C
I²C
I²C
10/12
I²C
I²C
10/12
I²C
I²C
UPSAMPLE
I²C
I²C
DEREPEATER
I²C
I²C
8
8
(HDMI CLOCKx2)
(HDMI CLOCK)
(CTL3)
SERIAL
INTERFACE
FRO
INTERFACE
I²C
I²C
τ
τ
τ
I²C
I²C
I²C
+
-
I²C
VHREF TIMING
+
-
GENERATOR
I²C
+
-
I²C
I²C
τ
+
-
I²C
I²C
I²C
τ
+
-
I²C
I²C
I²C
&
+
-
I²C
I²C
+
-
τ
I²C
I²C
I²C
τ
4
I²C
AUDIO FIFO
I²C
AUDIO PLL
I²C
I²C
I²C
SERIAL
POWER
MANAGEMENT
I²C
F_15400_135.eps
ORR/V
ORB/U
ORG/Y
VPA[11:0]
VPB[11:0]
VPC[11:0]
FREF
VREF
HREF
VCLK
PL
HS
VS
CS
DE
CTL[3:0]
AP[3:0]
WS
ACLK
OE
240505
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