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EN 132
9.
9.3.2
Diagram A4, MC34067P (IC 7U01)
Block Diagram
15
V
CC
9
V
Enable /
CC
UVLO Adjust
1
Osc Charge
2
Frequency
Osc RC
3
Oscillator
Control Current
16
One–Shot
Error Amp
6
Output
8
Noninverting
Input
Inverting Input
7
Error
11
Amp
Soft–Start
9.3.3
Diagram B1A, NCP5422ADR2G (IC 7U00)
EL1.1U
Circuit Descriptions, Abbreviation List, and IC Data Sheets
UVLO /
5.0 V
Enable
Reference
V
UVLO
ref
Variable
Oscillator
Steering
One–Shot
Flip–Flop
2.5 V
Clamp
Soft–Start
Fault Detector
4
Ground
Figure 9-4 Internal block diagram and pin configuration
Block Diagram
V
CC
BIAS
V
CC
8.6 V
−
7.8 V
IS+1
+
IS−1
−
−
70 mV
IS+2
+
IS−2
−
−
FAULT
70 mV
S
Q
Set
Dominant
−
R
+
0.25 V
−
E/A OFF
5.0 A
1.0 V
V
FB1
Pin Configuration
GATE(H)1
GATE(L)1
GND
BST
IS+1
IS−1
V
COMP1
A
WL
Y
WW = Work Week
Figure 9-5 Internal block diagram and pin configuration
Pin Configuration
5
V
ref
14
Output A
12
Output B
13
Pwr Gnd
10
Fault Input
R
OSC
CURRENT
SOURCE
RAMP1
GEN
CLK1
OSC
CLK2
S
Reset
Dominant
FAULT
PWM
Comparator 1
R
FAULT
RAMP1
0.425 V
−
S
+
Reset
FAULT
Dominant
PWM
Comparator 2
R
FAULT
RAMP2
E/A OFF
0.425 V
1.2 mA
−
E/A1
−
+
E/A2
1.0 V
COMP1
V
COMP2
FB2
SO−16
1
16
GATE(H)2
GATE(L)2
V
CC
R
OSC
IS+2
IS−2
V
FB1
FB2
COMP2
= Assembly Location
= Wafer Lot
= Year
MC34067
Osc Charge
1
Osc RC
2
Osc Control Current
3
Gnd
4
V ref
5
Error Amp Out
6
Inverting Input
7
Noninverting Input
8
(Top View)
RAMP2
BST
BST
GATE(H)1
non−overlap
V
CC
GATE(L)1
BST
GATE(H)2
non−overlap
V
CC
GATE(L)2
GND
FAULT
F_15400_129.eps
240505
One–Shot RC
16
V CC
15
Drive Output A
14
13
Power Gnd
Drive Output B
12
C Soft–Start
11
Fault Input
10
Enable/UVLO
9
Adjust
F_15710_163.eps
230905
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