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Electrical Adjustment
Grp / No. Item
16 DLYCNT (SLOT2)
17 DLYCNT (SLOT2)
18 DLYCNT (SLOT2)
19 DLYCNT (SLOT2)
90
SW FPGA -SETTING
0 LVDS_AJY_TIM
1 LVDS_SJY_PHASE
2 RSTOFF
3 LVDS_AJY_TIM
4 LVDS_AJY_PHASE
5 RSTOFF
100
CXA7010
0 G SIG Center
1 B SIG Center
2 R SIG Center
3 G Bright Control
4 B Bright Control
5 R Bright Control
6 G Gain Control
7 B Gain Control
8 R Gain Control
9 G VCOM Control
10 B VCOM Control
11 R VCOM Control
12 G SID Control A
13 B SID Control A
14 R SID Control A
15 G SID Control B
16 B SID Control B
17 R SID Control B
18 G SID Control C
19 B SID Control C
20 R SID Control C
21 G SID Control D
22 B SID Control D
23 R SID Control D
24 G SID Control E
25 B SID Control E
26 R SID Control E
27 G SID Control F
28 B SID Control F
29 R SID Control F
30 G SIGFRINV
31 B SIGFRINV
32 R SIGFRINV
33 G SID1FRINV
34 B SID1FRINV
35 R SID1FRINV
36 G SID2FRINV
37 B SID2FRINV
38 R SID2FRINV
101
CXD3550_TG
0 SHP_R
1 SHP_G
2 SHP_B
3 SCANM
4 FRPM
5 HST_R_PC
6 HST_G_PC
7 HST_B_PC
8 HST_R_PF
9 HST_G_PF
10 HST_B_PF
11 DCK1_R_W
12 DCK1_R_F
13 DCK2_R_W
14 DCK2_R_F
Function
SLOT2 Clock Phase [Reserved]
SLOT2 Clock Phase [Reserved]
SLOT2 Clock Phase [Reserved]
SLOT2 Clock Phase [Reserved]
AV
AV
AV
Slot
Slot
Slot
Range
0 - 255
0 - 255
0 - 255
0 - 255
0 - 7
0 - 255
0 - 1
0 - 7
0 - 255
0 - 1
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 1
0 - 1
0 - 1
0 - 1
0 - 1
0 - 1
0 - 1
0 - 1
0 - 1
0 - 127
0 - 127
0 - 127
0 - 3
0 - 3
0 - 127
0 - 127
0 - 127
0 - 127
0 - 127
0 - 127
0 - 255
0 - 127
0 - 255
0 - 127
-76-
Initial
Note
1
1
1
1
0
135
0
135
0
112
112
112
0
0
0
208
208
208
150
150
150
50
50
50
50
50
50
176
176
176
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
1
1
25
25
25
2
2
7
7
7
12
12
12
10
24
10
24
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