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Electrical Adjustment
Grp / No. Item
66 YE_GAIN_C0
67 YE_GAIN_C1
68 YE_GAIN_C2
69 YE_GAIN_C3
70 YE_GAIN_C4
71 YEOFF_YE_SW
72 YEOFF_YE_LVL
73 COLOR_AJY
83
FINE FPGA Sharpnes
0 Sharpness MIN [PC-SD]
1 Sharpness MIN [PC-HD]
2 Sharpness MIN [AV-SD]
3 Sharpness MIN [AV-HD]
4 Sharpness CENTER [PC-SD]
5 Sharpness CENTER [PC-HD]
6 Sharpness CENTER [AV-SD]
7 Sharpness CENTER [AV-HD]
8 Sharpness MAX [PC-SD]
9 Sharpness MAX [PC-HD]
10 Sharpness MAX [AV-SD]
11 Sharpness MAX [AV-HD]
84
FINE FPGA - Blending
0 BKMOD
1 BLD_I_SIZE_H
2 BLD_I_SIZE_V
3 BLD_CURVE
4 RGB_GAIN
5 RGB_GAIN
6 RGB_GAIN
7 RGB_GAIN
8 RGB_GAIN
9 RGB_GAIN
10 Bld_Exp_Int
11 Bld_Exp_Int
12 Bld_Exp_Int
13 Bld_Exp_Int
14 Bld_Exp_Int
15 Bld_Exp_Int
16 Bld_off_mult
17 Bld_off_mult
18 Bld_off_mult
19 Bld_off_mult
20 Bld_off_mult
21 Bld_off_mult
85
AV FPGA Dot Clock Rate
1 PC-Dot Clock Rate
2 AV-Dot Clock Rate
86
MOTHER FPGA DLYCNT
0 DLYCNT (SLOT1)
1 DLYCNT (SLOT1)
2 DLYCNT (SLOT1)
3 DLYCNT (SLOT1)
4 DLYCNT (SLOT1)
5 DLYCNT (SLOT1)
6 DLYCNT (SLOT1)
7 DLYCNT (SLOT1)
8 DLYCNT (SLOT1)
9 DLYCNT (SLOT1)
10 DLYCNT (SLOT2)
11 DLYCNT (SLOT2)
12 DLYCNT (SLOT2)
13 DLYCNT (SLOT2)
14 DLYCNT (SLOT2)
15 DLYCNT (SLOT2)
Function
0: Blending Mode (NORMAL) Layered Disable
1: Blending Mode (BLANKINK)Layered Disable
2: Blending Mode (NORMAL)Layered Enable
3: Blending Mode (BLANKING)Layered Enable
Inner Frame Width H
Inner Frame Width V
Curve
PC-Standard
PC-Real
PC-Dynamic
AV-Standard
AV-Cinema
AV-Dynamic
PC-Standard
PC-Real
PC-Dynamic
AV-Standard
AV-Cinema
AV-Dynamic
PC-Standard
PC-Real
PC-Dynamic
AV-Standard
AV-Cinema
AV-Dynamic
Slot-DIgtal
Slot-DIgital
SLOT1 Clock Phase [DVI-Dsub]
SLOT1 Clock Phase [HDCP-DVI]
SLOT1 Clock Phase [Dual Fanc-SDI]
SLOT1 Clock Phase [Dual Link-SDI]
SLOT1 Clock Phase [AMIMON]
SLOT1 Clock Phase [Reserved]
SLOT1 Clock Phase [Reserved]
SLOT1 Clock Phase [Reserved]
SLOT1 Clock Phase [Reserved]
SLOT1 Clock Phase [Reserved]
SLOT2 Clock Phase [DVI-Dsub]
SLOT2 Clock Phase [HDCP-DVI]
SLOT2 Clock Phase [Dual Fanc-SDI]
SLOT2 Clock Phase [Dual Link-SDI]
SLOT2 Clock Phase [AMIMON]
SLOT2 Clock Phase [Reserved]
Range
0 - 511
0 - 511
0 - 511
0 - 511
0 - 511
0 - 1
0 - 255
0 - 16383
0 - 127
0 - 127
0 - 127
0 - 127
0 - 127
0 - 127
0 - 127
0 - 127
0 - 127
0 - 127
0 - 127
0 - 127
0 - 3
0 - 255
0 - 255
0 - 255
0 - 511
0 - 511
0 - 511
0 - 511
0 - 511
0 - 511
0 -255
0 -255
0 -255
0 -255
0 -255
0 -255
0 -255
0 -255
0 -255
0 -255
0 -255
0 -255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
0 - 255
-75-
Initial
Note
300
278
207
120
100
1
255
128
0
0
0
0
35
30
46
35
100
100
77
70
3
0
0
0
256
256
256
256
256
256
125
125
125
125
125
125
64
64
64
64
64
64
1002
1002
7
7
3
3
3
1
1
1
1
1
7
7
3
3
3
1
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