Transmitter System Dr-135; Pll Synthesizer Circuit Dr-135 - Alinco DR-135 Service Manual

2) Transmitter System DR-135

1. Modulator Circuit
2. Power Amplifier Circuit
3. APC Circuit

3) PLL Synthesizer Circuit DR-135

1. PLL
2. Reference Frequency Circuit
The audio signal is converted to an electrical signal by the microphone, and
input it to the microphone amplifier (Q6). Amplified signal which passes through
mic-mute control IC109 is adjusted to an appropriate mic-volume by means of
mic-gain adjust VR106.
IC114:A and B consists of two operational amplifiers; one amplifier (pin 1, 2
and 3) is composed of pre-emphasis and IDC circuit and the other (pin 5, 6
and 7) is composed of a splatter filter. The maximum frequency deviation is
obtained by VR107. And input to the signal switch (IC113) (9600 bps packet
signal input switch) and input to the cathode of the variable capacitor of the
VCO, to change the electric capacity in the oscillation circuit. This produces
the frequency modulation.
The transmitted signal is oscillated by the VCO, amplified by the drive amplifier
(Q145) and younger amplifier (Q115, Q144), and input to the final power module
(IC110). The signal is then amplified by the final power module (IC110) and
led to the antenna switch (D110) and low-pass filter (L113, L114, L115, L116,
C215, C216, C202, C203 and C204), where unwanted high harmonic waves
are reduced as needed, and the resulting signal is supplied to the antenna.
Part of the transmission power from the low-pass filter is detected by D111
and D112, converted to DC. The detection voltage is passed through the APC
circuit (Q118, Q117, Q116), then it controls the APC voltage supplied to the
younger amplifier Q115 and the final power module IC110 to fix the transmission
power.
The dividing ratio is obtained by sending data from CPU (IC1) to pin 2 and
sending clock pulses to pin 3 of the PLL IC (IC116). The oscillated signal from
the VCO is amplified by the buffer (Q134 and Q135) and input to pin 15 of
IC116. Each programmable divider in IC116 divides the frequency of the input
signal by N according to the frequency data, to generate a comparison
frequency of 5 or 6.25 kHz.
The reference frequency appropriate for the channel steps is obtained by dividing
the 21.25 MHz reference oscillation (X102) by 4250 or 3400, according to the data
from the CPU (IC1). When the resulting frequency is 5 kHz, channel step of 5, 10,
15, 20, 25, 30 and 50 kHz are used. When it is 6.25 kHz, the 12.5 kHz channel step
is used.
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