Circuit Description; Receiver System Dr-135 - Alinco DR-135 Service Manual

CIRCUIT DESCRIPTION

1) Receiver System DR-135

The receiver system is a double super-heterodyne system with a 21.7MHz first IF and a 450kHz second IF.
1. Front End
2. IF Circuit
3. Demodulator Circuit
The received signal at any frequency in the 136.000MHz to 173.995MHz range
is passed through the low-pass filter (L116, L115, L114, L113, C204, C203,
C202, C216 and C215) and tuning circuit (L105, L104 and D105, D104), and
amplified by the RF amplifier (Q107). The signal from Q107 is then passed
through the tuning circuit (L103, L102, and variable capacitor D103, D102)
and converted into 21.7MHz by the mixer (Q106). The tuning circuit, which
consists of L105, L104, variable capacitor D105 and D104, L103, L102, variable
capacitor D103 and D102, is controlled by the tracking voltage from the VCO.
The local signal from the VCO is passed through the buffer (Q145), and supplied
to the source of the mixer (Q106). The radio uses the lower side of the super-
heterodyne system.
The mixer mixes the received signal with the local signal to obtain the sum of
and difference between them. The crystal filter (XF102, XF101) selects 21.7
MHz frequency from the results and eliminates the signal of the unwanted
frequencies. The first IF amplifier (Q105) then amplifies the signal of the selected
frequency.
After the signal is amplified by the first IF amplifier (Q105), it is input to pin24
of the demodulator IC (IC108). The second local signal of 21.25MHz (shared
with PLL IC reference oscillation), which is oscillated the external oscillator
X102 (VCTCXO), is input through pin 1 of IC108. Then, these two signals are
mixed by the internal mixer in IC108 and the result is converted into the second
IF signal with a frequency of 450kHz. The second IF signal is output from pin
3 of IC108 to the ceramic filter (FL102 or FL101), where the unwanted frequency
band of that signal is eliminated, and the resulting signal is sent back to the
IC108 through pin 5.
The second IF signal input via pin 5 is demodulated by the internal limiter
amplifier and quadrature detection circuit in IC 108, and output as an audio
signal through pin 12.
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