Yamaha CS1D Service Manual page 41

CS1D
AK5392-VS-E2 (XV065A00) ADC (Analog to Digital Converter)
PIN
NAME I/O
NO.
1 VREFL O L ch standard voltage output (+3.75 V)
2 GNDL - L ch Ground
3 VCOML O L ch common voltage (+2.5 V)
4 AINL+ I L ch analog (+) input
5 AINL- - L ch analog (-) input
6 ZCAL I Zero calibration
"L": VCOML,VCOMR
"H": Analog input (AINL+/-,AINRR+/-)
7 VD - Power supply for digital
8 DGND - Ground for digital
9 CAL O Calibration status
10 /RST I Reset
11 SMODE2 I Serial interface mode select
12 SMODE1 I MSB first, 2's compliment
SMODE2
13 LRCK I/O L/R ch select clock
14 SCLK I/O Serial data clock
ICS2008A (XV619A00) T.C. Reader/Generator
PIN
NAME I/O
NO.
1 INTR O Interrupt request
2 RESET I Master reset
3 FRAME I Color frame A / B input
4 CLICK I LTC SYNC input
5 LTCIN- I SMPTE LTC input -
6 LTCIN+ I SMPTE LTC input +
7 LTCOUT O SMPTE LTC output
8 LFC I External RC circuit
9 XTAL2 O 14.318 MHz crystal oscillator
10 XTAL1 I 14.318 MHz crystal oscillator
11 AVDD - Analog power supply
12 AVSS - Analog ground
13 COUT O C(Chroma) output
14 YOUT O Y(Luma) output
15 C2 I C(Chroma) input
16 Y2 I Y(Luma) input
17 C1 I C(Chroma) input
18 Y1 I Y(Luma) input
19 STHRESH I SYNC threshold bypass input
20 CTHRESH I Clamp threshold bypass input
21 DTHRESH I Data threshold bypass input
22 RXD I UART receive data
PDIUSBD12PW (XW583A00) USB Interface
PIN
NAME I/O
NO.
1 DATA0 I/O Bit 0 of bi-directional data.
2 DATA1 I/O Bit 1 of bi-directional data.
3 DATA2 I/O Bit 2 of bi-directional data.
4 DATA3 I/O Bit 3 of bi-directional data.
5 GND - Ground
6 DATA4 I/O Bit 4 of bi-directional data.
7 DATA5 I/O Bit 5 of bi-directional data.
8 DATA6 I/O Bit 6 of bi-directional data.
9 DATA7 I/O Bit 7 of bi-directional data.
10 ALE I Address Latch Enable.
11 CS_N I Chip Select (Active Low).
12 SUSPEND I/O Device is in Suspend state.
13 CLKOUT O Programmable Output Clock (slew-rate controlled)
14 INT_N O interrupt (Active Low)
36
FUNCTION
SMODE1 MODE LRCK
L L Slave mode H/L
L H Master mode H/L
H L Slave mode
L/H
H H Master mode L/H
FUNCTION
FUNCTION
PIN
NAME I/O
NO.
15 SDATA O Serial data output
16 FSYNC I/O Frame synchronization clock
17 MCLK I Master clock input
CMODE="H":384 fs
CMODE="L":256 fs
18 CMODE I Master clock select
"L": MCLK=256 fs (12.288 MHz @fs=48 kHz)
"H": MCLK=384 fs (18.432 MHz @fs=48 kHz)
19 HPFE I HPF enable "L": OFF "H": ON
20 TEST I TEST pin
Connect it with DGND.
21 BGND - Ground
22 AGND - Ground for analog
23 VA - Power supply for analog (+5 V)
24 AINR- I R ch analog (+) input
25 AINR+ I R ch analog (-) input
26 VCOMR O R ch common voltage (-2.5 V)
27 GNDR - R ch ground
28 VREFR O R ch standard voltage output (+3.75 V)
PIN
NAME I/O
NO.
23 CTS I Clear to send
24 TXD O UART transmit data
25 RTS O Ready to send
26 LRCLK O SMPTE LTC receive clock
27 VITCGATE O VITE cord is for video overlay
28 VITCOUT O SMPTE VITE output
29 A0 I Address bus
30 A1 I Address bus
31 /SMPTECS I SMPTE port chip select
32 /UARTSC I UART chip select
33 /IOR I Read enable
34 VSS - Digital ground
35 VDD - Digital power supply
36 /IOW I Write enable
37 D0 I/O
38 D1 I/O
39 D2 I/O
40 D3 I/O
Data bus
41 D4 I/O
42 D5 I/O
43 D6 I/O
44 D7 I/O
PIN
NAME I/O
NO.
15 RD_N I Read Strobe (Active Low)
16 WR_N I Write Strobe (Active Low)
17 DMREQ O DMA Request.
18 DMACK_N I DMA Acknowledge (Active Low).
19 EOT_N I End of DMA Transfer (Active Low).
20 RESET_N I Reset (Active Low and asynchronous).
Built-in Power-On-Reset circuit
21 GL_N O GoodLink LED indicator (Active Low)
22 XTAL1 I Crystal Connection 1 (6 MHz)
23 XTAL2 O Crystal Connection 2 (6 MHz)
24 Vcc - Voltage supply (4.0-5.5 V)
25 D- - USB D-data line
26 D+ - USB D+data line
27 Vout3.3 - 3.3 V regulated output.
28 A0 I Address bit. A0=1 selects command
instruction; A0=0 selects the data phase.
FUNCTION
FUNCTION
FUNCTION