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Lattice Semiconductor ECP5 Technical Note

High-speed i/o interface
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ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
FPGA-TN-02035-1.3
October 2020

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Summary of Contents for Lattice Semiconductor ECP5

  • Page 1 ECP5 and ECP5-5G High-Speed I/O Interface Technical Note FPGA-TN-02035-1.3 October 2020...
  • Page 2 The information provided in this document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at any time without notice.

  • Page 3: Table Of Contents

    Write Implementation (DDR2, DDR3/DDR3L Address, Command, and Clock) ..........41 © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
  • Page 4 MEM_SYNC ..............................80 © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
  • Page 5 Revision History .................................. 84 © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
  • Page 6 Figure 8.2. DELAYG Primitive .............................. 65 © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
  • Page 7 Figure 9.5. MIPI_FILTER Ports ............................. 81 © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
  • Page 8 Table 9.7. MIPI_FILTER Port Description ..........................82 © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 9: Acronyms In This Document

    Simultaneous Switching Noise © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 10: Introduction

    DDR interfaces capture data on both the rising and falling edges of the clock, thus doubling the performance. ECP5 and ECP5-5G device I/O also have dedicated circuitry that is used along with the DDR I/O to support DDR2, DDR3, DDR3L, LPDDR2, and LPDDR3 SDRAM memory interfaces.

  • Page 11: High-Speed I/O Interface Building Blocks

    DQS strobe and up to 12 to 16 ports for DQ data and DM data mask signals. The number of DQS Lanes on the device is different for each device size. ECP5 and ECP5-5G devices support DQS lanes on the left and right sides of the device.

  • Page 12: Pll

    DDRDLL code. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 13: Dlldel

    MOVE and DIRECTION control inputs. The LOADN resets the delay back to the default value. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 14: Building Generic High Speed Interfaces

    .Centered – Clock is centered to the data when coming into the device © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 15: High-Speed Ddr Interface Details

    © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 16: Gddrx1_Rx.sclk.aligned

    Figure 5.3. GDDRX1_RX.SCLK.Aligned Interface (Static Delay) © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 17: Gddrx2_Rx.eclk.centered

    The following figures show the static delay and dynamic delay options for this interface. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 18: Gddrx2_Rx.eclk.aligned

    ECLKSYNCB element. This element can be enabled through Clarity Designer. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 19: Figure 5.7. Gddrx2_Rx.eclk.aligned Interface (Static Delay)

    Figure 5.8. GDDRX2_RX.ECLK.Aligned Interface (Dynamic Data/Clock Delay) © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 20: Gddrx2_Rx.mipi

    © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 21: Gddrx71_Rx.eclk

    USE PRIMARY preference may be assigned to the SCLK out of the CLKDIVF module. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 22: Gddrx1_Tx.sclk.aligned

    The output data can be optionally tristated using either a Tristate input going through an I/O register. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 23: Gddrx2_Tx.eclk.aligned

    Figure 5.13. GDDRX2_TX.ECLK.Aligned Interface © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 24: Gddrx2_Tx.eclk.centered

    © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 25: Gddrx71_Tx.eclk

    This section describes the various design guidelines used for building generic high-speed DDR interfaces in ECP5 and ECP5-5G devices. In additional to these guidelines, it is also required to follow the Interface Rules described for each type of interface, you need to find the interface you are building in the High-Speed DDR Interface Details section.

  • Page 26: Receive Interface Guidelines

    None of the clocks going to the DDR registers can come from internal general routing. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 27: Timing Analysis For High Speed Ddr Interfaces

    © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 28: Ddr Clock To Out Constraints For Transmit Interfaces

    Therefore, any data transition must occur between the tCO Min and tCO Max values. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 29: Figure 5.18. Tco Min And Max Timing Analysis

    = Input Clock Port © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 30: Figure 5.20. Transmit Aligned Interface Timing

    © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 31: Ecp5 And Ecp5-5G Memory Interfaces

    All of the DDR SDRAM interface transfers data at both the rising and falling edges of the clock. The I/O DDR registers in the ECP5 and ECP5-5G device can be used to support DDR2, DDR3, DDR3L, LPDDR2, and LPDDR3 memory interfaces.

  • Page 32: Figure 6.2. Typical Lpddr2/Lpddr3 Memory Interface

    DDR memory configurations and features supported by ECP5 and ECP5-5G device. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 33: Ddr Memory Interface Requirements

    ECP5 and ECP5-5G devices generate a DQS signal that is center aligned with the DQ, the data signal. This is accomplished by ensuring a DQS strobe is 90° shifted relative to the DQ data. The ECP5 and...

  • Page 34: Features For Memory Interface Implementation

    LPDDR2) outputs. In ECP5 and ECP5-5G devices, a DQS group consists of 12 to 16 I/O depending on the device and package selected to accommodate these DDR interface needs. ECP5 and ECP5-5G devices support DQS signals on the left and right sides of the device.

  • Page 35: Dll-Compensated Dqs Delay Elements

    6.2.2. DLL-Compensated DQS Delay Elements The DQS to and from the memory is connected to the DQS delay element inside the ECP5 and ECP5-5G device. The DQS delay block receives the delay control code, DDRDEL, from the on-chip DDRDLL. The code generated by DDRDLL is connected to the DQSBUF circuit to perform 90°...

  • Page 36: Read Pulse Positioning Optimization

    Due to the DQS round trip delay that includes PCB routing and I/O pad delays, proper positioning of the READ pulse is crucial for successful read operations. The ECP5 and ECP5-5G device DQSBUF block provides the dynamic READ pulse positioning function which allows the memory controller to locate the READ pulse to an appropriate timing window for the read operations by monitoring the positioning result.

  • Page 37: Figure 6.7. Read Signal Training Process

    (UDDCNTLN) also have the same PAUSE requirement. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 38: Dynamic Margin Control On Dqsbuf

    6.2.6. Read Data Clock Domain Transfer Using Input FIFO Each IDDR module in the ECP5 and ECP5-5G device has a dedicated input FIFO to provide a safe clock domain transfer from the DQS domain to the ECLK or SCLK domain. The input FIFO is 8-level deep with 3-bit write and read pointers. It transfers the read data from the non-continuous DQS domain to the continuous ECLK.

  • Page 39: Figure 6.8. Ddr2, Ddr3/Ddr3L, Lpddr2, And Lpddr3 Read Side Implementation

    Clarity Designer, the MEM_SYNC soft IP block is also generated and included. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 40: Write Implementation (Dq, Dqs, And Dm)

    Figure 6.9. DDR2, DDR3/DDR3L, LPDDR2, and LPDDR3 Write Side (DQ, DQS, and DM) © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 41: Write Implementation (Ddr2, Ddr3/Ddr3L Address, Command, And Clock)

    Figure 6.10. DDR2, DDR3/DDR3L Address, Command, and Clock Generation © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 42: Write Implementation (Lpddr2 And Lpddr3 Address, Command, And Clock)

    Figure 6.11. LPDDR2 Output for CA Generation © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 43: Figure 6.12. Lpddr2 Output For Csn, Cke, And Clock Generation

    Figure 6.13. LPDDR3 Output Side for CA Generation © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 44: Ddr Memory Interface Design Rules And Guidelines

    ECP5-5G devices. ECP5 and ECP5-5G devices have dedicated DQS banks with the associated DQ pads.  The left and right sides of an ECP5 and ECP5-5G device share an identical I/O structure. All of the memory interfaces can be implemented on these sides.

  • Page 45: Ddr2/Ddr3 Memory Interface Termination Guidelines

    DDR3 SDRAM's ODT function.  Do not locate any termination on the FPGA side. The ECP5 and ECP5-5G device has internal termination on DQ and DQS, which is dynamically controlled. Use the TERMINATION preference for DQ and DQS pads to enable the internal parallel termination to VCCIO/2.

  • Page 46: Termination For Address, Commands, And Controls

    DQS interface such as DDR2 with single ended strobe. However, a DQS signal must use the DQS/DQS# pads only.  Data group signals (DQ, DQS, DM) can use any of the left and right sides of the ECP5 and ECP5-5G device as long as they keep the DQS-DQ association rule. ...

  • Page 47: Pin Placement Considerations For Improved Noise Immunity

     Place the DQS groups for data implementation starting from the middle of the (right or left) edge of the ECP5 and ECP5-5G device. Allow a corner DQS group to be used as a data group only when necessary to implement the required width.
  • Page 48 VREF1 pad is not located. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 49: Using Clarity Designer To Build And Plan High Speed Ddr Interfaces

    © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 50: Configuring Ddr Modules In Clarity Designer

    Technical Note 7.1. Configuring DDR Modules in Clarity Designer The catalog section of Clarity Design lists all the DDR architecture modules available on ECP5 and ECP5-5G. All the DDR modules are located under Architecture Modules – I/O. This includes: ...

  • Page 51: Figure 7.3. Sdr Configuration Tab

    Figure 7.3. SDR Configuration Tab © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 52: Table 7.1. Sdr Configuration Parameters

    Dynamic User-Defined: Dynamic delay element DELAYF is used with attribute DEL_MODE = USER_DEFINED. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 53: Configuring Ddr Generic Modules

    Figure 7.5. DDR_Generic Pre-Configuration Tab © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 54: Figure 7.6. Ddr_Generic Configuration Tab

    Configuration tab. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 55: Table 7.3. Ddr_Generic Configuration Tab Parameters

    Frequency © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 56: Table 7.4. Clarity Designer Ddr_Generic Interface Selection

    © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 57: Configuring 7:1 Lvds Interface Modules

    Figure 7.8. GDDR_7:1 LVDS Configuration Tab © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 58: Configuring Ddr Memory Interfaces

    Figure 7.9. DDR_MEM Option Selected in the Catalog Tab of Clarity Designer © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 59: Figure 7.10. Ddr_Mem Configuration Tab

    Figure 7.10. DDR_MEM Configuration Tab © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 60: Table 7.6. Ddr_Mem Configuration Tab Parameters

    © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 61: Figure 7.11. Ddr_Mem Clock/Address/Command Tab

    LPDDR3 = Number of chip Selects © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 62: Building Ddr Interfaces In Clarity Designer

    ECP5 and ECP5-5G High-Speed I/O Interface Technical Note There is an additional tab called Advanced Settings for the ECP5 and ECP5-5G device that can be used to adjust the default DQS Read and Write Delay settings. Figure 7.12. DDR_MEM Advanced Settings Tab Figure 7.8...

  • Page 63: Planning Ddr Interfaces In Clarity Designer

    Figure 7.13. DDR Modules Paced Using Clarity Design Planner © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 64: Ddr Software Primitives And Attributes

    DELAY block completely as well. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 65: Delayf

    Delayed data to input register block or to pin © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 66: Delay Attribute Description

    Figure 8.3. DDRDLLA Primitive © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 67: Dll Delay (Dlldel)

    Delayed clock output © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 68: Generic Ddr Input And Output Primitives

    8.7. Generic DDR Input and Output Primitives The ECP5 and ECP5-5G device IDDR/ODDR modules support 2:1, 4:1 and 7:1 gearing modes on the left and right sides only. IDDR/ODDR modules on the top (and bottom for non-SERDES parts) only supports 2:1 due to lack of Edge Clocks.

  • Page 69: Iddrx2F

    7 bits of output data. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 70: Output Ddr Primitives

    DDR data output on both edges of ECLK © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 71: Oddr71B

    Generates a BURSTDET output that can be used to validate the READ pulse positioning. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 72: Dqsbufm

    DQS. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 73: Input And Output Memory Ddr Primitives

    Note: Default value is set based on device characterization to achieve the 90° phase shift. 8.11. Input and Output Memory DDR Primitives The ECP5 and ECP5-5G device IDDR/ODDR modules support 4:1 (2x) gearing mode that are used to implement the memory functions.

  • Page 74: Memory Input Ddr Primitives

    SET so that all output buffers are tristated by default © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 75: Memory Output Ddr Primitives For Dq Output

    Figure 8.14. ODDRX2DQSB Primitive © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 76: Memory Output Ddr Primitives For Tristate Output Control

    Figure 8.16. TSHX2DQSA Primitive © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 77: Memory Output Ddr Primitives For Address And Command

    Address and command output © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 78: Soft Ip Modules

    Figure 9.1. GDDR_SYNC Ports © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 79: Rx_Sync

    Indicate that startup is finished and RX circuit is ready to operate. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 80: Mem_Sync

    Figure 9.4. BW_ALIGN Ports © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 81: Mipi_Filter

    Figure 9.5. MIPI_FILTER Ports © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 82: Table 9.7. Mipi_Filter Port Description

    Filter_clk=200 MHz. cutoff=8. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 83: Technical Support Assistance

    Submit a technical support case through www.latticesemi.com/techsupport. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 84: Revision History

    Updated Technical Support information. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
  • Page 85 Initial release. © 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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