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Lattice Semiconductor ECP5 Technical Notes

High-speed i/o interface
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November 2015
Introduction
TM
TM
ECP5
and ECP5-5G
Data Rate (SDR) interfaces, using the logic built into the Programmable I/O (PIO). SDR applications capture data
on one edge of a clock while DDR interfaces capture data on both the rising and falling edges of the clock, thus
doubling the performance. ECP5 and ECP5-5G device I/Os also have dedicated circuitry that is used along with
the DDR I/O to support DDR2, DDR3, DDR3L, LPDDR2 and LPDDR3 SDRAM memory interfaces.
This document discusses how to utilize the capabilities of the ECP5 and ECP5-5G devices to implement high-
speed generic DDR interface and the DDR memory interfaces. Refer to the Implementing DDR Memory Interfaces
section of this document for more information.
External Interface Description
This technical note uses two types of external interface definitions, centered and aligned. A centered external inter-
face means that, at the device pins, the clock is centered in the data opening. An aligned external interface means
that, at the device pins, the clock and data transition are aligned. This is also sometimes called edge-on-edge.
Figure 1 shows the external interface waveform for SDR and DDR.
Figure 1. External Interface Definitions
The interfaces described are referenced as centered or aligned interfaces. An aligned interface will need to adjust
the clock location to satisfy the capture flip-flop setup and hold times. A centered interface will need to balance the
clock and data delay to the first flip-flop to maintain the setup and hold already provided.
© 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
devices support high-speed I/O interfaces, including Double Data Rate (DDR) and Single
SDR Aligned
DDR Aligned
ECP5 and ECP5-5G
High-Speed I/O Interface
SDR Centered
DDR Centered
1
Technical Note TN1265
TN1265_1.1

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Summary of Contents for Lattice Semiconductor ECP5

  • Page 1 © 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
  • Page 2 DQSN) for the DQS strobe and up to 12 to 16 ports for DQ data and DM data mask signals. The number of DQS Lanes on the device is different for each device size. ECP5 and ECP5-5G devices support DQS lanes on the left...
  • Page 3 ECP5 and ECP5-5G High-Speed I/O Interface The PLL provides frequency synthesis, with additional static and dynamic phase adjustment, as well. Four output ports are provided, CLKOP, CLKOS, CLKOS2 and CLKOS3. All four outputs have the same set of dividers. There is one PLL per corner on the biggest device, totaling to four PLLs on each device.
  • Page 4 ECP5 and ECP5-5G High-Speed I/O Interface Input DDR (IDDR) The input DDR function can be used in either 1X (2:1), 2X (4:1) or 7:1 gearing modes. In the 1X mode, the IDDR module inputs a single DDR data input and SCLK (primary clock) and provides a 2-bit wide data synchronized to the SCLK (primary clock) to the FPGA fabric.
  • Page 5 Types of High-Speed DDR Interfaces This section describes the different types of high-speed DDR interfaces available in ECP5 and ECP5-5G devices. Table 1 lists these interfaces. Descriptions for each interface in Table 1 are provided below the table.
  • Page 6 This section describes each of the generic high-speed interfaces in detail, including the clocking to be used for each interface. For detailed information about the ECP5 and ECP5-5G device clocking structure, refer to TN1263, ECP5 and ECP5-5G sysClock PLL/DLL Design and Usage Guide.

  • Page 7: Interface Requirements

    ECP5 and ECP5-5G High-Speed I/O Interface Interface Requirements • The clock input must use a PCLK input so that it can be routed directly to the primary clock tree. • The user must set the timing preferences as per section “Timing Analysis Requirement”...
  • Page 8 ECP5 and ECP5-5G High-Speed I/O Interface Figure 7. GDDRX1_RX.SCLK.Aligned Interface (Dynamic Data/Clock Delay) DELAYF Datain DEL_MODE= SCLK_ALIGNED Data_LoadN LOADN IDDRX1F (optional) MOVE Data_Move Q[0] DIRECTION Data_Direction Q[1] Data_CFlag CFLAG DLLDELD Clkin SCLK Clock_CFlag CFLAG LOADN Clock_LoadN DDRDEL Clock_Move MOVE Primary...
  • Page 9 ECP5 and ECP5-5G High-Speed I/O Interface Figure 8. GDDRX2_RX.ECLK.Centered Interface (Static Delay) IDDRX2F DELAYG ECLK DEL_MODE= Datain Q [3 :0 ] SCLK Q [3 :0 ] ECLK_CENTERED AlignWD ALIGNWD ECLKSYNCB Sclk Primary Clkin ECLKI CLKDIVF ECLKO GDDR _SYNC STOP Edge...
  • Page 10 ECP5 and ECP5-5G High-Speed I/O Interface • DEL_MODE attribute is used with DELAYG and DELAYF element to indicate the interface type so that the cor- rect delay value can be set in the delay element • The ECLKBRIDGE can be optionally enabled if the data bus will be crossing over between the left and right sides of the device.
  • Page 11 ECP5 and ECP5-5G High-Speed I/O Interface Figure 11. GDDRX2_RX.ECLK.Aligned Interface (Dynamic Data/Clock Delay) DELAYF Datain DEL_MODE= ECLK_CENTERED IDDRX2F Data_LoadN LOADN (optional) Data_Move MOVE Data_Direction DIRECTION ECLK Q[3:0] Q[3:0] Data_CFlag SCLK CFLAG DDR_reset AlignWD ALIGNWD ECLKSYNCB DLLDELD Sclk ECLKI Primary Clkin...
  • Page 12 ECP5 and ECP5-5G High-Speed I/O Interface • The ECLKBRIDGE can be optionally enabled if the data bus will be crossing over between the left and right sides of the device. If ECLKBRIDGE is enabled then the ECLKBRIDGECS element should be used in the interface before the ECLKSYNCB element.
  • Page 13 ECP5 and ECP5-5G High-Speed I/O Interface The following figures show the interface with the soft IP modules. Figure 13. GDDRX71_RX.ECLK Interface IDDR 71 B Datain Q[0] Q[1] ECLK ECLKSYNCB Q[2] Edge SCLK Q[3] ECLKO ECLKI Q[4] “ 0” STOP Q[5]...
  • Page 14 ECP5 and ECP5-5G High-Speed I/O Interface Figure 14. GDDRX1_TX.SCLK.Aligned Interface ODDRX1F Data[1:0] Dout Refclk SCLK Reset Primary ODDRX1F 1 ' b 1 Clkout 1 ' b 0 SCLK Interface Requirements • The clock to the output DDR modules must be routed on the primary clock tree GDDRX1_TX.SCLK.Centered...
  • Page 15 ECP5 and ECP5-5G High-Speed I/O Interface GDDRX2_TX.ECLK.Aligned The interface is used to generate Generic Transmit DDR with 2X gearing using high speed edge clock (ECLK). The Clock output is edge aligned to the Data output. This DDR interface uses the following modules: •...
  • Page 16 ECP5 and ECP5-5G High-Speed I/O Interface • The same ECLK and SCLK are used for both Data and Clock generation. • The EHXPLLL element is used to generate the clocks for the data and clock ODDR modules. The clock used to generate the clock output is delayed 90 to center to data at the output.
  • Page 17 This section describes the various design guidelines used for building generic high speed DDR interfaces in ECP5 and ECP5-5G devices. In additional to these guidelines, it is also required to follow the Interface Rules described for each type of interface, you will need to find the interface you are building in the section above “High Speed Inter- face Details”.
  • Page 18 • In addition to dedicate PCLK pins, ECP5 and ECP5-5G devices have GR_PCLK pins, these use shortest general route path to get to the primary clock tree. These pins are not recommended for use with DDR interfaces. They can be used for SDR or other generic FPGA designs.
  • Page 19 ECP5 and ECP5-5G High-Speed I/O Interface Timing Analysis for High Speed DDR Interfaces It is recommended that the user run Static Timing Analysis in the software for each of the high speed interfaces. This section describes the timing preferences to used for each type of interface and the expected trace results. The preferences can either be entered directly in the .lpf file or through the Design Planner graphical user interface.
  • Page 20 ECP5 and ECP5-5G High-Speed I/O Interface Example: For GDDRX2_RX.ECLK.Centered Interface running at max speed of 400 MHz, the preference would be - INPUT_SETUP PORT "datain" 0.320000 ns HOLD 0.320000 ns CLKPORT "clk”; Note: Please check DS1044, ECP5 and ECP5-5G Family Data Sheet for the latest tSUDDR and tHOGDDR num- bers.
  • Page 21 ECP5 and ECP5-5G High-Speed I/O Interface DDR Clock to Out Constraints for Transmit Interfaces All of the Transmit (TX) interfaces both x1 and x2 can be constrained with Clock to out constraint to detect the rela- tionship between the Clock and Data when leaving the device.
  • Page 22 ECP5 and ECP5-5G High-Speed I/O Interface The DS1044, ECP5 and ECP5-5G Family Data Sheet specifies the t and t values at DVB_GDDRX1/X2 DVA_GDDRX1/X2 maximum speed. But we do not have the tU value hence min t can be calculated using the following equation.
  • Page 23 All of the DDR SDRAM interface transfers data at both the rising and falling edges of the clock. The I/O DDR regis- ters in the ECP5 and ECP5-5G device can be used to support DDR2, DDR3, DDR3L, LPDDR2 and LPDDR3 memory interfaces.
  • Page 24 ECP5 and ECP5-5G High-Speed I/O Interface DDR memories also require a Data Mask (DM) signal to mask data bits during write cycles. Note that the ratio of DQS to data bits is independent of the overall width of the memory. Figure 24 shows a typical 8-bit interface that has eight associated DQ data bits per DQS strobe signal.
  • Page 25 ECP5 and ECP5-5G High-Speed I/O Interface Figure 25. Typical LPDDR2/LPDDR3 Memory Interface Figure 26. DQ-DQS During Read Preamble Postamble (at PIN) (at PIN) (at IDDR) (at IDDR) 90 degree phase shift between DQS pin to IDDR Figure 27. DQ-DQS During Write...
  • Page 26 IDDR and ODDR register gearing mode together with data transitioning on both edges of the clock. In addition, during a write cycle, the ECP5 and ECP5-5G devices generate a DQS signal that is center aligned with the DQ, the data signal. This is accomplished by ensuring a DQS strobe is 90° shifted relative to the DQ data.
  • Page 27 Figure 28 shows a typical DQ-DQS group for ECP5 and ECP5-5G devices. The 10th I/O Pad of this 16 I/O group is the dedicated DQS pin. All the 9 pads before the DQS and 6 pads after the DQS are covered by this DQS bus span.
  • Page 28 DLL-Compensated DQS Delay Elements The DQS to and from the memory is connected to the DQS delay element inside the ECP5 and ECP5-5G device. The DQS delay block receives the delay control code, DDRDEL, from the on-chip DDRDLL. The code generated by DDRDLL is connected to the DQSBUF circuit to perform 90°...
  • Page 29 Due to the DQS round trip delay that includes PCB routing and I/O pad delays, proper positioning of the READ pulse is crucial for successful read operations. The ECP5 and ECP5-5G device DQSBUF block provides the dynamic READ pulse positioning function which allows the memory controller to locate the READ pulse to an appropriate timing window for the read operations by monitoring the positioning result.
  • Page 30 ECP5 and ECP5-5G High-Speed I/O Interface operations be performed repetitively at a READ pulse position during the initialization for getting jitter immunity. 16 read operations can be performed in a periodic calibration if used during the normal operation. The memory con- troller can determine the proper position alignment when there is no failure on BURSTDET assertions during these multiple trials.
  • Page 31 Read Data Clock Domain Transfer Using Input FIFO Each IDDR module in the ECP5 and ECP5-5G device has a dedicated input FIFO to provide a safe clock domain transfer from the DQS domain to the ECLK or SCLK domain. The input FIFO is 8-level deep with 3-bit write and read pointers.
  • Page 32 The following sections explain the DDR2, DDR3/DDR3L, LPDDR2, LPDDR3 memory interfaces implementation using the X2 gearing mode. ECP5 and ECP5-5G devices support these memory interfaces generation through the Clarity Designer tool. Clarity Designer will generate one module that include the Read and Write side implementa- tion shown below.
  • Page 33 ECP5 and ECP5-5G High-Speed I/O Interface • The DQSBUFM is used to generate the Read and Write pointers that is used to transfer data from the DQS to ECLK inside the IDDRX2DQA module • Read 1, 0 and Readclksel_2, 1, 0 signals of DQSBUFM are used by the user logic to obtain the optimal READ...
  • Page 34 ECP5 and ECP5-5G High-Speed I/O Interface Figure 32. DDR2, DDR3/DDR3L, LPDDR2 and LPDDR3 Write Side (DQ, DQS and DM) Eclk (from ECLKSYNCA as shown in the Input interface) Sclk (from CLKDIVF as shown in the Input interface) DDR_reset TSHX2DQA dqtri_0(0)
  • Page 35 ECP5 and ECP5-5G High-Speed I/O Interface Write Implementation (DDR2, DDR3/DDR3L Address, Command and Clock) DDR2, DDR3, DDR3L write side interface side to generate the Clock, Address and Command uses the following modules: • ODDRX2F with inputs tied to constants to generate the DDRCLK output.
  • Page 36 ECP5 and ECP5-5G High-Speed I/O Interface • Both ECLK and SCLK is used in these elements. This is same ECLK and SLCK generated in the Input Read side module shown above. Figure 34. LPDDR2 Output for CA generation DDR_reset Sclk (from CLKDIVF as shown in the Input interface)
  • Page 37 ECP5 and ECP5-5G High-Speed I/O Interface Figure 36. LPDDR3 Output side for CA Generation DDR_reset Sclk (from CLKDIVF as shown in the Input interface) Eclk (from ECLKSYNCB as shown in the Input interface) CA[9:0] ca <n>_in(0) ODDRX2DQA ca <n>_in(1) DQSBUFM ca <n>_in(2)
  • Page 38 ECP5-5G devices. ECP5 and ECP5-5G devices have dedicated DQS banks with the associated DQ pads. • The left and right sides of an ECP5 and ECP5-5G device share an identical I/O structure. All of the memory inter- faces can be implemented on these sides.
  • Page 39 DDR3 SDRAM's ODT function. • Do not locate any termination on the FPGA side. The ECP5 and ECP5-5G device has internal termination on DQ and DQS, which is dynamically controlled. Use the TERMINATION preference for DQ and DQS pads to enable the internal parallel termination to VCCIO/2.
  • Page 40 DQS interface such as DDR2 with single ended strobe. However, a DQS signal must use the DQS/DQS# pads only. • Data group signals (DQ, DQS, DM) can use any of the left and right sides of the ECP5 and ECP5-5G device as long as they keep the DQS-DQ association rule.
  • Page 41 SSO/SSI immunity. • Place the DQS groups for data implementation starting from the middle of the (right or left) edge of the ECP5 and ECP5-5G device. Allow a corner DQS group to be used as a data group only when necessary to implement the required width.
  • Page 42 Configuring DDR Modules in Clarity Designer The catalog section of Clarity Design lists all the DDR architecture modules available on ECP5 and ECP5-5G. All the DDR modules are located under Architecture Modules – IO. This includes: •...
  • Page 43 ECP5 and ECP5-5G High-Speed I/O Interface Configuring SDR Modules To build and SDR interface, select SDR option under Architecture Modules – IO in the Catalog tab of Clarity Designer. Enter the name of the module. Figure 39 shows the type of interface selected as SDR and module name entered.
  • Page 44 ECP5 and ECP5-5G High-Speed I/O Interface Figure 40. SDR Configuration Tab Table 6 explains the various configurations options available for SDR modules. Table 6. SDR Configuration Parameters GUI Option Description Values Default Interface Type Type of Interface (Transmit or Transmit, Receive...
  • Page 45 ECP5 and ECP5-5G High-Speed I/O Interface GUI Option Description Values Default FDEL for User Defined If Delay type selected above is 0 to 127 “user defined”, delay values can be entered with this parameter 1. When Data Path Delay value is a.
  • Page 46 ECP5 and ECP5-5G High-Speed I/O Interface Figure 42. DDR_Generic Pre-Configuration Tab Figure 42 shows the Pre-Configuration Tab for DDR generic interfaces. The Table 7 explains the various parame- ters in this tab. Table 7. DDR_Generic Pre-Configuration Parameters GUI Option Range...
  • Page 47 ECP5 and ECP5-5G High-Speed I/O Interface Figure 43. DDR_Generic Configuration Tab The check box on the top of this tab indicates that the interface is selected based on entries in the Pre-Configura- tion Tab. The user can choose to change these values by disabling this entry. The best suitable interface is picked based on the selections made in the Pre-Configuration tab.
  • Page 48 ECP5 and ECP5-5G High-Speed I/O Interface GUI Option Description Values Default Value Gearing Ratio DDR register gearing ratio 2:1, 4:1 Alignment Clock to Data alignment Edge-to-Edge or Cen- Centered tered Bus Width Bus width for each interface. 1 – 256...
  • Page 49 ECP5 and ECP5-5G High-Speed I/O Interface GUI Option Description Values Default Value Actual Clock Frequency Displays the achieved PLL output Actual PLL output Fre- clock frequency quency achieved based on interface requirement CLKI Input Buffer Type The I/O Standard for the PLL Ref-...
  • Page 50 ECP5 and ECP5-5G High-Speed I/O Interface Figure 44. GDDR_7:1 Option Selected in the Catalog Tab of Clarity Designer Clicking Customize displays the Configuration Tab where the 7:1 LVDS interface can be configured. Figure 45 shows the “Configuration” tab for 7:1 LVDS interfaces.
  • Page 51 ECP5 and ECP5-5G High-Speed I/O Interface Figure 45. GDDR_7:1 LVDS Configuration Tab Table 10 explains the various parameters in this tab. Table 10. GDDR_7:1 LVDS Configuration Parameters GUI Option Description Values Interface Type Type of interface (Receive or Transmit) Transmit, Receive...
  • Page 52 ECP5 and ECP5-5G High-Speed I/O Interface Figure 46. DDR_MEM Option Selected in the Catalog Tab of Clarity Designer Figure 47 shows the Configuration Tab for the DDR_MEM interface.
  • Page 53 ECP5 and ECP5-5G High-Speed I/O Interface Figure 47. DDR_MEM Configuration Tab Table 11 below describes the various settings shown in the Configuration tab. Table 11. DDR_MEM Configuration Tab Parameters GUI Option Description Range Default Value Interface DDR memory interface type...
  • Page 54 ECP5 and ECP5-5G High-Speed I/O Interface GUI Option Description Range Default Value Data Width DDR memory interface data width DDR2, DDR3, DDR3L: 8, 16, 24, 32, 40, 48, 56, 64, 72 LPDDR2, LPDDR3: 16, 32 DDR2, DDR3, DDR3L:  Number of DQ per DQS...
  • Page 55 ECP5 and ECP5-5G High-Speed I/O Interface Figure 48. DDR_MEM Clock/Address/Command Tab Table 12 lists the values that can be used for the Clock/Address/Command settings. Table 12. DDR_MEM Clock/Address/Command Parameters GUI Option Range Default Value Number of Clocks DDR2: 1, 2, 4...
  • Page 56 LPDDR2: Blank LPDDR3= Number of chip Selects There is an additional tab called Advanced Settings for the ECP5 and ECP5-5G device that can be used to adjust the default DQS Read and Write Delay settings. Figure 49. DDR_MEM Advanced Settings Tab...
  • Page 57 ECP5 and ECP5-5G High-Speed I/O Interface Table 13. DDR_MEM Advanced Settings Tab Parameters GUI Option Range Default Value DQS Read Delay Adjustment FACTORYONLY, PLUS, MINUS FACTORYONLY DQS Read Delay Value Grey out (if DQS Delay Adjustment = FACTORY- ONLY) 0-255 (if DQS delay adjustment = PLUS)
  • Page 58 ECP5 and ECP5-5G High-Speed I/O Interface Figure 50. DDR Modules Paced Using Clarity Design Planner CLKDIV DQS Group ECLK tree IO Logic DDRDLL...
  • Page 59 ECP5 and ECP5-5G High-Speed I/O Interface DDR Software Primitives and Attributes This section describes the software primitives that can be used to implement all the DDR interfaces. These primi- tives are divided into ones that are used to implement the DDR data and ones for DDR Strobe signal or the Source Synchronous clock.
  • Page 60 ECP5 and ECP5-5G High-Speed I/O Interface DELAYF By default, the DELAYF is configured to factory delay settings based on the clocking structure. Users can overwrite the DELAY setting using the MOVE and DIRECTION control inputs. The LOADN will reset the delay back to the default value.
  • Page 61 ECP5 and ECP5-5G High-Speed I/O Interface DELAY Attribute Description Table 17 describes the attributes available for the DELAYF and DELAYG elements. The value of DEL_MODE is selected based on the interface that will be generated. These values are used to compensate for the clock injection time, hence should be selected based on clocking used.
  • Page 62 ECP5 and ECP5-5G High-Speed I/O Interface Table 18. DDRDLLA Port List Port Description Reference clock input to the DDRDLL. Should run at the same frequency as the clock to be delayed. Reset input to the DDRDLL Update control to update the delay code. When low, the delay code out of the UDDCNTLN DDRDLL is updated.

  • Page 63: Plus, Minus

    Generic DDR Input and Output Primitives The ECP5 and ECP5-5G device IDDR/ODDR modules support 2:1, 4:1 and 7:1 gearing modes on the left and right sides only. IDDR/ODDR modules on the top (and bottom for non-SERDES parts) will only support 2:1 due to lack of edge clocks.
  • Page 64 ECP5 and ECP5-5G High-Speed I/O Interface Table 23. IDDRX2F Port List Port Description DDR data input ECLK Fast edge clock SCLK Primary clock input (divide-by-2 of ECLK) Reset to DDR registers ALIGNWD This signal is used for word alignment. It will shift the word by one bit.
  • Page 65 ECP5 and ECP5-5G High-Speed I/O Interface Table 25. ODDRX1F Port List Port Description D0, D1 Parallel data input to ODDR (D0 is sent out first then D1) SCLK SCLK input Reset input DDR data output on both edges of SCLK ODDRX2F This primitive is used to receive Generic DDR with 2X gearing.
  • Page 66 ECP5 and ECP5-5G High-Speed I/O Interface Table 27. ODDR71B Port List Port Description D0, D1, D2, D3, D4, Parallel data input to the ODDR (D0 is sent out first and D6 last) D5, D6 ECLK ECLK input (3.5x speed of SCLK)
  • Page 67 ECP5 and ECP5-5G High-Speed I/O Interface Figure 61. DQSBUFM Primitive DQSBUFM DQSI DQSR90 READ [1:0] READCLKSEL0 DQSW READCLKSEL1 DQSW270 READCLKSEL2 RDPNTR[2:0] DDRDEL WRPNTR[2:0] ECLK DATAVALID SCLK BURSTDET DYNDELAY [7:0] PAUSE RDLOADN RDMOVE RDDIRECTION WRLOADN RDCFLAG WRMOVE WRCFLAG WRDIRECTION Table 28. DQSBUF Port List...
  • Page 68 1. Default value is set based on device characterization to achieve the 90 degree phase shift Input and Output Memory DDR Primitives The ECP5 and ECP5-5G device IDDR/ODDR modules support 4:1(2X) gearing mode that are used to implement the memory functions.

  • Page 69: Set, Reset

    ECP5 and ECP5-5G High-Speed I/O Interface Memory Input DDR Primitives The following are the primitives used to implement various memory DDR input configurations. IDDRX2DQA This primitive is used to implement the DDR2 memory input interface at higher speeds and DDR3 memory inter- face.
  • Page 70 ECP5 and ECP5-5G High-Speed I/O Interface Memory Output DDR Primitives for DQ Outputs The following are the primitives used to implement various memory DDR output configurations to generate the DQ outputs. ODDRX2DQA This primitive is used to generate DQ data output for DDR2 with x2 gearing and for DDR3 memory interface.
  • Page 71 ECP5 and ECP5-5G High-Speed I/O Interface Table 34. ODDRX2DQSB Port List Port Description D0, D1, D2, D3 Data input to the ODDR (D0 is output first, D3 last) ECLK ECLK input SCLK SCLK input DQSW DQSW includes write leveling phase shift from ECLK...
  • Page 72 ECP5 and ECP5-5G High-Speed I/O Interface Table 36. TSHX2DQSA Port List Port Description T0, T1 Tristate input (T0 is output first then T1) ECLK ECLK input (2x speed of SCLK) SCLK SCLK input DQSW DQSW includes write leveling phase shift from ECLK...
  • Page 73 ECP5 and ECP5-5G High-Speed I/O Interface Soft IP Modules The following soft IP Modules are available for use with the Generic DDR interfaces described above. All of the soft IP Modules can be generated using Clarity Designer. Table 38 below summarizes the list of soft IPs available and the ones that are optional vs the ones that will be automatically generated with the interface in Clarity Designer.
  • Page 74 ECP5 and ECP5-5G High-Speed I/O Interface Detailed Description of Each Soft IP GDDR_SYNC This module is needed to startup al RX Centered and all TX interfaces with 2x gearing. Figure 68. GDDR_SYNC Ports GDDR_SYNC DDR_ RESET STOP SYNC_CLK READY START Table 40.
  • Page 75 ECP5 and ECP5-5G High-Speed I/O Interface Table 41. RX_SYNC Port Description Port In/Out Descriptions SYNC_CLK Startup clock. This cannot be the RX_CLK or divided version. It can be other low speed continuously running clock. For example, oscillator clock. Active high reset to this sync circuit. When RST=1, STOP=0, FREEZE=0, UDDCNTLN=1, DLL_RESET=1, DDR_RESET=1, READY=0.
  • Page 76 ECP5 and ECP5-5G High-Speed I/O Interface BW_ALIGN This module is used to perform 7:1 video RX bit and word alignment. This module is optional and can be enabled in Clarity Designer. Figure 71. BW_ALIGN Ports BW_ALIGN ALIGNWORD PLL_ LOCK UPDATE...
  • Page 77 ECP5 and ECP5-5G High-Speed I/O Interface MIPI_FILTER This module is needed to filter low speed signal for MIPI RX. It filters out narrow pulses. It will allow pulse width above 40ns to pass. Figure 72. MIPI_FILTER Ports MIPI_FILTER FILTER_CLK LSOUT Table 44.

  • Page 78: Technical Support Assistance

    Date Version Change Summary November 2015 Added support for ECP5-5G. Changed document title to ECP5 and ECP5-5G High-Speed I/O Inter- face. Updated the following figures: — Figure 4, GDDRX1_RX.SCLK.Centered Interface (Static Delay) — Figure 5, GDDRX1_RX.SCLK.Centered Interface (Dynamic Data delay) —...

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