CAMERA LINK FC300ACL Instruction Manual page 4

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(2-2) Operational descriptions
● Progressive scanning
FC300ACL/FS300ACL having Interline transfer CCD with 659(H)×494(V) pixels captures the current image instantaneously.
Stable and sharp images can be obtained even in the asynchronous shutter mode, as each frame image is progressively
scanned continuously scanning all lines from top to bottom of the picture image at 1/90 sec. frame rate.
● Image output of the camera
Video signal output from the camera are amplified by CDS/Video amplifier, A/D converted, converted into 5-bit serial LVDS signal
via ChannelLink device, then output from CameraLink-compliant connector (26 pins) on the rear panel of the camera.
● External trigger input signal(CC1)
When the signal gets H level (positive logic) during operations in the asynchronous shutter mode, asynchronous shutter images
are obtained,
(2-3) Digital output signal
● Digital video output signal(DO -DO )
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These are 10-bit differential digital output signals compliant to CameraLink STD. 10-bit digital signals are converted to four pairs of
differential serial data signals in LVDS format (X0±-X3±) by the ChannelLink device in the camera.
(Note) These four pairs of differential serial data signals (X0±-X3±) contain each LDV,FDV signals below.
● Line data timing signal (LDV)
This signal represents the horizontal synchronous timing of the image signal. It is converted to serial data signal by the
ChannelLink device as well and is superimposed on the data (X0±-X3±) (Correspondent to LVAL signal of CameraLink STD)
● Frame data timing signal (FDV)
This signal represents the vertical synchronous timing of the image signal. It is converted to serial data signal by the ChannelLink
device as well and is superimposed on the data (X0±-X3±) (Correspondent to FVAL signal of CameraLink STD)
● Pixel clock (CLK)
This signal represents the timing of the image signal. It is converted to Xclk± signal of the CameraLink STD as the CLK signal of
the ChannelLink device
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