Interrupt Sharing; Design Overview - IBM AT 5170 Technical Reference

Interrupt Sharing
A definition for standardized hardware design has been
established that enables mUltiple adapters to share an interrupt
level. This section describes this design and discusses the
programming support required.
Note: Since interrupt routines do not exist in ROM for
protected mode operations, this design is intended to run
only in the microprocessor's real address mode.
Design Overview
Most interrupt-supporting adapters hold the
I
interrupt request
I
line (IRQ) at a low level and then drive the line high to cause an
interrupt. In contrast, the shared-interrupt hardware design
allows IRQ to float high through pull-up resistors on each
adapter. Each adapter on the line may cause an interrupt by
pulsing the line to a low level. The leading edge of the pulse arms
the 8259A Interrupt Controller; the trailing edge signals the
interrupt controller to cause the interrupt. The duration of this
r-....
pulse must be between 125 and 1,000 nanoseconds.
The adapters must have an
I
interrupt
I
status bit (INT) and a
I
interrupt enable
I
bit (ENA) that can be controlled and
monitored by its software.
Each adapter sharing an interrupt level must monitor the IRQ
line. When any adapter drives the line low, all other adapters on
that line must be prevented from issuing an interrupt request until
they are rearmed.
If an adapter's INT status bit is at a high level when the interrupt
sharing logic is rearmed, the adapter must reissue the interrupt.
This prevents lost interrupts if two adapters issue an interrupt at
the same time and an interrupt handler issues a Global Rearm
after servicing one of the adapters.
1-14 System Board