Infineon Technologies XC2200 User Manual page 433

Each OGUy unit generates 4 output signals that are distributed to the system (not all of
them are necessarily used, please refer to
• ERU_PDOUTy to directly output the pattern match information for gating purposes
in other modules (pattern match = 1).
• ERU_GOUTy to output the pattern match or pattern miss information (inverted
pattern match), or a permanent 0 or 1 under software control for gating purposes in
other modules.
• ERU_TOUTy as combination of a peripheral trigger, a pattern detection result
change event, or the ETLx trigger outputs TRxy to trigger actions in other modules.
• ERU_IOUTy as gated trigger output (ERU_GOUTy logical AND-combined with
ERU_TOUTy) to trigger interrupts (e.g. the interrupt generation can be gated to allow
interrupt activation during a certain time window).
6.8.6.1 Trigger Combination
The trigger combination logically OR-combines different trigger inputs to form a common
trigger ERU_TOUTy. Possible trigger inputs are:
• In each ETLx unit of the Input Channels, the trigger output TRxy can be enabled and
the trigger event can be directed to one of the OGUy units.
• One out of three peripheral trigger signals per OGUy can be selected as additional
trigger source. These peripheral triggers are generated by on-chip peripheral
modules, such as capture/compare or timer units. The selection is done by bit field
EXOCONy.ISS.
• In the case that at least one pattern detection input is enabled (EXOCONy.IPENx)
and a change of the pattern detection result from pattern match to pattern miss (or
vice-versa) is detected, a trigger event is generated to indicate a pattern detection
result event (if enabled by ECOCONy.GEEN).
The trigger combination offers the possibility to program different trigger criteria for
several input signals (independently for each Input Channel) or peripheral signals, and
to combine their effects to a single output, e.g. to generate an interrupt or to start an ADC
conversion. This combination capability allows the generation of an interrupt per OGU
that can be triggered by several inputs (multitude of request sources -> one reaction).
The following table describes the peripheral trigger connections for the OGUy stages.
The selection is defined by the bit fields ISS in registers
EXOCON1 (for OGU1),
User's Manual
SCU, V1.13
EXOCON2 (for OGU2), or
6-173
System Units (Vol. 1 of 2)
System Control Unit (SCU)
Section 6.8.7):
EXOCON3
XC2200 Derivatives
EXOCON0 (for OGU0),
(for OGU3).
V2.1, 2008-08