Infineon Technologies XC2200 User Manual

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U s e r ' s M a n u a l , V 2 . 1, Au g . 2 0 0 8

XC2200 Derivatives

1 6 / 3 2 - B i t S i n g l e -C h i p M i c r o c o n t r o l l e r w i t h

3 2 - B i t P e r f o r m a n c e

V o l u m e 1 ( o f 2 ) : S y s t e m U n i ts

M i c r o c o n t r o l l e rs

Table of Contents

Summary of Contents for Infineon Technologies XC2200

Page 1 U s e r ’ s M a n u a l , V 2 . 1, Au g . 2 0 0 8 XC2200 Derivatives 1 6 / 3 2 - B i t S i n g l e -C h i p M i c r o c o n t r o l l e r w i t h...
Page 2 Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life.
Page 3 U s e r ’ s M a n u a l , V 2 . 1, Au g . 2 0 0 8 XC2200 Derivatives 1 6 / 3 2 - B i t S i n g l e -C h i p M i c r o c o n t r o l l e r w i t h...
Page 4 XC2200 Derivatives System Units (Vol. 1 of 2) XC2200 Revision History: V2.1, 2008-08 Previous Version(s): V2.0, 2007-12 V1.0, 2007-06 (XC2000) V0.1, 2007-03, Draft version Page Subjects (major changes since last revision) Derivative synopsis table replaced by reference to Data Sheets...
Page 5: Summary Of Chapters
XC2200 Derivatives System Units (Vol. 1 of 2) Summary Of Chapters Summary Of Chapters This User’s Manual consists of two Volumes, “System Units” and “Peripheral Units”. For a quick overview this table of chapters summarizes both volumes, so you immediately can find the reference to the desired section in the corresponding document ([1] or [2]).
Page 6: Table Of Contents
XC2200 Derivatives System Units (Vol. 1 of 2) Table Of Contents Table Of Contents This User’s Manual consists of two Volumes, “System Units” and “Peripheral Units”. For your convenience this table of contents (and also the keyword and register index) lists both volumes, so you can immediately find the reference to the desired section in the corresponding document ([1] or [2]).
Page 7: Table Of Contents
XC2200 Derivatives System Units (Vol. 1 of 2) Table Of Contents 3.9.2 Operating Modes ........3-20 [1] 3.9.3...
Page 8 XC2200 Derivatives System Units (Vol. 1 of 2) Table Of Contents 4.8.3 Multiply and Divide Unit ....... . 4-62 [1] DSP Data Processing (MAC Unit) .
Page 9 XC2200 Derivatives System Units (Vol. 1 of 2) Table Of Contents 6.2.2 WUT Registers ........6-46 [1] Reset Operation .
Page 10 XC2200 Derivatives System Units (Vol. 1 of 2) Table Of Contents 6.11.2 Overview ......... . . 6-210 [1] 6.11.3...
Page 11 XC2200 Derivatives System Units (Vol. 1 of 2) Table Of Contents 7.3.10 Port 9 ..........7-28 [1] 7.3.11...
Page 12 XC2200 Derivatives System Units (Vol. 1 of 2) Table Of Contents 10.6.4 CAN Bootstrap Loader ....... . . 10-26 [1] 10.6.5...
Page 13 XC2200 Derivatives System Units (Vol. 1 of 2) Table Of Contents 15.7 RTC Interrupt Generation ....... . 15-13 [2] 15.8...
Page 14 XC2200 Derivatives System Units (Vol. 1 of 2) Table Of Contents 17.4 Capture Mode Operation ....... . . 17-14 [2] 17.5...
Page 15 XC2200 Derivatives System Units (Vol. 1 of 2) Table Of Contents 18.6.4 Hall Mode for Brushless DC-Motor Control ....18-75 [2] 18.7 Modulation Control Registers ......18-77 [2] 18.7.1...
Page 16 IIS Protocol Registers ....... . 19-198 [2] 19.7 USIC Implementation in XC2200 ......19-204 [2] 19.7.1 Implementation Overview .
Page 17 XC2200 Derivatives System Units (Vol. 1 of 2) Table Of Contents 20.2.6 Message Acceptance Filtering ......20-21 [2] 20.2.7...
Page 18: Introduction
Infineon’s XC2200 devices were specifically designed to fulfill the requirements of today’s and future body applications by providing high performance (control and DSP) at low power consumption. All XC2200 members are fully software and pin compatible. Designers of automotive body systems can choose the optimal combination of memory, peripherals, temperature, and packaging to match the application’s requirements.
Page 19 The complete Pro Electron conforming designations are listed in the respective Data Sheets. Some sections of this manual do not refer to all of the XC2200 derivatives which are currently available or planned (such as devices with different types of on-chip memory or peripherals).
Page 20: Members Of The 16-Bit Microcontroller Family
XC2200 Derivatives System Units (Vol. 1 of 2) Introduction Members of the 16-bit Microcontroller Family The microcontrollers in the Infineon 16-bit family have been designed to meet the high performance requirements of real-time embedded control applications. The architecture of this family has been optimized for high instruction throughput and minimized response time to external stimuli (interrupts).
Page 21 Note: As the architecture and the basic features, such as the CPU core and built-in peripherals, are identical for most of the currently offered versions of the XC2200, descriptions within this manual that refer to the “XC2200” also apply to the other variations, unless otherwise noted.
Page 22: Summary Of Basic Features
System Units (Vol. 1 of 2) Introduction Summary of Basic Features The XC2200 devices are enhanced members of the Infineon XC2000 Family of full featured single-chip CMOS microcontrollers. This manual covers several device types are covered in this manual. The various derivates are referred to as XC2200 throughout this manual.
Page 23 XC2200 Derivatives System Units (Vol. 1 of 2) Introduction Note: The system stack can be located in any memory area within the complete addressing range. High Performance 16-bit CPU with Five-Stage Pipeline and MAC Unit • Single clock cycle instruction execution •...
Page 24 XC2200 Derivatives System Units (Vol. 1 of 2) Introduction • Programmable vector table (start location and step-width) 8-Channel Peripheral Event Controller (PEC) • Interrupt driven single cycle data transfer • Programmable PEC interrupt request level, (15 down to 8) • Transfer count option (standard CPU interrupt after programmable number of PEC transfers) •...
Page 25 XC2200 Derivatives System Units (Vol. 1 of 2) Introduction Green Plastic Low-Profile Quad Flat Pack (LQFP) Packages • PG-LQFP-144, 20 × 20 mm body, 0.5 mm (19.7 mil) lead spacing, surface mount technology • PG-LQFP-100, 14 × 14 mm body, 0.5 mm (19.7 mil) lead spacing,...
Page 26: Abbreviations
XC2200 Derivatives System Units (Vol. 1 of 2) Introduction Abbreviations The following acronyms and terms are used within this document: Analog Digital Converter Address Latch Enable Arithmetic and Logic Unit Asynchronous/synchronous Serial Channel Controller Area Network (License Bosch) CAPCOM CAPture and COMpare unit...
Page 27: Naming Conventions
XC2200 Derivatives System Units (Vol. 1 of 2) Introduction Programmable Logic Array Phase Locked Loop Program Management Unit Power Validation Circuit Pulse Width Modulation Random Access Memory RISC Reduced Instruction Set Computing Read Only Memory Real Time Clock Special Function Register...
Page 28: Architectural Overview
Architectural Overview Architectural Overview The architecture of the XC2200 core combines the advantages of both RISC and CISC processors in a very well-balanced way. This computing and controlling power is completed by the DSP-functionality of the MAC-unit. The XC2200 integrates this powerful CPU core with a set of powerful peripheral units into one chip and connects them very efficiently.
Page 29: Basic Cpu Concepts And Optimizations
XC2200 Derivatives System Units (Vol. 1 of 2) Architectural Overview Basic CPU Concepts and Optimizations The main core of the CPU consists of a set of optimized functional units including the instruction fetch/processing pipelines, a 16-bit Arithmetic and Logic Unit (ALU), a 40-bit Multiply and Accumulate Unit (MAC), an Address and Data Unit (ADU), an Instruction Fetch Unit (IFU), a Register File (RF), and dedicated Special Function Registers (SFRs).
Page 30 XC2200 Derivatives System Units (Vol. 1 of 2) Architectural Overview Summary of CPU Features • Opcode fully upward compatible with C166 Family • 2-stage instruction fetch pipeline with FIFO for instruction pre-fetching • 5-stage instruction execution pipeline • Pipeline forwarding controls data dependencies in hardware •...
Page 31: High Instruction Bandwidth/Fast Execution
Architectural Overview 2.1.1 High Instruction Bandwidth/Fast Execution Based on the hardware provisions, most of the XC2200’s instructions can be executed in just one clock cycle (1/f ). This includes arithmetic instructions, logic instructions, and move instructions with most addressing modes.
Page 32: Powerful Execution Units
XC2200 Derivatives System Units (Vol. 1 of 2) Architectural Overview 2.1.2 Powerful Execution Units The 16-bit Arithmetic and Logic Unit (ALU) performs all standard (word) arithmetic and logical operations. Additionally, for byte operations, signals are provided from bits 6 and 7 of the ALU result to set the condition flags correctly. Multiple precision arithmetic is provided through a ‘CARRY-IN’...
Page 33: High Performance Branch-, Call-, And Loop-Processing
XC2200 Derivatives System Units (Vol. 1 of 2) Architectural Overview 2.1.3 High Performance Branch-, Call-, and Loop-Processing Pipelined execution delivers maximum performance with a stream of subsequent instructions. Any disruption requires the pipeline to be refilled and the new instruction to step through the pipeline stages.
Page 34: Consistent And Optimized Instruction Formats
The high performance of the CPU-hardware can be utilized efficiently by a programmer by means of the highly functional XC2200 instruction set which includes the following instruction classes: • Arithmetic Instructions •...
Page 35: Programmable Multiple Priority Interrupt System
2.1.5 Programmable Multiple Priority Interrupt System The XC2200 provides 96 separate interrupt nodes that may be assigned to 16 priority levels with 8 group priorities on each level. Most interrupt sources are connected to a dedicated interrupt node. In some cases, multi-source interrupt nodes are incorporated for efficient use of system resources.
Page 36: Interfaces To System Resources
2.1.6 Interfaces to System Resources The CPU of the XC2200 interfaces to the system resources via several bus systems which contribute to the overall performance by transferring data concurrently. This avoids stalling the CPU because instructions or operands need to be transferred.
Page 37: On-Chip System Resources
PEC services are very well suited, for example, to moving register contents to/from a memory table. The XC2200 has eight PEC channels, each of which offers such fast interrupt- driven data transfer capabilities.
Page 38 XC2200 Derivatives System Units (Vol. 1 of 2) Architectural Overview Up to 768 Kbytes of on-chip Flash memory store code or constant data. The on-chip Flash memory consists of 2 or 3 Flash modules, each built up from 4-Kbyte sectors. Each...
Page 39 12 Mbytes (approximately, see Table 2-1) of external RAM and/or ROM can be connected to the microcontroller. The External Bus Interface also provides access to external peripherals. Table 2-1 XC2200 Memory Map Address Area Start Loc. End Loc. Area Size Notes IMB register space FF’FF00...
Page 40 XC2200 Derivatives System Units (Vol. 1 of 2) Architectural Overview Table 2-1 XC2200 Memory Map (cont’d) Address Area Start Loc. End Loc. Area Size Notes SFR area 00’FE00 00’FFFF 0.5 Kbyte – Dual-Port RAM 00’F600 00’FDFF 2 Kbytes – Reserved for DPRAM 00’F200...
Page 41 To meet the needs of designs where more memory is required than is provided on chip, up to 12 Mbytes of external RAM/ROM/Flash or peripherals can be connected to the XC2200 microcontroller via its external bus interface. All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC).
Page 42: On-Chip Peripheral Blocks
These built-in peripherals either allow the CPU to interface with the external world or provide functions on-chip that otherwise would need to be added externally in the respective system. The XC2200 generic peripherals are: • General Purpose Timer Unit (GPT1, GPT2) •...
Page 43 XC2200 Derivatives System Units (Vol. 1 of 2) Architectural Overview Peripheral Interfaces The on-chip peripherals generally have two different types of interfaces: an interface to the CPU and an interface to external hardware. Communication between the CPU and peripherals is performed through Special Function Registers (SFRs) and interrupts. The SFRs serve as control/status and data registers for the peripherals.
Page 44 • Reserved Bits: Some of the bits which are contained in the XC2200’s SFRs are marked as ‘Reserved’. User software should never write ‘1’s to reserved bits. These bits are currently not implemented and may be used in future products to invoke new functions.
Page 45 XC2200 Derivatives System Units (Vol. 1 of 2) Architectural Overview Table 2-2 Compare Modes (CAPCOM2) Compare Modes Function Mode 0 Interrupt-only compare mode; several compare interrupts per timer period are possible Mode 1 Pin toggles on each compare match; several compare events per timer period are possible Mode 2 Interrupt-only compare mode;...
Page 46 XC2200 Derivatives System Units (Vol. 1 of 2) Architectural Overview Capture/Compare Units CCU6 The CCU6 units support generation and control of timing sequences on up to three 16- bit capture/compare channels plus one independent 16-bit compare channel. In compare mode, the CCU6 units provide two output signals per channel which have inverted polarity and non-overlapping pulse transitions (deadtime control).
Page 47 XC2200 Derivatives System Units (Vol. 1 of 2) Architectural Overview General Purpose Timer Unit (GPT1, GPT2) The GPT12E unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication.
Page 48 The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows the XC2200 to measure absolute time differences or to perform pulse multiplication without software overhead.
Page 49 Architectural Overview Real Time Clock (RTC) The Real Time Clock (RTC) module of the XC2200 is directly clocked wih a separate clock signal. Several internal and external clock sources can be selected via register RTCCLKCON. It is, therefore, independent from the selected clock generation mode of the XC2200.
Page 50 For applications that require less analog input channels, the remaining channel inputs can be used as digital input port pins. The A/D converters of the XC2200 support two types of request sources which can be triggered by several internal and external events.
Page 51 XC2200 Derivatives System Units (Vol. 1 of 2) Architectural Overview Universal Serial Interface Channel Modules (USIC) Each USIC channel can be individually configured to match the application needs, e.g. the protocol can be selected or changed during run time without the need for a reset. The following protocols are supported: •...
Page 52 XC2200 Derivatives System Units (Vol. 1 of 2) Architectural Overview In addition to the FIFO buffer, a bypass mechanism allows the introduction of high- priority data without flushing the FIFO buffer. • Transmit control information For each data word to be transmitted, a 5-bit transmit control information has been added to automatically control some transmission parameters, such as word length, frame length, or the slave select control for the SPI protocol.
Page 53 XC2200 Derivatives System Units (Vol. 1 of 2) Architectural Overview To reach a desired baud rate, two criteria have to be respected, the module capability and the application environment. The module capability is defined with respect to the module’s input clock frequency f , being the base for the module operation.
Page 54 XC2200 Derivatives System Units (Vol. 1 of 2) Architectural Overview The USIC module contains two independent communication channels, with structure shown in Figure 2-3. The data shift unit and the data buffering of each channel support full-duplex data transfers. The protocol-specific actions are handled by protocol pre-processors (PPP).
Page 55 XC2200 Derivatives System Units (Vol. 1 of 2) Architectural Overview MultiCAN Module The MultiCAN module contains up to five independently operating CAN nodes with Full- CAN functionality which are able to exchange Data and Remote Frames via a gateway function. Transmission and reception of CAN frames is handled in accordance with CAN specification V2.0 B (active).
Page 56 XC2200 Derivatives System Units (Vol. 1 of 2) Architectural Overview MultiCAN Features • CAN functionality conforms to CAN specification V2.0 B active for each CAN node (compliant to ISO 11898) • Up to Five independent CAN nodes • Up to 128 independent message objects (shared by the CAN nodes) •...
Page 57 System Units (Vol. 1 of 2) Architectural Overview Parallel Ports The XC2200 derivatives are available in two different packages: • In LQFP-144, they provide up to 118 I/O lines which are organized into 11 input/output ports and 2 input ports.
Page 58 XC2200 Derivatives System Units (Vol. 1 of 2) Architectural Overview Table 2-3 Summary of the XC2200’s Parallel Ports (cont’d) Port Width Width Alternate Functions Port 4 Chip select signals, Serial interface lines of CAN2, Input/Output lines for CAPCOM2, Timer control signals...
Page 59: Clock Generation
The Clock Generation Unit uses a programmable on-chip PLL with multiple prescalers to generate the clock signals for the XC2200 with high flexibility. The system clock f is the reference clock signal, which can be output to the external system. The system clock f can be derived from several internal and external clock sources.
Page 60: Power Management
Architectural Overview Power Management The XC2200 can operate within a wide supply voltage range from 3 V to 5 V. The internal core supply voltage is generated via on-chip Embedded Voltage Regulators and is supervised by on-chip Power Validation Circuits.
Page 61: On-Chip Debug Support (Ocds)
On-Chip Debug Support (OCDS) The On-Chip Debug Support system provides a broad range of debug and emulation features built into the XC2200. The user software running on the XC2200 can thus be debugged within the target system environment. The OCDS is controlled by an external debugging device via the debug interface, consisting of the IEEE-1149-conforming JTAG port and a break interface.
Page 62: Memory Organization
Memory Organization Memory Organization The memory space of the XC2200 is configured in a “Von Neumann” architecture. This means that code and data are accessed within the same linear address space. All of the physically separated memory areas, including internal ROM and Flash, internal RAM, the internal Special Function Register Areas (SFRs and ESFRs), the internal IO area, and external memory are mapped into one common address space.
Page 63 System Units (Vol. 1 of 2) Memory Organization The XC2200 provides a total addressable memory space of 16 Mbytes. This address space is arranged as 256 segments of 64 Kbytes each, and each segment is again subdivided into four data pages of 16 Kbytes each (see Figure 3-1).
Page 64: Address Mapping
Table 3-1) are mapped into one contiguous address space. All sections can be accessed in the same way. The memory map of the XC2200 contains some reserved areas, so future derivatives can be enhanced in an upward-compatible fashion. Note: Table 3-1 shows the maximum available memory areas.
Page 65 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization Accesses to the shaded areas are reserved. In devices with external bus interface these accesses generate external bus accesses. The areas marked with “<” are slightly smaller than indicated, see column “Notes”.
Page 66: Special Function Register Areas
Memory Organization Special Function Register Areas The Special Function Registers (SFRs) controlling the system and peripheral functions of the XC2200 can be accessed via four dedicated address areas: • 512-byte SFR area (located above the internal RAM: 00’FFFF … 00’FE00 •...
Page 67 The functions of the CPU, the bus interface, the IO ports, and the on-chip peripherals of the XC2200 are controlled via a number of Special Function Registers (SFRs). All Special Function Registers can be addressed via indirect and long 16-bit addressing modes.
Page 68 <CP> + 06 <CP> + 04 <CP> + 02 <CP> + 00 The XC2200 supports fast register bank (context) switching. Multiple global register banks can physically exist within the DPRAM at the same time. Only the global register User’s Manual V2.1, 2008-08...
Page 69 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization bank selected by the Context Pointer register (CP) is active at a given time, however. Selecting a new active global register bank is simply done by updating the CP register.
Page 70: Data Memory Areas
3.10). However, both data memory areas provide the fastest access. Depending on the device additional on-chip memory areas may exist with the special purpose to retain data while the system power domain is switched off. The XC2200 contains: • The Stand-By RAM (SBRAM).
Page 71 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization An area of 24 Kbytes is dedicated to DSRAM (00’8000 … 00’DFFF ). The locations without implemented DSRAM are reserved. Stand-By RAM (SBRAM) The SBRAM provides 1 Kbyte of memory supplied by the wake-up power domain (DMP_M).
Page 72: Program Memory Areas
System Units (Vol. 1 of 2) Memory Organization Program Memory Areas The XC2200 provides two on-chip program memory areas for code/data storage: • The Program Flash/ROM stores code and constant data. Flash memory is (re-) programmed by the application software or flash loaders, ROM is mask-programmed in the factory.
Page 73: Program/Data Sram (Psram)
System Units (Vol. 1 of 2) Memory Organization 3.4.1 Program/Data SRAM (PSRAM) The XC2200 provides 64 Kbytes of PSRAM (E0’0000 … E0’FFFF ). The PSRAM provides fast code execution without initial delays. Therefore, it supports non-sequential code execution, for example via the interrupt vector table.
Page 74: Non-Volatile Program Memory (Flash)
Write accesses to the read-only part are blocked and a trap can be activated. 3.4.2 Non-Volatile Program Memory (Flash) The XC2200 provides up to 764 Kbytes of program Flash (C0’0000 … CB’FFFF Code and data fetches are always 64-bit aligned, using byte select lines for word and byte data.
Page 75: System Stack
System Units (Vol. 1 of 2) Memory Organization System Stack The system stack may be defined anywhere within the XC2200’s memory areas (including external memory). For all system stack operations the respective stack memory is accessed via a 24-bit stack pointer. The Stack Pointer (SP) register provides the lower 16 bits of the stack pointer (stack pointer offset), the Stack Pointer Segment (SPSEG) register adds the upper 8 bits of the stack pointer (stack segment).
Page 76: Io Areas
System Units (Vol. 1 of 2) Memory Organization IO Areas The following areas of the XC2200’s address space are marked as IO area: • The external IO area is provided for external peripherals (or memories) and also comprises the on-chip LXBus-peripherals, such as the CAN or USIC modules. It is located from 20’0000...
Page 77: External Memory Space
Memory Organization External Memory Space The XC2200 is capable of using an address space of up to 16 Mbytes. Only parts of this address space are occupied by internal memory areas or are reserved. A total area of approximately 12 Mbytes references external memory locations. This external memory is accessed via the XC2200’s external bus interface.
Page 78: Crossing Memory Boundaries
Memory Organization Crossing Memory Boundaries The address space of the XC2200 is implicitly divided into equally sized blocks of different granularity and into logical memory areas. Crossing the boundaries between these blocks (code or data) or areas requires special attention to ensure that the controller executes the desired operations.
Page 79: Embedded Flash Memory
Chapter 3.10 describes how the flash memory is embedded into the memory architecture of the XC2200 and lists all SFRs that affect its behavior. 3.9.1 Definitions This section defines the nomenclature and some abbreviations as a base for the rest of the document.
Page 80 “array” this contains as well all accompanying logic as assembly buffer, high voltage logic and the digital logic that allows to operate them in parallel. • Memory: The complete flash memory of the XC2200 consists of 3 flash arrays. This structure is visualized in Figure 3-5.
Page 81: Operating Modes
XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization 256 KB Array Sect or Num ber Sector Page Num ber Page Block Num ber Sector Page Block 137 Bits Combined flash memory byte address Array Sect or Page Block...
Page 82 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization • In case of detecting an execution error like attempting to write to a write protected range, sending a wrong password, after all sequence errors. For the long lasting commands the read mode stays active until the last command of the sequence is received and the operation is started.
Page 83: Operations
XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization 3.9.3 Operations The flash memory supports the following operations: • Instruction fetch. • Data read. • Command sequences to change data and control the protection. 3.9.3.1 Instruction Fetch from Flash Memory Instructions are fetched by the PMU in groups of aligned 64 bits.
Page 84 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization 3.9.3.2 Data Reads from Flash Memory Data reads are issued by the DMU. Data is always requested in 16-bit words. The flash memory delivers for every read request 128 bits plus ECC as described in “Instruction...
Page 85 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization 3.9.3.4 Command Sequences As described before changing data in the flash memory is performed with command sequences. Table 3-3 Command Sequence Overview Command Sequence Description Details on Page Reset to Read...
Page 86: Details Of Command Sequences
XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization 3.9.4 Details of Command Sequences The description defines the command sequence with pseudo assembler code. It is “pseudo” because all addresses are direct addresses which is generally not possible in real assembler code.
Page 87 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization Reset to Read Arguments: – Definition: MOV XXAA , XXF0 Timing: One cycle command that does not set any “BUSY” flags. But note that an immediately following write access to the IMB Core is stalled for a few clock cycles during which the IMB Core is busy with aborting a previous command.
Page 88 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization The argument “MR” defines the read margin: • : normal read margin. • : hard read 0 margin. • : alternate hard read 0 margin. • : hard read 1 margin.
Page 89 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization not disabled when the “Enter Page Mode” command is received, the command is not executed, and the protection error flag PROER is set in the IMB_FSR. Enter Security Page Mode...
Page 90 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization The high order bits XX should address the target page. The IMB Core takes always the page address that was used by the last “Enter Page Mode” command. When the 128-bit block assembly register of the IMB Core is filled completely after 8 “Load Page...
Page 91 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization “Program Page” command is only accepted if the addressed flash module is in Page Mode (otherwise, a sequence error is reported instead of execution). With the “Program Page” command, the page mode is terminated, indicated by resetting the...
Page 92 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization Read accesses to the busy flash module are not possible. Read accesses to the not busy flash module are especially supported. Reading a busy flash module stalls until the flash module becomes ready again.
Page 93 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization Erase Security Page Arguments: SECPA Definition: MOV XXAA , XX80 MOV XX54 , XXA5 MOV SECPA, XX53 Timing: 3-cycle command that sets BUSY for the whole erasing duration. Description: The addressed security page is erased.
Page 94 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization “Reset to Read” command, it is interpreted as password and the reset is not executed. The 16-bit passwords are internally compared with the keywords out of the “Security Page 0”. If one or more passwords are not identical to their related keywords, the protected sectors remain in the locked state and a protection error (PROER) is indicated in the Flash status register.
Page 95 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization • The next Application Reset (including HW and SW reset) is received. Re-Enable Read/Write Protection Arguments: – Definition: MOV XX5E , XXXX Timing: 1-cycle command that does not set any busy flags.
Page 96: Data Integrity
XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization 3.9.5 Data Integrity This section describes means for detecting and preventing the inadvertent modification of data in the flash memory. 3.9.5.1 Error Correcting Codes (ECC) With very low probability a flash cell can become disturbed or lose its data value faster than specified.
Page 97 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization Therefore the application must ensure that flash processes can perform uninterrupted and under the defined operating conditions, e.g. by early brown-out warning that prevents the software from starting flash processes.
Page 98 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization and thus the execution of injected OCDS instructions. In case of start after reset in internal flash, all flash access operations are controlled by the flash-internal user code and are therefore allowed, as long as not especially disabled by the user, e.g. before enabling the debug interface.
Page 99: Protection Handling Details
XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization 3.9.6 Protection Handling Details As shortly described in “Protection Overview” on Page 3-36 the flash memory can be in different protection states. The protection handling can be separated into different...
Page 100 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization 3.9.6.1 The Lower Layer “Physical State” After reset the protection state of the device is restored from the following information: • The security page 1 contains a “lock code”. This consists of two words of data (32 bits).
Page 101 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization The command “Disable Read Protection” sets RPRODIS to 1 if the correct passwords that are stored in SecP0 are supplied. If incorrect passwords are entered the bit PROER is set and RPRODIS stays unchanged. As protection against “brute force attacks” that search the correct password the password detection is locked.
Page 102 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization Table 3-4 “Flash State” Determining RPA and WPA (cont’d) IMB_ IMB_ IMB_ IMB_ IMB_ Resulting Security Level in RPA and WPA FSR. FSR. FSR. FSR. FSR. PROI PROI ODIS ODIS Errored protection state (see below): –...
Page 103 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization Table 3-6 Effective Write Security (cont’d) Security Level 1 | # 1 | # Global write protection. 1 | # Sector specific write protection depending on IMB_PROCONx. To summarize: •...
Page 104: Protection Handling Examples
XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization • A successful “Disable Write Protection” sets WPRODIS and clears WPA. • “Re-Enable Read/Write Protection” clears RPRODIS and WPRODIS and sets RPA and WPA according to Table 3-4 depending on PROIN, PROINER and RPRO.
Page 105 FF'0080 flash_security_page_layout.vsd Figure 3-8 Layout of Security Pages Generally the 16-bit words are stored as always in the XC2200 in little endian format. • The PWx words contain the passwords. • The double bit RPRO is stored as in the related ISFR...
Page 106 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization 3.9.7 Protection Handling Examples Some examples on how to work with the protection system. Delivery State The device is delivered in the “non-protected state”. Security page 1 is erased (so it does not contain the “lock code” AA55AA55 Security page 0 is erased and so “invalid”...
Page 107 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization Changing Passwords or Security Settings Changing the passwords is a delicate operation. The interrelation of the two security pages must be kept in mind. Usually in the protected state the SecP1 contains the lock code. First write protection must be disabled with the correct passwords.
Page 108: Eeprom Emulation
EEPROM. There is quite a number of algorithms for efficiently using flash memory as EEPROM. The following section describes one (the most simple) of these algorithms. It should be noted that the XC2200 does not offer the customer any hardware means for EEPROM emulation. All of the following must be realized by software.
Page 109 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization page after programming the new one. Additionally a CRC check could be performed over the group. As all involved pages are re-used cyclically the endurance from customer perspective is increased by the factor N. N must be chosen high enough to fulfill endurance and retention requirements.
Page 110: Interrupt Generation
XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization 3.9.9 Interrupt Generation Long lasting processes (these are mainly: program page, erase page, erase sector and margin changes) set the IMB_FSR.BUSY flag of one flash module when accepting the request and reset this flag after finishing the process. Software is required to poll the busy flag in order to determine the end of the operation.
Page 111 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization • Program the sector with data. A common protection against software crashes is to fill the unused part of the sector with trap codes. • Change the read level to hard margin 0.
Page 112: On-Chip Program Memory Control
FF’FFFF . Included are the program SRAM, the embedded flash memories and central control logic called “IMB Core”. In the XC2200 device the IMB contains the following memories: • 764 KB flash memory in three independent modules. • 64 KB program SRAM (see Section 3.4.1).
Page 113 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization instructions on the predicted branch in advance. In case of a misprediction this interface can abort outstanding requests and continues fetching on the correct branch. As the CPU can consume up to one 32-bit instruction per clock cycle the performance of this interface determines the CPU performance.
Page 114: Register Interface
XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization 3.10.2 Register Interface “IMB Registers” on Page 3-53 describes the special function registers of the IMB. “System Control Registers” on Page 3-64 the special function registers that influence the IMB but are not allocated to the IMB address range are described.
Page 115 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization Field Bits Typ Description WSFLASH [2:0] Wait States for Flash Access Number of wait cycles after which the IMB expects read data from the flash memory. This field determines as well the read timing of the PSRAM in the flash emulation address range.
Page 116 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization Field Bits Typ Description [15:14] rw Disable Data Read from Flash Memory “01”: Short notation DDF = 1. If RPA = 1 data cannot be read from flash memory. If RPA = 0 this field has no effect.
Page 117 + 1000 *PSPROT and ends at E8’FFFF for XC2200. So with PSPROT=00 the complete PSRAM is writable. In case of XC2200 with PSPROT=10 bigger the complete implemented PSRAM is write- protected. Interrupt Control Interrupt control and status. Reset by Application Reset.
Page 118 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization Field Bits Typ Description Interrupt Enable If set, the interrupt signal of the IMB gets activated when ISR is set. DIDTRP Disable Instruction Fetch Double Bit Error Trap If set, a double bit ECC error does not cause the replacement of the fetched data by a trap instruction.
Page 119 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization Flash State Flash state. Split into registers IMB_FSR_BUSY, IMB_FSR_OP, IMB_FSR_PROT. The protection relevant fields or IMB_FSR_PROT are described in “Protection Handling Details” on Page 3-38. The registers are reset by the Application Reset with the exception of “ERASE”, “PROG”, and “OPER”.
Page 120 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization Field Bits Typ Description PROG Program Task Indication This bit is set when a program task is started. The affected flash module is indicated by a BUSY bit. The PROG bit is not automatically reset but must be cleared by a “Clear...
Page 121 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization Field Bits Typ Description OPER Operation Error The IMB Core maintains internal bits that are set when starting a program or erase process. They are cleared when this process finishes. These bits are not reset by an Application Reset but only by a System Reset.
Page 122 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization Field Bits Typ Description PROER Protection Error Set by a violation of the installed protection. Reset by “Clear Status” and “Reset to Read” commands or an Application Reset. ISBER Instruction Fetch Single Bit Error Set if during instruction fetch a single-bit ECC error was detected (and corrected).
Page 123 Hard Read 2 Same for flash module 2. Protection Configuration Protection configuration register of each implemented flash module. In XC2200 PROCON0, PROCON1 and PROCON2 are implemented. PROCON0 is described below. PROCON1 (at address FF’FF12 ) and PROCON2 (at address FF’FF14 ) have the same functionality for the other two flash modules.
Page 124 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization IMB_PROCONx (x=0-2) Protection Configuration. ISFR (FF FF10 +2*x) Reset value: 0000 – – – – – – S9U S8U S7U S6U S5U S4U S3U S2U S1U S0U – – –...
Page 125 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization 3.10.2.2 System Control Registers These registers are used to wakeup and shutdown parts of the memory sub-system. Table 3-8 Registers Address Space Module Base Address End Address Note 0000 0FFF...
Page 126 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization Field Bits Type Description COMCFG [13:12] rw Clock Off Mode Configuration This bit field defines if the shutdown request is activated in clock-off mode. If COMCFG[13] is 1 the shutdown request is activated in clock-off mode (i.e.
Page 127 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization Field Bits Type Description BPMODEN Bit Protection for MODEN This bit enables the write access to the bit MODEN. It always reads 0. It is only active during the write access cycle.
Page 128 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization Field Bits Type Description COMCFG [13:12] rw Clock Off Mode Configuration This bit field defines if the power-down request is activated in clock-off mode. If COMCFG[13] is 1 the power-down request is activated in clock-off mode (i.e.
Page 129: Startup, Shutdown
XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization 3.10.3 Startup, Shutdown The startup and shutdown of memories and the processor sub-system is described in the Programmier’s Guide. Also the use of the Kernel Control registers is described there.
Page 130: Error Reporting Summary
XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization 3.10.4 Error Reporting Summary Table 3-10 summarizes the types of detected errors and the possible reactions. Table 3-10 IMB Error Reporting Error Reaction Data read from PSRAM with parity error.
Page 131: Data Retention Memories
The flash protection can not be by-passed by accessing the reserved memory ranges. 3.11 Data Retention Memories This section describes the usage of the special purpose data memories Stand-By RAM (SBRAM) and Marker Memory (MKMEM). Depending on the device not all of them are available. The XC2200 contains: • SBRAM. • MKMEM.
Page 132: Stand-By Ram Accesses
XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization Both are supplied by the wake-up power domain (DMP_M) and retain their data while the system power domain (DMP_1) is switched off. 3.11.1 Stand-By RAM Accesses The SBRAM is not mapped into the address range of the processor. All accesses are done via the 4 SFRs SBRAM_WADD, SBRAM_RADD, SBRAM_DATA0 and SBRAM_DATA1.
Page 133 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization from write to read accesses SBRAM_RADD should be written again before reading SBRAM_DATAx. Note: Because of this pre-reading feature and the auto-increment behavior it is important to initialize always the address following the last data in order to prevent parity/ECC errors due to this pre-reading.
Page 134: Stand-By Ram Registers
XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization 3.11.2 Stand-By RAM Registers This section describes the SBRAM register interface in detail. Table 3-11 Registers Overview Register Short Register Long Name Offset Page Number Name Address SBRAM_RADD SBRAM Read Address...
Page 135 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization Field Bits Type Description Modification This bit indicates whether the last read access to SBRAM data lead to an automatic increment of RPTR. The last data read access was done to DATA0 and RPTR was not modified automatically.
Page 136 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization Field Bits Type Description Modification This bit indicates whether the last write access to SBRAM data lead to an automatic increment of WPTR. The last data write access was done to DATA0 and WPTR was not modified automatically.
Page 137 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization 3.11.2.3 SBRAM Data Register 0 This register delivers the read data and is the target for the write data without modification of the respective address pointer. Reset by Power-On Reset.
Page 138 XC2200 Derivatives System Units (Vol. 1 of 2) Memory Organization 3.11.2.4 SBRAM Data Register 1 This register delivers the read data and is the target for the write data with modification of the respective pointer. Reset by Power-On Reset. SBRAM_DATA1...
Page 139: Central Processing Unit (Cpu)
Because a five-stage processing pipeline (plus 2-stage fetch pipeline) is implemented in the XC2200, up to five instructions can be processed in parallel. Most instructions of the XC2200 are executed in one single clock cycle due to this parallelism.
Page 140 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) In contrast to other on-chip peripherals, there is a closer conjunction between the watchdog timer and the CPU. If enabled, the watchdog timer expects to be serviced by the CPU within a programmable period of time, otherwise it will reset the chip.
Page 141 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) All CSFRs may be accessed wordwise, or bytewise (some of them even bitwise). Reading bytes from word CSFRs is a non-critical operation. Any write operation to a single byte of a CSFR clears the non-addressed complementary byte within the specified CSFR.
Page 142: Components Of The Cpu
XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) Components of the CPU The high performance of the CPU results from the cooperation of several units which are optimized for their respective tasks (see Figure 4-1). Prefetch Unit and Branch Unit feed the pipeline minimizing CPU stalls due to instruction reads.
Page 143: Instruction Fetch And Program Flow Control
XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) In general the instructions move through 7 pipeline stages, where each stage processes its individual task (see Section 4.3 for a summary): • the 2-stage fetch pipeline prefetches instructions from program memory and stores them into an instruction FIFO •...
Page 144 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) 24-bit 64-bit Address Data IFU Control IFU Pipeline Instruction Buffer (up to 6 Instr.) Branch Detection and Prediction Logic Prefetch Return Stack Stage Instruction Buffer (up to 3 Instr.)
Page 145: Branch Detection And Branch Prediction Rules
XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) 4.2.1 Branch Detection and Branch Prediction Rules The Branch Detection Unit preprocesses instructions and classifies detected branches. Depending on the branch class, the Branch Prediction Unit predicts the program flow...
Page 146 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) stable (T ) until a whole 64-bit double word can be buffered (T ) in the 96-bit prefetch buffer again. Table 4-2 Correctly Predicted Instruction Flow (Sequential Execution)
Page 147: Incorrectly Predicted Instruction Flow
XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) n+21 n+21 n+20 n+20 a+40 n+19 n+18 n+17 n+16 a+32 n+16 n+15 n+15 n+14 a+24 n+14 n+13 n+12 n+12 a+16 n+11 n+11 n+10 n+10 MCA04918 Figure 4-3 Program Memory Section for Correctly Predicted Flow 4.2.3...
Page 148 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) Table 4-3 Incorrectly Predicted Instruction Flow (Restarted Execution) PMU Address I… I… I… I… I… a+16 a+24 PMU Data 64bit I… – I… I… I… PREFETCH I… –...
Page 149: Instruction Processing Pipeline
The performance of the CPU (pipeline) is decreased by bandwidth limitations (same resource is accessed by different stages) and data dependencies between instructions. The XC2200’s CPU has dedicated hardware to detect and to resolve different kinds of dependencies. Some of those dependencies are described in the following section.
Page 150 Note: The XC2200 has a fully interlocked pipeline, which means that these conflicts do not cause any malfunction. Instruction re-ordering is only required for performance reasons.
Page 151: Pipeline Conflicts Using General Purpose Registers
XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) 4.3.1 Pipeline Conflicts Using General Purpose Registers The GPRs are the working registers of the CPU and there are a lot of possible dependencies between instructions using GPRs. A high-speed five-port register file prevents bandwidth conflicts.
Page 152 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) However, if a GPR is used for indirect addressing the address pointer (i.e. the GPR) will be required already in the DECODE stage. In this case the instruction is stalled in the address stage until the operation in the ALU is executed and the result is forwarded to the address stage.
Page 153: Pipeline Conflicts Using Indirect Addressing Modes
XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) To avoid these stalls, one multicycle instruction or two single cycle instructions may be inserted. These instructions must not update the GPR used for indirect addressing. Conflict_GPRs_Pointer_NoStall: ADD R0,R1 ;Compute new value for R0...
Page 154 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) Conflict_GPRs_Pointer_WrongHistory: ADD R3,[R0] ;R0 points to DPRAM (e.g.) MOV R0,R4 MOV DPPX, ... ;change DPPx ADD R6,[R0] ;R0 now points to SRAM (e.g.) MOV R6,R1 Table 4-7 Pipeline Dependencies with Pointers (Valid Speculation)
Page 155: Pipeline Conflicts Due To Memory Bandwidth
XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) 4.3.3 Pipeline Conflicts Due to Memory Bandwidth Memory bandwidth conflicts can occur if instructions in the pipeline access the same memory area at the same time. Special access mechanisms are implemented to minimize conflicts.
Page 156 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) The CoXXX instructions are the only instructions able to read two memory operands per cycle. A conflict between the two read and one pending write access can occur if all three operands are located in the DPRAM area.
Page 157 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) The DSRAM is a single-port memory with one read/write port. To reduce the number of bandwidth conflict cases, a Write Back Buffer is implemented. It has three data entries.
Page 158: Pipeline Conflicts Caused By Cpu-Sfr Updates
XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) 4.3.4 Pipeline Conflicts Caused by CPU-SFR Updates CPU-SFRs control the CPU functionality and behavior. Changes and updates of CSFRs influence the instruction flow in the pipeline. Therefore, special care is required to ensure that instructions in the pipeline always work with the correct CSFR values.
Page 159 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) Conflict_CSFR_Update_Stall: MUL R0,R1 MOV R6,MDL ADD R6,R1 MOV R3,[R0] Table 4-11 Pipeline Dependencies with Result CSFRs (Stall) Stage DECODE = MUL = MOV = ADD = MOV = MOV...
Page 160 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) By reordering instructions, the bubble in the pipeline can be filled with an instruction not using this resource. Conflict_CSFR_Update_Resolved: MUL R0,R1 MOV R3,[R0] MOV R6,MDL ADD R6,R1 Table 4-12...
Page 161 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) CSFRs Affecting the Whole CPU Some CSFRs affect the whole CPU or the pipeline before the Memory stage. The CPU- SFRs CPUCON1, CP, SP, STKUN, STKOV, VECSEG, TFR, and PSW affect the overall...
Page 162 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) Conflict_Canceling: MOV IDX1,#12 MOV R6,mem ADD R6,R1 MOV R3,[R0] Table 4-13 Pipeline Dependencies with Control CSFRs (Canceling) Stage DECODE = MOV = MOV = MOV = MOV = MOV...
Page 163 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) For all the other instructions that modify this kind of CSFR, a simple stall and cancel mechanism guarantees the correct instruction flow. A possible explicit write-operation to this kind of CSFRs is detected on the MEMORY stage of the pipeline.
Page 164: Cpu Configuration Registers
CPU Configuration Registers The CPU configuration registers select a number of general features and behaviors of the XC2200’s CPU core. In general, these registers must not be modified by application software (exceptions will be documented, e.g. in an errata sheet).
Page 165 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) CPUCON2 CPU Control Register 2 SFR (FE1A Reset Value: 8FBB FIFODEPTH FIFOFED LFIC DAID SL IAEN Field Bits Type Description FIFODEPTH [15:12] rw FIFO Depth Configuration 0000 No FIFO (entries) 0001 One FIFO entry …...
Page 166 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) Field Bits Type Description OVRUN Pipeline Control Overrun of pipeline bubbles not allowed Overrun of pipeline bubbles allowed RETST Enable Return Stack Return Stack is disabled Return Stack is enabled...
Page 167: Use Of General Purpose Registers
XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) Use of General Purpose Registers The CPU uses several banks of sixteen dedicated registers R0, R1, R2, … R15, called General Purpose Registers (GPRs), which can be accessed in one CPU cycle. The GPRs are the working registers of the arithmetic and logic units and many also serve as address pointers for indirect addressing modes.
Page 168 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) Bitfield BANK in register PSW selects which of the three physical register banks is activated. The selected bank can be changed explicitly by any instruction which writes to the PSW, or implicitly by a RETI instruction, an interrupt or hardware trap. In case of an interrupt, the selection of the register bank is configured via registers BNKSELx in the Interrupt Controller ITC.
Page 169: Gpr Addressing Modes
XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) 4.5.1 GPR Addressing Modes Because the GPRs are the working registers and are accessed frequently, there are three possible ways to access a register bank: • Short GPR Address (mnemonic: Rw or Rb) •...
Page 170 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) 24-Bit Memory Addresses can be directly used to access GPRs located in the DPRAM (not applicable for local register banks). In case of a memory read access, a hit detection logic checks if the accessed memory location is cached in the global register bank.
Page 171: Context Switching
XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) 4.5.2 Context Switching When a task scheduler of an operating system activates a new task or an interrupt service routine is called or terminated, the working context (i.e. the registers) of the left task must be saved and the working context of the new task must be restored.
Page 172 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) Switching the Context of the Global Register Bank The contents of the global register bank are switched by changing the base address of the memory-mapped GPR bank. The base address is given by the contents of the Context Pointer (CP).
Page 173 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) Global Bank Global Bank Global Bank Execution Execution Execution Execution Execution Task A Task B Task B Task B Task A Execution of Execution of SCXT CP POP CP...
Page 174 , otherwise the store phase will overwrite SFRs (beginning at FE00 The XC2200 switches the complete memory-mapped GPR bank with a single instruction. After switching, the service routine executes within its own separate context. The instruction “SCXT CP, #New_Bank” pushes the value of the current context pointer (CP) into the system stack and loads CP with the immediate value “New_Bank”, which...
Page 175: Code Addressing
Central Processing Unit (CPU) Code Addressing The XC2200 provides a total addressable memory space of 16 Mbytes. This address space is arranged as 256 segments of 64 Kbytes each. A dedicated 24-bit code address pointer is used to access the memories for instruction fetches. This pointer has two parts: an 8-bit code segment pointer CSP and a 16-bit offset pointer called Instruction Pointer (IP).
Page 176 CSP register. Register IP is not mapped into the XC2200’s address space; thus, it is not directly accessible by the programmer. However, the IP can be modified indirectly via the stack by means of a return instruction.
Page 177: Data Addressing
XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) Data Addressing The Address Data Unit (ADU) contains two independent arithmetic units to generate, calculate, and update addresses for data accesses, the Standard Address Generation Unit (SAGU) and the DSP Address Generation Unit (DAGU). The ADU performs the following major tasks: •...
Page 178 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) Physical Address = Base Address + ∆ × Short Address ∆ ∆ Note: is 1 for byte GPRs, is 2 for word GPRs. Rw, Rb: Specifies direct access to any GPR in the currently active context (global register bank or local register bank).
Page 179: Long Addressing Modes
XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) 4.7.2 Long Addressing Modes Long addressing modes specify 24-bit addresses and, therefore, can access any word or byte data within the entire address space. Long addresses can be specified in different ways to generate the full 24-bit address: •...
Page 180 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) 4.7.2.1 Data Page Pointers DPP0, DPP1, DPP2, DPP3 These four non-bit-addressable registers select up to four different data pages to be active simultaneously at run-time. The lower 10 bits of each DPP register select one of the 1024 possible 16-Kbyte data pages;...
Page 181 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) Note: Due to the internal instruction pipeline, a write operation to the DPPx registers could stall the instruction flow until the DPP is actually updated. The instruction that immediately follows the instruction which updates the DPP register can use the new value of the changed DPPx.
Page 182: Indirect Addressing Modes
XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) 4.7.3 Indirect Addressing Modes Indirect addressing modes can be considered as a combination of short and long addressing modes. This means that the “long” 16-bit pointer is provided indirectly by the contents of a word GPR which itself is specified directly by a short 4-bit address (‘Rw’...
Page 183 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) Table 4-20 Indirect Addressing Modes Mnemonic Particularities [Rw] Most instructions accept any GPR (R15 … R0) as indirect address pointer. Some instructions accept only the lower four GPRs (R3 … R0).
Page 184: Dsp Addressing Modes
XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) 4.7.4 DSP Addressing Modes In addition to the Standard Address Generation Unit (SAGU), the DSP Address Generation Unit (DAGU) provides an additional set of pointer registers (IDX0, IDX1) and offset registers (QX0, QX1).
Page 185 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) There are indirect addressing modes which allow parallel data move operations before the long 16-bit address is calculated (see Figure 4-16 for an example). Other indirect addressing modes allow decrementing or incrementing the indirect address pointers (IDXx contents) by 2 or by the contents of the offset registers QX0 and QX1 (used in conjunction with the IDX pointers).
Page 186 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) 16-Bit IDX Pointer Memory 02'0000 01'0000 DPRAM in Data Page 3 00'0000 MCA04926 Figure 4-15 Arithmetic MAC Operations and Addressing via the IDX Pointers Table 4-21 Generating Physical Addresses from Indirect Pointers (IDXx)
Page 187 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) The following indirect addressing modes are provided: Table 4-22 DSP Addressing Modes Mnemonic Particularities [IDXx] Most CoXXX instructions accept IDXx (IDX0, IDX1) as an indirect address pointer. [IDXx+] The specified indirect address pointer is automatically post-incremented by 2 after the access.
Page 188 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) The CoREG Addressing Mode The CoSTORE instruction utilizes the special CoREG addressing mode for immediate storage of the MAC-Unit register after a MAC operation. The address of the MAC-Unit...
Page 189 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) CoXXXMxx [IDX0+], [R2+] Address Operations 1) Calculate Pointer Addresses IDXx = IDX0 R2 Address = CP + 2 × 2 (Global Register Bank) 2) Intermediate Address of Write Pointer...
Page 190: The System Stack
4.7.5 The System Stack The XC2200 supports a system stack of up to 64 Kbytes. The stack can be located internally in one of the on-chip memories or externally. The 16-bit Stack Pointer register (SP) addresses the stack within a 64-Kbyte segment selected by the Stack Pointer Segment register (SPSG).
Page 191 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) Stack Pointer Register SFR (FE12 Reset Value: FC00 Field Bits Type Description [15:1] Modifiable Portion of Register SP Specifies the top of the system stack. SPSEG Stack Pointer Segment...
Page 192 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) 4.7.5.2 The Stack Overflow/Underflow Pointers STKOV/STKUN These limit registers (not bit-addressable) supervise the stack pointer. A trap is generated when the stack pointer reaches its upper or lower limit. The Stack Pointer Segment Register SPSG is not taken into account for the stack pointer comparison.
Page 193 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) STKOV Stack Overflow Reg. SFR (FE14 Reset Value: FA00 stkov Field Bits Type Description stkov [15:1] Modifiable Portion of Register STKOV Specifies the segment offset address of the lower limit of the system stack.
Page 194: Standard Data Processing
All standard arithmetic, shift-, and logical operations are performed in the 16-bit ALU. In addition to the standard functions, the ALU of the XC2200 includes a bit-manipulation unit and a multiply and divide unit. Most internal execution blocks have been optimized to perform operations on either 8-bit or 16-bit numbers.
Page 195 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) Field Bits Type Description USR1 General Purpose Flag May be used by application USR0 General Purpose Flag May be used by application MULIP Multiplication/Division in Progress Note: Always set to 0 (MUL/DIV not interruptible), for compatibility with existing software.
Page 196 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) Negative numbers are always represented as the 2’s complement of the corresponding positive number. The range of signed numbers extends from -8000 to +7FFF for the word data type, or from -80 to +7F for the byte data type.
Page 197 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) Table 4-24 Shift Right Rounding Error Evaluation C-Flag V-Flag Rounding Error Quantity No rounding error 0 < Rounding error < Rounding error = Rounding error > Z-Flag: The Z-flag is normally set to 1 if the result of an ALU operation equals zero, otherwise it is cleared.
Page 198: 16-Bit Adder/Subtracter, Barrel Shifter, And 16-Bit Logic Unit
4.8.2 Bit Manipulation Unit The XC2200 offers a large number of instructions for bit processing. These instructions either manipulate software flags within the internal RAM, control on-chip peripherals via control bits in their respective SFRs, or control IO functions via port pins.
Page 199 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) This method has several consequences: • The read-modify-write approach may be critical with hardware-affected bits. In these cases, the hardware may change specific bits while the read-modify-write operation is in progress;...
Page 200: Multiply And Divide Unit
4.8.3 Multiply and Divide Unit The XC2200’s multiply and divide unit has two separated parts. One is the fast 16 × 16-bit multiplier that executes a multiplication in one CPU cycle. The other one is a division sub-unit which performs the division algorithm in 18 … 21 CPU cycles (depending on the data and division types).
Page 201 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) Multiply/Divide Low Reg. SFR (FE0E Reset Value: 0000 Field Bits Type Description [15:0] Low Part of MD The low order sixteen bits of the 32-bit multiply and divide register MD.
Page 202: Dsp Data Processing (Mac Unit)
XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) DSP Data Processing (MAC Unit) The new CoXXX arithmetic instructions are performed in the MAC unit. The MAC unit provides single-instruction-cycle, non-pipelined, 32-bit additions; 32-bit subtraction; right and left shifts; 16-bit by 16-bit multiplication; and multiplication with cumulative subtraction/addition.
Page 203: Mac Unit Control
4.9.2 Representation of Numbers and Rounding The XC2200 supports the 2’s complement representation of binary numbers. In this format, the sign bit is the MSB of the binary word. This is set to zero for positive numbers and set to one for negative numbers. Unsigned numbers are supported only by multiply/multiply-accumulate instructions which specify whether each operand is signed or unsigned.
Page 204: The 16-Bit By 16-Bit Signed/Unsigned Multiplier And Scaler
XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) 4.9.3 The 16-bit by 16-bit Signed/Unsigned Multiplier and Scaler The multiplier executes 16-bit by 16-bit parallel signed/unsigned fractional and integer multiplication in one CPU-cycle. The multiplier allows the multiplication of unsigned and signed operands.
Page 205: The Data Limiter
XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) 4.9.7 The Data Limiter Saturation arithmetic is also provided to selectively limit overflow when reading the accumulator by means of a CoSTORE <destination>., MAS instruction. Limiting is performed on the MAC-Unit accumulator. If the contents of the accumulator can be represented in the destination operand size without overflow, then the data limiter is disabled and the operand is not modified.
Page 206: The 40-Bit Signed Accumulator Register
XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) 4.9.9 The 40-bit Signed Accumulator Register The 40-bit accumulator consists of three concatenated registers MAE, MAH, and MAL. MAE is 8 bits wide, MAH and MAL are 16 bits wide. MAE is the Most Significant Byte of the 40-bit accumulator.
Page 207 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) Accumulator High Word SFR (FE5E Reset Value: 0000 Field Bits Type Description [15:0] High Part of Accumulator The 40-bit accumulator is completed by the accumulator low word (MAL) and bitfield MAE User’s Manual...
Page 208: The Mac Unit Status Word Msw
XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) 4.9.10 The MAC Unit Status Word MSW The upper byte of register MSW (bit-addressable) shows the current status of the MAC Unit. The lower byte of register MSW represents the 8-bit MAC accumulator extension, building the 40-bit accumulator together with registers MAH and MAL.
Page 209 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) MAC Unit Status (MV, MN, MZ, MC, MSV, ME, MSL) These condition flags indicate the MAC status resulting from the most recently performed MAC operation. These flags are controlled by the majority of MAC instructions according to specific rules.
Page 210: The Repeat Counter Mrw
XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) MSL-Flag: The MSL-flag is set if an automatic saturation of the accumulator has happened. The automatic saturation is enabled if bit MS in register MCW is set. The MSL-Flag can be also set by instructions which limit the contents of the accumulator.
Page 211 XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) Table 4-26 Encoding of MAC Repeat Word Control Code in ‘rrr’ Effect on Repeat Counter regular CoXXX instruction RESERVED ‘-USR0 CoXXX’ instruction, decrements repeat counter and sets bit USR0 if MRW is zero ‘-USR1 CoXXX’...
Page 212: Constant Registers
XC2200 Derivatives System Units (Vol. 1 of 2) Central Processing Unit (CPU) 4.10 Constant Registers All bits of these bit-addressable registers are fixed to 0 or 1 by hardware. These registers can be read only. Register ZEROS/ONES can be used as a register-addressable constant of all zeros or all ones, for example for bit manipulation or mask generation.
Page 213: Interrupt And Trap Functions
For all types of traps, the current program status is saved on the system stack. External Interrupt Processing Although the XC2200 does not provide dedicated interrupt pins, it allows connection of external interrupt sources and provides several mechanisms to react to external events including standard inputs, non-maskable interrupts, and fast external interrupts. Except for the non-maskable interrupt and the reset input, these interrupt functions are alternate port functions.
Page 214: Interrupt System Structure
The reserved vector locations build a jump table in the low end of a segment (selected by register VECSEG) in the XC2200’s address space. The jump table consists of the appropriate jump instructions which transfer control to the interrupt or trap service routines and which may be located anywhere within the address space.
Page 215 XC2200 Derivatives System Units (Vol. 1 of 2) Interrupt and Trap Functions Interrupt and Peripheral Event Controller PEC Pointer SRCP0 DSTP0 PECSEG0 SRCP1 DSTP1 PECSEG1 Interrupt Request Lines SRCP7 DSTP7 PECSEG7 irq0 irq1 C166S V2 PEC Request irq2 Arbitr. Request...
Page 216: Interrupt Arbitration And Control
System Units (Vol. 1 of 2) Interrupt and Trap Functions Interrupt Arbitration and Control The XC2200’s interrupt arbitration system handles interrupt requests from up to 80 sources. Interrupt requests may be triggered either by the on-chip peripherals or by external inputs.
Page 217 XC2200 Derivatives System Units (Vol. 1 of 2) Interrupt and Trap Functions The interrupt prioritization is done in three stages: • Select one of the active interrupt requests • Compare the priority levels of the selected interrupt request and an eventual OCDS service request •...
Page 218 XC2200 Derivatives System Units (Vol. 1 of 2) Interrupt and Trap Functions Both the OCDS break requests and the hardware traps bypass the arbitration scheme and go directly to the core (see also Figure 5-2). The arbitration process starts with an enabled interrupt request and stays active as long as an interrupt request is pending.
Page 219 XC2200 Derivatives System Units (Vol. 1 of 2) Interrupt and Trap Functions Field Bits Type Description GLVL [1:0] Group Priority Level (Is completed by bit GPX to the 3-bit group level) Highest priority level … … Lowest priority level 1) Bit xxIR supports bit-protection.
Page 220 CPU level, is copied into bitfield ILVL of register PSW after pushing the old PSW contents onto the stack. The interrupt system of the XC2200 allows nesting of up to 15 interrupt service routines of different priority levels (level 0 cannot be arbitrated).
Page 221 This may be required to exclude specific interrupt sources based on the current status of the application. In particular, this is necessary to achieve a deterministic execution of time-critical code sequences. Interrupt requests in the XC2200 can be disabled and enabled on three different levels: • Control all interrupt requests globally •...
Page 222 XC2200 Derivatives System Units (Vol. 1 of 2) Interrupt and Trap Functions Please note that the sequence above blindly controls the global enable flag. If the global setting must not be changed, the code sequence can be enhanced, as shown below:...
Page 223: Interrupt Vector Table
System Units (Vol. 1 of 2) Interrupt and Trap Functions Interrupt Vector Table The XC2200 provides a vectored interrupt system. This system reserves a set of specific memory locations, which are accessed automatically upon the respective trigger event. Entries for the following events are provided: •...
Page 224 XC2200 Derivatives System Units (Vol. 1 of 2) Interrupt and Trap Functions VECSEG Vector Segment Pointer SFR (FF12 Reset Value: Table 5-1 vecseg Field Bits Type Description vecseg [7:0] Segment number of the Vector Table The reset value of register VECSEG, that means the initial location of the vector table, depends on the reset configuration.
Page 225 XC2200 Derivatives System Units (Vol. 1 of 2) Interrupt and Trap Functions Table 5-2 XC2200 Interrupt Nodes Source of Interrupt or PEC Control Vector Trap Service Request Register Location Number CAPCOM Register 16, or CC2_CC16IC xx’0040 / 16 ERU Request 0...
Page 226 XC2200 Derivatives System Units (Vol. 1 of 2) Interrupt and Trap Functions Table 5-2 XC2200 Interrupt Nodes (cont’d) Source of Interrupt or PEC Control Vector Trap Service Request Register Location Number GPT2 Timer 5 GPT12E_T5IC xx’008C / 35 GPT2 Timer 6 GPT12E_T6IC xx’0090...
Page 227 XC2200 Derivatives System Units (Vol. 1 of 2) Interrupt and Trap Functions Table 5-2 XC2200 Interrupt Nodes (cont’d) Source of Interrupt or PEC Control Vector Trap Service Request Register Location Number CAN Request 1 CAN_1IC xx’0104 / 65 CAN Request 2 CAN_2IC xx’0108...
Page 228 XC2200 Derivatives System Units (Vol. 1 of 2) Interrupt and Trap Functions Table 5-2 XC2200 Interrupt Nodes (cont’d) Source of Interrupt or PEC Control Vector Trap Service Request Register Location Number USIC2 Request 3 U2C1_0IC xx’017C / 95 USIC2 Request 4 U2C1_1IC xx’0180...
Page 229 XC2200 Derivatives System Units (Vol. 1 of 2) Interrupt and Trap Functions Table 5-3 lists the vector locations for hardware traps and the corresponding status flags in register TFR. It also lists the priorities of trap service for those cases in which more than one trap condition might be detected within the same instruction.
Page 230 XC2200 Derivatives System Units (Vol. 1 of 2) Interrupt and Trap Functions Interrupt Jump Table Cache Servicing an interrupt request via the vector table usually incurs two subsequent branches: an implicit branch to the vector location and an explicit branch to the actual service routine.
Page 231 XC2200 Derivatives System Units (Vol. 1 of 2) Interrupt and Trap Functions Field Bits Type Description Fast Interrupt Enable The interrupt jump table cache is not used The interrupt jump table cache is enabled, the vector table entry for the specified request...
Page 232: Operation Of The Peripheral Event Controller Channels
Interrupt and Trap Functions Operation of the Peripheral Event Controller Channels The XC2200’s Peripheral Event Controller (PEC) provides 8 PEC service channels which move a single byte or word between any two locations. A PEC transfer can be triggered by an interrupt service request and is the fastest possible interrupt response.
Page 233 XC2200 Derivatives System Units (Vol. 1 of 2) Interrupt and Trap Functions PECCx (x=0-7) PEC Channel Control Reg. x SFR(FEC0 +2*x) Reset Value: 0000 PLEV COUNT Field Bits Type Description EOPINT End of PEC Interrupt Selection End of PEC interrupt on the same (PEC) level...
Page 234 XC2200 Derivatives System Units (Vol. 1 of 2) Interrupt and Trap Functions The PEC channel number is derived from the respective ILVL (LSB) and GLVL, where the priority band (ILVL) is selected by the channel’s bitfield PLEV (see Table 5-5). So,...
Page 235 XC2200 Derivatives System Units (Vol. 1 of 2) Interrupt and Trap Functions Table 5-6 Interrupt Priority Examples Priority Level Type of Service COUNT ≠ 00 COUNT ≠ 00 Interr. Group COUNT = 00 Level Level PLEV = XX PLEV = 00...
Page 236: The Pec Source And Destination Pointers
XC2200 Derivatives System Units (Vol. 1 of 2) Interrupt and Trap Functions 5.4.2 The PEC Source and Destination Pointers The PEC channels’ source and destination pointers specify the locations between which the data is to be moved. Both 24-bit pointers are built by concatenating the 16-bit offset register (SRCPx or DSTPx) with the respective 8-bit segment bitfield (SRCSEGx or DSTSEGx, combined in register PECSEGx).
Page 237 XC2200 Derivatives System Units (Vol. 1 of 2) Interrupt and Trap Functions SRCPx (x=0-7) PEC Source Pointer x XSFR(EC40 +4*x) Reset Value: 0000 SRCPx Field Bits Type Description SRCPx [15:0] Source Pointer Offset of Channel x Source address bits 15 … 0...
Page 238: Pec Transfer Control
XC2200 Derivatives System Units (Vol. 1 of 2) Interrupt and Trap Functions Table 5-7 PEC Data Pointer Register Addresses Channel # PECSEGx EC80 EC82 EC84 EC86 EC88 EC8A EC8C EC8E SRCPx EC40 EC44 EC48 EC4C EC50 EC54 EC58 EC5C DSTPx...
Page 239 XC2200 Derivatives System Units (Vol. 1 of 2) Interrupt and Trap Functions The PEC transfer counter allows service of a specified number of requests by the respective PEC channel, and then (when COUNT reaches 00 ) activation of an interrupt service routine, either associated with the PEC channel’s priority level or with the general...
Page 240: Channel Link Mode For Data Chaining
XC2200 Derivatives System Units (Vol. 1 of 2) Interrupt and Trap Functions 5.4.4 Channel Link Mode for Data Chaining In channel link mode, every two PEC channels build a pair (channels 0+1, 2+3, 4+5, 6+7), where the two channels of a pair are activated in turn. Requests for the even channel trigger the currently active PEC channel (or the end-of-block interrupt), while requests for the odd channel only trigger its associated interrupt node.
Page 241: Pec Interrupt Control
XC2200 Derivatives System Units (Vol. 1 of 2) Interrupt and Trap Functions 5.4.5 PEC Interrupt Control When the selected number of PEC transfers has been executed, the respective PEC channel is disabled and a standard interrupt service routine is activated instead. Each...
Page 242 XC2200 Derivatives System Units (Vol. 1 of 2) Interrupt and Trap Functions PECISNC C7IR C7IE C6IR C6IE C5IR C5IE C4IR C4IE C3IR C3IE C2IR C2IE C1IR C1IE C0IR C0IE Interrupt Request Pulse Generator EOPIC ILVL GLVL MCD04914 Figure 5-4 End of PEC Interrupt Sub Node Note: The interrupt service routine must service and clear all currently active requests before terminating.
Page 243: Prioritization Of Interrupt And Pec Service Requests
An interrupt class covers a set of interrupt sources with the same importance, i.e. the same priority from the system’s viewpoint. Interrupts of the same class must not interrupt each other. The XC2200 supports this function with two features: •...
Page 244 XC2200 Derivatives System Units (Vol. 1 of 2) Interrupt and Trap Functions The example shown below establishes 3 interrupt classes which cover 2 or 3 interrupt priorities, depending on the number of members in a class. A level 6 interrupt disables all other sources in class 2 by changing the current CPU level to 8, which is the highest priority (ILVL) in class 2.
Page 245: Context Switching And Saving Status
XC2200 Derivatives System Units (Vol. 1 of 2) Interrupt and Trap Functions Context Switching and Saving Status Before an interrupt request that has been arbitrated is actually serviced, the status of the current task is automatically saved on the system stack. The CPU status (PSW) is saved together with the location at which execution of the interrupted task is to be resumed after returning from the service routine.
Page 246 The more registers a routine uses, the more time is spent saving and restoring. The XC2200 allows switching the complete bank of CPU registers (GPRs) either automatically or with a single instruction, so the service routine executes...
Page 247 XC2200 Derivatives System Units (Vol. 1 of 2) Interrupt and Trap Functions BNKSEL0 Register Bank Selection Reg. 0 XSFR(EC20 Reset Value: 0000 BNKSEL1 Register Bank Selection Reg. 1 XSFR(EC22 Reset Value: 0000 BNKSEL2 Register Bank Selection Reg. 2 XSFR(EC24 Reset Value: 0000 BNKSEL3 Register Bank Selection Reg.
Page 248: Interrupt Node Sharing
XC2200 Derivatives System Units (Vol. 1 of 2) Interrupt and Trap Functions Interrupt Node Sharing Interrupt nodes may be shared among several module requests if either the requests are generated mutually exclusively or the requests are generated at a low rate. If more than one source is enabled in this case, the interrupt handler will first need to determine the requesting source.
Page 249: External Interrupts
Interrupt and Trap Functions External Interrupts Although the XC2200 has no dedicated INTR input pins, it supports many possibilities to react to external asynchronous events. It does this by using a number of IO lines for interrupt input. The interrupt function may be either combined with the pin’s main function or used instead of it if the main pin function is not required.
Page 250 XC2200 Derivatives System Units (Vol. 1 of 2) Interrupt and Trap Functions Pins T2IN or T4IN can be used as external interrupt input pins when the associated auxiliary timer T2 or T4 in block GPT1 is configured for capture mode. This mode is...
Page 251: Ocds Requests
XC2200 Derivatives System Units (Vol. 1 of 2) Interrupt and Trap Functions OCDS Requests The OCDS module issues high-priority break requests or standard service requests. The break requests are routed directly to the CPU (like the hardware trap requests) and are prioritized there.
Page 252: Service Request Latency
5.10 Service Request Latency The numerous service requests of the XC2200 (requests for interrupt or PEC service) are generated asynchronously with respect to the execution of the instruction flow. Therefore, these requests are arbitrated and are inserted into the current instruction stream.
Page 253 Memory access for vector table read - - - (except for intr. jump table cache) 1) This is the longest possible access time within the XC2200 system. 2) Depending on segmentation off/on. The actual response to an interrupt request may be delayed further depending on programming techniques used by the application.
Page 254: Trap Functions
Trap functions are not maskable and always have priority over interrupt requests on any priority level. The XC2200 provides two different kinds of trapping mechanisms: Hardware Traps are triggered by events that occur during program execution (such as illegal access or undefined opcode);...
Page 255 The global register bank is selected. Execution branches to the respective trap vector in the vector table. A trap service routine must be terminated with the RETI instruction. The nine hardware trap functions of the XC2200 are divided into two classes: Class A traps are: •...
Page 256 XC2200 Derivatives System Units (Vol. 1 of 2) Interrupt and Trap Functions Trap Flag Register SFR (FFAC Reset Value: 0000 Field Bits Type Description System Request 0 Flag No trigger detected The selected condition has been detected STKOF Stack Overflow Flag...
Page 257 XC2200 Derivatives System Units (Vol. 1 of 2) Interrupt and Trap Functions Field Bits Type Description ILLOPA Illegal Word Operand Access No illegal word operand access event detected A word operand access (read or write) to an odd address has been attempted...
Page 258 XC2200 Derivatives System Units (Vol. 1 of 2) Interrupt and Trap Functions Class B Traps Class B traps are generated by unrecoverable hardware failures. In the case of a hardware failure, the CPU must immediately start a failure service routine. Class B traps can interrupt an atomic/extend sequence and an I/O read access.
Page 259 SR1 trap routine. Undefined Opcode Trap (B) When the instruction currently decoded by the CPU does not contain a valid XC2200 opcode, the UNDOPC flag is set in register TFR and the CPU enters the undefined opcode trap routine. The instruction that causes the undefined opcode trap is executed as a NOP.
Page 260 XC2200 Derivatives System Units (Vol. 1 of 2) Interrupt and Trap Functions Memory Access Error (B) When a memory access error is detected, the ACER flag is set in register TFR and the CPU enters the access error trap routine. The access error is reported in the following cases: •...
Page 261: System Control Unit (Scu)
System Control Unit (SCU) System Control Unit (SCU) The System Control Unit (SCU) of the XC2200 handles all system control tasks besides the debug related tasks which are controlled by the OCDS/Cerberus. All functions described in this chapter are tightly coupled, thus, they are conveniently handled by one unit, the SCU.
Page 262: Clock Generation Unit
System Control Unit (SCU) Clock Generation Unit The Clock Generation Unit (CGU) allows a very flexible clock generation for the XC2200. During user program execution the frequency can be programmed for an optimal ratio between performance and power consumption in the actual application state.
Page 263 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Register Overview The CGU is controlled by a number of registers shown in the following figure. Oscillator Control PLL Control System Control Output Control WUOSCCON PLLSTAT SYSCON0 RTCCLKCON...
Page 264: Trimmed Current Controlled Wake-Up Clock (Osc_Wu)
Voltages on XTAL1 must comply to the voltage defined in the data sheet. XTAL1 External Clock Signal OSC_HP XTAL2 leave unconnected CGU_OSC _HP_ExtIn.vsd Figure 6-3 XC2200 External Clock Input Mode for the High-Precision Oscillator User’s Manual V2.1, 2008-08 SCU, V1.13...
Page 265: Phase-Locked Loop (Pll) Module
XTAL1 OSC_HP XTAL2 CGU_OSC _HP_Crystal.vsd Figure 6-4 XC2200 External Crystal Mode Circuitry for the High-Precision Oscillator 6.1.4 Phase-Locked Loop (PLL) Module The PLL can convert a low-frequency external clock signal to a high-speed system clock for maximum performance. The PLL also has fail-safe logic that detects degenerate external clock behavior such as abnormal frequency deviations or a total loss of the external clock.
Page 266 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) – Unlocked Mode – Normal Mode • Different power saving modes – Power Down – Sleep Mode (VCO Power Down) • Glitchless programming of output divider K2 and VCO bypass divider K1 •...
Page 267 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) PLL Modes The PLL clock is generated from in one of the following software selectable modes: • Normal Mode • Prescaler Mode • Unlocked Mode In Normal Mode the reference frequency is divided by a factor P, multiplied by a factor N and then divided by a factor K2.
Page 268 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Configuration and Operation of the Unlocked Mode In Unlocked Mode, the PLL is running at its VCO base frequency and is derived from by the K2-Divider. PLLSTAT .
Page 269 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) PLLCON 1. PLLSTAT . PLLCON0. OSCSEL FINDIS VCOBY Divider Core Divider Clock Lock Source Detect. Divider Osc. PLL Block HPOSCCON. HPOSCCON. PLLCON1. PLLSTAT . OSCWDTRST PLLV RESLD VCOLOCK PLL _Normal_Mode.vsd...
Page 270 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) While the Prescaler Mode is used the Normal Mode can be configured and checked for a positive VCO Lock status. The first target frequency of the Normal Mode should be selected in a way that it matches or is only slightly higher as the one used in the Prescaler Mode.
Page 271 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) sporadic clock pulses coming from the oscillator circuit. Without a clock input , the PLL gradually slows down to its VCO base frequency and remains there. The automatic...
Page 272 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Note: Changing the system operation frequency by changing the value of the K1-Divider has a direct influence on the power consumption of the device. Therefore, this has to be done carefully.
Page 273 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Note: The oscillator watchdog requires the trimmed currenct controlled clock as a reference. Therefore, it can only be used (HPOSCCON.PLLV is valid) while the clock source is active.
Page 274 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.1.4.6 Switching PLL Parameters The following restriction applies when changing PLL parameters inside the PLLCON0 to PLLCON3 registers: • The VCO bypass switch may be used at any time, however, it has to be ensured that the maximum operating frequency of the device (see data sheet) will not be exceeded.
Page 275: Clock Control Unit
System Units (Vol. 1 of 2) System Control Unit (SCU) 6.1.5 Clock Control Unit The Clock Control Unit (CCU) selects the current clock sources for the clock signals used in the XC2200. It generates the following clocks: • System clock • RTC count clock •...
Page 276 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) OSCWDT VCOLCK Emergency Emergency Event Event SYSCON 0. CLKSEL System SYSCON 0.EMCLKSELEN Master Clock PLLCON 1.EMCLKEN Clock Multiplexer Selection HPOSCCON.EMCLKEN (MCM) CLKIN1 Emergency to EXTCLK selection Clock SYSCON 0.
Page 277 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) RTC Clock Generation For the RTC module it is possible to select the operation in synchronous or asynchronous mode in the module itself. The asynchronous clock for the RTC can be selected out of following clock sources in the CCU: •...
Page 278 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.1.5.2 Selecting and Changing the Operating Frequency When selecting the clock source and the clock generation method, the required parameters must be carefully written to the respective bit fields, to avoid unintended intermediate states.
Page 279 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) • Bit PLLSTAT.VCOLOCK = 0, while the PLL is not locked • Bit SYSCON0.EMSVCO is set, if SYSCON0.EMCLKSELEN is set • The PLL VCO clock input is disconnected (PLLSTAT.FINDIS = 1) and the PLL clock slows down to its VCO base frequency.
Page 280: External Clock Output
This clock can be controlled via software, and so can be adapted to the requirements of the connected external circuitry. The programmability also extends the power management to a system level, as also circuitry (peripherals, etc.) outside the XC2200 can be run at a scalable frequency or can temporarily be left without a clock.
Page 281 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) EXTCON.FORV EXTCON. Ctrl. Reload FOEN Counter FOTL EXTCON.FOSS EXTCON.FOTL Reload Counter CCU_EXTCLK_Counter.vsd Figure 6-12 Programmable Frequency Output Generation always provides complete output periods (provided is available): • When is started (EXTCON.FOEN is set) counter FOCNT is loaded from...
Page 282 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) OU T (FORV = 0) OU T (FORV = 2) OU T (FORV = 5) FOEN FOEN 1) FOSS = 1, Output of Counter 2) FOSS = 0, Output of Toggle Latch...
Page 283: Cgu Registers
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.1.7 CGU Registers 6.1.7.1 Wake-up Clock Register This register controls the settings of OSC_WU. WUOSCCON Wake-up OSC Control Register ESFR (F1AE Reset Value: 0000 FREQSEL Field Bits Type...
Page 284 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.1.7.2 High Precision Oscillator Register This register controls the setting of OSC_HP. HPOSCCON High Precision OSC Control Register ESFR (F1B4 Reset Value: 053C X1D GAINSEL MODE Field Bits...
Page 285 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description GAINSEL [5:4] Oscillator Gain Selection Reserved Reserved Reserved The gain control is configured for frequencies from 4 MHz to 25 MHz Note: Used for testing only.
Page 286 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description OSC2L1 OSC_HP Not Usable Frequency Event This sticky bit indicates if bit PLLV has been cleared since OSC2L1 has last been cleared (by writing 1 to bit STATCLR1.OSC2L1CLR).
Page 287 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.1.7.3 PLL Control Register This register controls the trimmed current controlled clock source. PLLOSCCON PLL OSC Control Register ESFR (F1B6 Reset Value: 0000 OSCTRIM Field Bits Type Description...
Page 288 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.1.7.4 PLL Registers These registers control the settings of the PLL. PLLSTAT PLL Status Register ESFR (F0BC Reset Value: 0000 Field Bits Type Description VCOBYST VCO Bypass Status...
Page 289 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description PRDY P-Divider Ready Status Bit field PLLCON1.PDIV has been changed, new K1 divider value not yet used. The P-Divider operates with the value defined in bit field PLLCON1.PDIV.
Page 290 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description VCOL1 VCO Lock Detection Reached Status This sticky bit indicates if bit VCOLOCK has been set since VCOL1 has last been cleared (by writing 1 to bit STATCLR1.VCOL1CLR).
Page 291 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) STATCLR1 PLL Status Clear 1 Register ESFR (F0E2 Reset Value: 0000 Field Bits Type Description VCOL0CLR VCOL0 Clear Trigger No action Bit PLLSTAT.VCOL0 is cleared VCOL1CLR VCOL1 Clear Trigger No action Bit PLLSTAT.VCOL1 is cleared...
Page 292 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) PLLCON0 PLL Configuration 0 Register ESFR (F1B8 Reset Value: 1302 NDIV VCOSEL Field Bits Type Description VCOBY VCO Bypass Select divider K2 for PLL clock (Normal / Unlocked Mode) Select divider K1 for PLL clock (Prescaler Mode, i.e.
Page 293 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description NDIV [13:8] N-Divider Value The value the N-Divider operates is NDIV+1. Only values between N = 8 and N = 28 are allowed for VCOSEL = 00...
Page 294 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) PLLCON1 PLL Configuration 1 Register ESFR (F1BA Reset Value: 000A PDIV Field Bits Type Description PLLPWD PLL Power Saving Mode Normal behavior Complete PLL block is put into a power saving...
Page 295 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description EMFINDISEN Emergency Input Clock Disconnect Enable This bit defines if bit PLLSTAT.FINDIS is set in a VCOLCK emergency case. No action PLLSTAT.FINDIS is set in a VCOLCK emergency case Note: Please refer to the Programmer’s Guide for a...
Page 296 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) PLLCON2 PLL Configuration 2 Register ESFR (F1BC Reset Value: 0001 K1DIV Field Bits Type Description K1DIV [9:0] K1-Divider Value The value the K1-Divider operates is K1DIV+1. K1ACK K1-Divider Ready Acknowledge Setting this bit provides the acknowledge to K1RDY.
Page 297 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) PLLCON3 PLL Configuration 3 Register ESFR (F1BE Reset Value: 00CB K2DIV Field Bits Type Description K2DIV [9:0] K2-Divider Value The value the K2-Divider operates is K2DIV+1. K2ACK K2-Divider Ready Acknowledge Setting this bit provides the acknowledge to K2RDY.
Page 298 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.1.7.5 System Clock Control Registers These registers control the system level clock behavior. SYSCON0 System Control 0 Register SFR (FF4A Reset Value: 0000 CLKSEL CLKSEL Field Bits Type...
Page 299 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description EMSVCO VCOLCK Emergency Event Source Status No VCOLCK emergency event occurred since EMSVCO has been cleared last A VCOLCK emergency event has occurred Note: This bit is only set if EMCLKSELEN is set.
Page 300 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) STATCLR0 Status Clear 0 Register ESFR (F0E0 Reset Value: 0000 Field Bits Type Description EMCOSC EMSOSC Clear Trigger No action Bit SYSCON0.EMSOSC is cleared EMCVCO EMSVCO Clear Trigger No action Bit SYSCON0.EMSVCO is cleared...
Page 301 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.1.7.6 RTC Clock Control Register Note: Only change register RTCCLKCON while the RTC is off. RTCCLKCON RTC Clock Control Register SFR (FF4E Reset Value: 0006 CLKSEL Field Bits...
Page 302 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.1.7.7 External Clock Control Register This register control the setting of external clock for pin 2.8 and 7.1. EXTCON External Clock Control Register SFR (FF5E Reset Value: 0000...
Page 303 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description FOEN Frequency Output Enable Frequency output generation stops when is/becomes low. FOCNT is running, is gated to pin. First reload after 0 - 1 transition.
Page 304: Wake-Up Timer (Wut)
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Wake-up Timer (WUT) The Wake-up Timer provides a very compact (and, therefore, power-saving) mean of re- activating the system from certain power saving modes automatically after a specific period of time.
Page 305 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) The wake-up interval counter (WIC) is clocked with /64, and counts down until it reaches zero. It then generates a wake-up trigger and sets bit WUCR.WUTRG. The timer is stopped in the following ways: •...
Page 306: Wut Registers
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.2.2 WUT Registers 6.2.2.1 Register WICR Via this register the status and configuration of the WIC counter is done. WICR Wake-up Interval Count Register ESFR (F0B0 Reset Value: FFFF...
Page 307 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.2.2.2 Register WUCR This register the status and control bits for the WUT. WUCR Wake-up Control Register ESFR (F1B0 Reset Value: 0000 ASP AON RUN Field Bits Type...
Page 308 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description Auto-Start Indicator Wake-up counter is started by software only Wake-up counter can be started by the PSC mechanism Auto-Stop Indicator Wake-up counter runs continuously...
Page 309: Reset Operation
6.3.1 Reset Architecture The XC2200 contains a very sophisticated reset architecture to offer the greatest amount of flexibility for the support of different applications. The reset architecture supports the different power domains.
Page 310 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Functional / User Reset • Debug Reset This reset leads to a defined state of the complete debug system. • Internal Application Reset This reset leads to a defined state of the complete application system with the following parts: all peripherals (except the RTC), the CPU and partially the SCU and the flash memory.
Page 311: General Reset Operation
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Table 6-1 Identification of a reset Type of Reset Identification (in hierarchical order, highest on top) Internal Application Reset RSTSTAT1.ST1 = 00 RSTSTATx.y = 10 Application Reset RSTSTAT1.ST1 = 00 RSTSTATx.y = 11...
Page 312 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Table 6-2 Restart of RSTCNTA Reset Active New Reset Trigger Power-On Debug Reset Internal Application Application Reset Reset Internal Application Restart with No Change No Change No Change...
Page 313: Debug Reset Assertion
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Example2 Reset request trigger A is asserted and leads to an Application Reset. Reset request trigger A is de-asserted before RSTCNTA reached zero. Reset request trigger B is asserted after reset request trigger A but before RSTCNTA reaches zero.
Page 314: Reset Request Trigger Sources
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.3.5 Reset Request Trigger Sources The following overview summarizes the different reset request trigger sources within the system. Power-On Reset Pin PORST A Power-on Reset is requests asynchronously, by driving the PORST pin low.
Page 315 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) If pin ESRx is enabled as reset output and the input level is low while the output stage is disabled (indicating that it is still driven low externally), the reset circuitry holds the chip in reset until a high level is detected on ESRx.
Page 316: Module Reset Behavior
Module Reset Behavior Table 6-5 lists how the various functions of the XC2200 are affected through a reset depending on the reset type. A “X” means that this block has at least some register/bits that are affected by this reset type.
Page 317 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Table 6-5 Effect of Reset on Device Functions Module / Function Application Internal Debug Reset Reset Application Reset CPU Core Peripherals (except SCU and RTC) Not affected Not affected...
Page 318: Reset Controller Registers
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.3.7 Reset Controller Registers 6.3.7.1 Status Registers After a reset has been executed, the Reset Status registers provide information on the type of the last reset. Note: After a Power Reset for domain DMP_1 register RSTSTAT0 is not cleared.
Page 319 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) RSTSTAT1 Reset Status 1 Register ESFR (F0B4 Reset Value: F000 ESR2 ESR1 ESR0 Field Bits Type Description ESR0 [1:0] ESR0 Reset Status The ESR0 reset trigger was not relevant for the...
Page 320 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description [7:6] WDT Reset Status The WDT reset trigger was not relevant for the last reset Reserved The WDT reset trigger was relevant for the last reset.
Page 321 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) RSTSTAT2 Reset Status 2 Register ESFR (F0B6 Reset Value: 0000 OJCONF3 OJCONF2 OJCONF1 Field Bits Type Description [1:0] Debug Reset Status The DB reset trigger was not relevant for the...
Page 322 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description OJCONF3 [9:8] OJCONF3 Reset Status The OJCONF3 reset trigger was not relevant for the last reset The OJCONF3 reset trigger was not relevant for the last reset...
Page 323 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.3.7.2 Configuration Registers These registers allow the behavioral configuration for the various reset trigger sources. RSTCON0 Reset Configuration 0 Register ESFR (F0B8 Reset Value: 0000 Field Bits Type...
Page 324 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) RSTCON1 Reset Configuration 1 Register ESFR (F0BA Reset Value: 0002 ESR2 ESR1 ESR0 Field Bits Type Description ESR0 [1:0] ESR0 Reset Type Selection This bit field defines which reset types are generated by a ESR0 reset request trigger.
Page 325 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description [7:6] WDT Reset Type Selection This bit field defines which reset types are generated by a WDT reset request trigger. No reset is generated...
Page 326 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) RSTCNTCON Reset Counter Control RegisterESFR (F1B2 Reset Value: 0A0A RELD RELA Field Bits Type Description RELA [7:0] Application Reset Counter Reload Value This bit field defines the reload value of RSTCNTA.
Page 327 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Software Reset Control Register This register controls the software reset operation. SWRSTCON Software Reset Control RegisterESFR (F0AE Reset Value: 0000 SWCFG Field Bits Type Description SWBOOT Software Boot Configuration Selection Bit field STSTAT.HWCFG is not updated with...
Page 328: External Service Request (Esr) Pins
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) External Service Request (ESR) Pins The ESR pins serve as multi-functional pins for an amount of different options: • Act as reset trigger input • Act as reset output •...
Page 329 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) ESRCFGx. AEDCON OSC_WU Edge Detection DMPMIT. Trap ESRxT Edge Detection ESRCFGx. SEDCON ESRx Input Digital Selection Filter to System ESRCFGx. DFEN Reset ESRx Control Control ESRx ESR _control .vsd Figure 6-15 ESRx Control Furthermore, an overlay with other product functions (i.e.
Page 330 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) ESREXCONx Input 0 Input 1 Input 2 Input 3 & ESRx Control Input 4 Input 5 ESRx ESRx_selection_MR. vsd Figure 6-16 ESRx Input Selection Up to three ESR pins (ESR0/ESR1/ESR2) are available. The availability of pins ESR1 and ESR2 is device and package dependent and is described in the data sheet.
Page 331 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.4.1.1 ESR as Reset Input The pins ESRx can serve as an external reset input as well as a reset output (open drain) for Internal Application and Application Resets. Additionally several GPIO pad triggers that can be enabled additionally via register ESREXCONx interfere with the ESR pin function.
Page 332 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.4.1.5 ESR as Trigger Input for the GSC The ESR can be used to request a change in the Control Mode. For more information Chapter 6.6. 6.4.1.6 Overlay with other Product Functions Additionally other port inputs (e.g.
Page 333 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Table 6-8 Additional ESR2 Functions Function Module Function is Implemented Trap Generation Trap Generation PSC Wake-up Request Power State Machine (PSC and CGU) OSC_WU enable Peripheral Normal Mode Request Global Mode Control (GSC)
Page 334 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.4.1.7 Pad Configuration for ESR Pads The configuration is selected via bit field ESRCFGx.PC. The pad functionality control can be configured independently for each pin, comprising: • A selection of the driver type (open-drain or push-pull) •...
Page 335: Esr Control Registers
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.4.2 ESR Control Registers 6.4.2.1 Configuration Registers ESR External Control Register The ESR External Control registers contain enable/disable bits for the different inputs that can lead to an ESR action. For ESR0 this option is not available.
Page 336 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description P10EN Port 1.0 Pin Enable This bit enables/disables the Port 1.0 pin for the activation of all ESR1 related actions. The input from port pin P1.0 is disabled The input from port pin P1.0 is enabled...
Page 337 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) ESREXCON2 ESR2 External Control Register SFR (FF34 Reset Value: 0001 1014 Field Bits Type Description ESR2EN ESR2 Pin Enable This bit enables/disables the ESR2 pin for the activation of all ESR2 related actions.
Page 338 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description P13EN Port 1.3 Pin Enable This bit enables/disables the Port 1.3 pin for the activation of all ESR2 related actions. The input from port pin P1.3 is disabled The input from port pin P1.3 is enabled...
Page 339 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) ESR Configuration Register The ESR configuration registers contains bits required for the behavioral control of the ESR pins. ESRCFG0 ESR0 Configuration Register ESFR (F100 Reset Value: 000E ESRCFG1...
Page 340 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description SEDCON [8:7] Synchronous Edge Detection Control This bit field defines the edges that lead to an ESRx trigger of the synchronous path. No trigger is generated...
Page 341: Esr Data Register
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.4.3 ESR Data Register 6.4.3.1 ESRDAT The ESR data register contains bits required if ESRx are used as data ports. ESRDAT ESR Data Register ESFR (F106 Reset Value: 0000...
Page 342: Power Supply And Control
System Control Unit (SCU) Power Supply and Control The XC2200 can run from a single external power supply. The core supply voltages can be fed in from an external Voltage Regulator (VR) or can be generated by on-chip Embedded Voltage Regulators (EVRs).
Page 343 6.5.2). By controlling the regulator, a core power domain can be switched off to save the leakage current within this area (see Chapter 6.5.3). Table 6-10 XC2200 Power Domains Supply and Control Power Domain Supply Supply Voltage Supply Source Checked by : 3.0 …...
Page 344: Supply Watchdog (Swd)
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.5.1 Supply Watchdog (SWD) The supply voltage of the pad I/O domain for systems and communication I/Os (DMP_B) is monitored to validate the overall power supply. The external supply voltage is monitored for following purposes: •...
Page 345 , bit SWDCON1.PON is set. Note: The physical value for V can found in the XC2200 data sheet. The SWD provides two adjustable threshold levels (LEV1 and LEV2) that can be individually programmed, via SWDCON0.LEV1V and SWDCON0.LEV2V, and deliver a compare value each.
Page 346 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) action and which action is triggered by each threshold can be configured via bit field SWDCON0.LxACON and bit fieldSWDCON0.LxALEV (x = 1,2). The SWD control (programming of the threshold levels) is done by software only.
Page 347 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.5.1.1 SWD Control Registers The following registers are the software interface for the SWD. SWDCON0 SWD Control 0 Register ESFR (F080 Reset Value: 0941 L2ACON LEV2V L1ACON LEV1V...
Page 348 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description LEV2V [11:8] Level Threshold 2 Voltage This bit field defines the voltage level that is used as check level threshold 2. The values of the level thresholds are listed in the data sheet.
Page 349 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) SWDCON1 SWD Control 1 Register ESFR (F082 Reset Value: 0000 Field Bits Type Description POWENCLR SWD Power Saving Mode Enable Clear No action Bit POWEN is cleared POWENSET...
Page 350: Monitoring The Voltage Level Of A Core Domain
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.5.2 Monitoring the Voltage Level of a Core Domain A Power Validation Circuit (PVC) monitors the internal core supply voltage of a core domain. It can be configured to monitor two programmable independent voltage levels.
Page 351 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.5.2.1 PVC Status and Control Registers These registers are the software interface for PVC_1 and PVC_M. The registers are updated by the PSC. PVC1CON0 PVC_1 Control Step 0 Register...
Page 352 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description L1INTEN Level Threshold 1 Interrupt Request Enable This bit defines if an interrupt request trigger is requested if the comparison check was successful. When a check is successful is defined via bit L1ALEV.
Page 353 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description L2INTEN Level Threshold 2 Interrupt Request Enable This bit defines if an interrupt request trigger is requested if the comparison check was successful. When a check is successful is defined via bit L2ALEV.
Page 354 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) PVCMCON0 PVC_M Control Step 0 Register MEM (F1E4 /--) Reset Value: 0544 LEV2V LEV1V Field Bits Type Description LEV1V [2:0] Level Threshold 1 Voltage This bit field defines the Level Threshold 1 that is compared with the DMP_M core supply voltage.
Page 355 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description L1RSTEN Level Threshold 1 Reset Request Enable This bit defines if a reset request trigger is requested if the comparison check was successful. When a check is successful is defined via bit L1ALEV.
Page 356 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description L2RSTEN Level Threshold 2 Reset Request Enable This bit defines if a reset request trigger is requested if the comparison check was successful. When a check is successful is defined via bit L2ALEV.
Page 357: Controlling The Voltage Level Of A Core Domain
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.5.3 Controlling the Voltage Level of a Core Domain The two core power domains DMP_M and DMP_1 can be controlled individually within certain limits. The limits are defined by the supported Power States.
Page 358 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.5.3.2 Embedded Voltage Regulator The main part of the device logic operates at a typical voltage level of 1.5 V. This supply voltage is generated by the Embedded Power Regulators (EVRs) out of the pad voltage.
Page 359 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Lower Power Reference (LPR) The LPR of an EVR is used for following purposes: • Operation in a power-save mode other than Active Mode • Special power saving in the Active Mode The LPR can be enabled / disabled via the bit EVRxSETyyV.LPRDIS.
Page 360 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) EVR Status and Control Registers EVR1CON0 EVR_1 Control 0 Register ESFR (F088 Reset Value: DF20 CCLEV LPRLEV Field Bits Type Description LPRLEV [5:3] Low Power Reference Level This bit field adjusts the core voltage generated by the EVR for low power reference settings.
Page 361 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) EVR1SET10V EVR_1 Setting for 1.0 V Register ESFR (F098 Reset Value: 005B EVR1SET15VLP EVR_1 Setting for 1.5 V LP Register ESFR (F09C Reset Value: 00DB EVR1SET15VHP EVR_1 Setting for 1.5 V HP Register...
Page 362 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description CCDIS Current Control Disable The current control is enabled The current control is disabled This bit updates bit EVR1CON0.CCDIS. Note: Before switching off the current control the...
Page 363 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) EVRMCON0 EVR_M Control 0 Register ESFR (F084 Reset Value: 0D20 CCLEV LPRLEV Field Bits Type Description LPRLEV [5:3] Low Power Reference Level This bit field adjusts the core voltage generated by the EVR for low power reference settings.
Page 364 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) EVRMCON1 EVR_M Control 1 Register ESFR (F086 Reset Value: 0101 HPADJUST Field Bits Type Description HPADJUST [7:0] HP Bandgap Adjustment This bit field is a device specific trimmvalue for the HP bandgap.
Page 365 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) EVRMSET10V EVR_M Setting for 1.0 V Register ESFR (F090 Reset Value: 005B EVRMSET15VLP EVR_M Setting for 1.5 V LP Register ESFR (F094 Reset Value: 00DB EVRMSET15VHP EVR_M Setting for 1.5 V HP Register...
Page 366 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description CCDIS Current Control Disable The current control is enabled The current control is disabled This bit updates bit EVRMCON0.CCDIS. Note: Before switching off the current control the...
Page 367 6.5.3.3 Sources for Core Supply Voltage The on-chip EVRs can generate the XC2200’s core supply voltage from the (externally supplied) IO voltage. In most applications this will be the preferred option. Besides this, the core supply voltage can also be supplied by other sources, i.e. an external regulator or other voltage source.
Page 368 Generating the core supply voltage externally requires additional efforts and circuitry to provide control over the power consumption of the XC2200. Note: Running the XC2200 with external supplies requires a more complex power supply system but minimizes the heat dissipation on the chip.
Page 369: Handling The Power System
Using the power system correctly is the key to power saving. Depending on the application different operating states can be defined in order to save maximal power. The XC2200 supports following power saving mechanisms: • Reduction of the system performance –...
Page 370 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) • Software: the user program writes to the respective control registers in order to initiate a state transition There is one additional trigger that generates a power transfer: •...
Page 371: Power State Controller (Psc)
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.5.5 Power State Controller (PSC) The Power State Controller (PSC) controls the operation of the EVRs and PVCs and handles changes in the different control values. 6.5.5.1 General Overview A power state transition implies in general a change of the core voltages in one or both core supply domains.
Page 372 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Sequence Sequence Step 1 Step 1 Step x Step 2 Step 2 PVCMCONxy PVC1CONxy Step 3 Step 3 SEQxSTEPy S1VM S1V1 Step 4 Step 4 EVRMSETmmV EVR1SETnnV Step 5...
Page 373 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) and PVCyCONBx has to be pre-configured for the wake-up transition before the first power state transition is stated. A transition sequence is started if a ramp-up trigger is asserted. A transition sequence is only started if no transition is currently running.
Page 374: Operating A Power Transfer
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Asynchronous/Synchronous Continuation An asynchronous continuation event is defined if both selected PVC OK signals (from PVC_M and PVC_1) match their configured action level. A synchronous continuation event is defined by the system clock for DMP_M divided by the value of bit field SEQzSTEPx.SYSDIV.
Page 375: Power Control Registers
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.5.7 Power Control Registers 6.5.7.1 PSC Status and Control Registers SEQCON Sequence Control Register SFR (FEE4 Reset Value: 8008 IDLE Field Bits Type Description SEQATRG Sequence A Trigger...
Page 376 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description SEQBEN Sequence B Enable Sequence B is never started Sequence B is started if requested Sequence B is only started if Sequence A is not currently active.
Page 377 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description SEQAOSCDIS 13 Sequence A OSC_WU Disable This bit defines if the OSC_WU is disabled with the end of the sequence A. The enable setting for OSC_WU is left...
Page 378 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) PSCSTAT PSC Status Register SFR (FFE8 Reset Value: 0C20 Field Bits Type Description AACT Sequence A Active This bit indicates if currently sequence A is active or not.
Page 379 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) STEP0 Step 0 Register SFR (FEF2 Reset Value: C063 TRGSEL Field Bits Type Description [2:0] DMP_M Voltage Configuration This bit defines the DMP_M core supply voltage that is requested from EVR_M.
Page 380 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description [5:3] DMP_1 Voltage Configuration This bit defines the DMP_1 core supply voltage that is requested from EVR_1. Full Voltage with HP bandgap selected. If...
Page 381 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description TRGSEL [11:8] Trigger Selection This bit field defines the which of the four possible OK signals from both PVCs are used for validating the power transition.
Page 382 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description PVCMOFF PVC_M Disabled This bit defines whether the PVC_M generates any valid check results or not. The PVC_M can be disabled in order to save power.
Page 383 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) SEQASTEP1 Sequence Step 1 for Set A Register SFR (FEE6 Reset Value: 0000 TRGSEL Field Bits Type Description [2:0] DMP_M Voltage Configuration This bit defines the DMP_M core supply voltage that is requested with this step from EVR_M.
Page 384 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description [5:3] DMP_1 Voltage Configuration This bit defines the DMP_1 core supply voltage that is requested from EVR_1. Full Voltage with HP bandgap selected. If...
Page 385 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description TRGSEL [11:8] Trigger Selection This bit field defines the which of the four possible OK signals from both PVCs are used for validating the power transition.
Page 386 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description PVCMOFF PVC_M Disabled This bit defines whether the PVC generates any valid check results or not for this step. The PVC can be disabled in order to save power.
Page 387 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) SEQASTEP2 Sequence Step 2 for Set A Register SFR (FEE8 Reset Value: 0000 SEQASTEP3 Sequence Step 3 for Set A Register SFR (FEEA Reset Value: 0000 SEQASTEP4 Sequence Step 4 for Set A Register...
Page 388 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description [5:3] DMP_1 Voltage Configuration This bit defines the DMP_1 core supply voltage that is requested from EVR_1. Full Voltage with HP bandgap selected. If...
Page 389 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description TRGSEL [11:8] Trigger Selection This bit field defines the which of the four possible OK signals from both PVCs are used for validating the power transition.
Page 390 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description PVCMOFF PVC_M Disabled This bit defines whether the PVC generates any valid check results or not for this step. The PVC can be disabled in order to save power.
Page 391 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) SEQBSTEP1 Sequence Step 1 for Set B Register SFR (FEF4 Reset Value: 88DB TRGSEL Field Bits Type Description [2:0] DMP_M Voltage Configuration This bit defines the DMP_M core supply voltage that is requested with this step from EVR_M.
Page 392 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description [5:3] DMP_1 Voltage Configuration This bit defines the DMP_1 core supply voltage that is requested from EVR_1. Full Voltage with HP bandgap selected. If...
Page 393 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description TRGSEL [11:8] Trigger Selection This bit field defines the which of the four possible OK signals from both PVCs are used for validating the power transition.
Page 394 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description PVCMOFF PVC_M Disabled This bit defines whether the PVC generates any valid check results or not for this step. The PVC can be disabled in order to save power.
Page 395 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) SEQBSTEP2 Sequence Step 2 for Set B Register SFR (FEF6 Reset Value: 80EB SEQBSTEP3 Sequence Step 3 for Set B Register SFR (FEF8 Reset Value: 80F3 SEQBSTEP4 Sequence Step 4 for Set B Register...
Page 396 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description [5:3] DMP_1 Voltage Configuration This bit defines the DMP_1 core supply voltage that is requested from EVR_1. Full Voltage with HP bandgap selected. If...
Page 397 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description TRGSEL [11:8] Trigger Selection This bit field defines the which of the four possible OK signals from both PVCs are used for validating the power transition.
Page 398 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description PVCMOFF PVC_M Disabled This bit defines whether the PVC generates any valid check results or not for this step. The PVC can be disabled in order to save power.
Page 399 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) PVC1CONA1 PVC_1 Control for Step 1 Set A Register ESFR (F016 Reset Value: 0000 PVC1CONA2 PVC_1 Control for Step 2 Set A Register ESFR (F018 Reset Value: 0000...
Page 400 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description L1INTEN Level Threshold 1 Interrupt Request Enable This bit defines if an interrupt request trigger is requested if the comparison check was successful. When a check is successful is defined via bit L1ALEV.
Page 401 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description L2INTEN Level Threshold 2 Interrupt Request Enable This bit defines if an interrupt request trigger is requested if the comparison check was successful. When a check is successful is defined via bit L2ALEV.
Page 402 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) PVCMCONA1 PVC_M Control for Step 1 Set A Register MEM (F1E6 /--) Reset Value: 0000 PVCMCONA2 PVC_M Control for Step 2 Set A Register MEM (F1E8 /--) Reset Value: 0000...
Page 403 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description L1INTEN Level Threshold 1 Interrupt Request Enable This bit defines if an interrupt request trigger is requested if the comparison check was successful. When a check is successful is defined via bit L1ALEV.
Page 404 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description L2INTEN Level Threshold 2 Interrupt Request Enable This bit defines if an interrupt request trigger is requested if the comparison check was successful. When a check is successful is defined via bit L2ALEV.
Page 405 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) PVC1CONB1 PVC_1 Control for Step 1 Set B Register ESFR (F024 Reset Value: 9504 PVC1CONB2 PVC_1 Control for Step 2 Set B Register ESFR (F026 Reset Value: 0544...
Page 406 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description L1INTEN Level 1 Interrupt Request Enable This bit defines if an interrupt request trigger is requested if the comparison level check was successful. When a check is successful is defined via bit L1ALEV.
Page 407 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description L2INTEN Level 2 Interrupt Request Enable This bit defines if an interrupt request trigger is requested if the comparison level check was successful. When a check is successful is defined via bit L2ALEV.
Page 408 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) PVCMCONB1 PVC_M Control for Step 1 Set B Register MEM (F1F4 /--) Reset Value: 0544 PVCMCONB2 PVC_M Control for Step 2 Set B Register MEM (F1F6 /--) Reset Value: 0544...
Page 409 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description L1INTEN Level 1 Interrupt Request Enable This bit defines if an interrupt request trigger is requested if the comparison level check was successful. When a check is successful is defined via bit L1ALEV.
Page 410 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description L2INTEN Level 2 Interrupt Request Enable This bit defines if an interrupt request trigger is requested if the comparison level check was successful. When a check is successful is defined via bit L2ALEV.
Page 411: Global State Controller (Gsc)
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Global State Controller (GSC) Mode Control for the system peripherals provides besides power saving modes and the clock management an additional opportunity for configuring the system to the application needs.
Page 412 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) the winner of the arbitration round is the same request trigger as in the previous round or if no winner was detected no new command request is generated.
Page 413 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Table 6-13 Request Source and Command Request Coupling (cont’d) Request Source Command Description Wake-up; Normal Mode Wake-up; Normal Mode GPT12E Wake-up; Normal Mode Wake-up; Normal Mode Clock-off; Stop Mode OCDS entry Debug;...
Page 414 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) The mode that has to be entered when the Suspend Mode is requested. The mode that has to be entered when the Suspend Mode is left. The request to enter Suspend Mode is forwarded from the OCDS. When the Suspend...
Page 415: Gsc Registers
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.6.2 GSC Registers 6.6.2.1 GSC Control and Status Registers The following register control and configure the behavior of the GSC. GSCSWREQ GSC Software Request Register SFR (FF14 Reset Value: 0000...
Page 416 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) GSCEN GSC Enable Register SFR (FF16 Reset Value: 7FFF Field Bits Type Description PSCBEXEN PSC Sequence B Exit Request Trigger Enable PSC sequence B exit request trigger is not...
Page 417 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description ESR0EN ESR0 Request Trigger Enable ESR0 request trigger is not taken into account (disabled) ESR0 request trigger is taken into account (enabled) ESR1EN ESR1 Request Trigger Enable...
Page 418 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description SW2EN Software 2 Request Trigger Enable SW2 request trigger is not taken into account (disabled) SW2 request trigger is taken into account (enabled) RES1 Reserved Read as 1 after reset;...
Page 419 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) GSCSTAT GSC Status Register SFR (FF18 Reset Value: 3C00 SOURCE PEN ERR NEXT CURRENT Field Bits Type Description CURRENT [1:0] Currently used Command This bit field states the currently used system mode.
Page 420 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description SOURCE [13:10] rh Requesting Source Status This bit field monitors the source that triggered the last request. 0000 PSCB exit 0001 PSCB entry 0010...
Page 421: Software Boot Support
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Software Boot Support In order to determine the correct starting point of operation for the software a minimum of hardware support is required. As much as possible is done via software. Some decisions have to be done in hardware because they must be known before any software is operational.
Page 422: External Request Unit (Eru)
ADC module. 6.8.1 Introduction The ERU of the XC2200 can be split in three main functional parts: • 4 independent Input Channels x for input selection and conditioning of trigger or gating functions •...
Page 423 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) common trigger. For each of these two signals, an input vector of 4 possible inputs is available (e.g. the actual input ERU_xA can be selected from one of the ERU inputs ERU_xA[3:0], similar for ERU_xB).
Page 424: Eru Pin Connections
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.8.2 ERU Pin Connections Figure 6-24 shows the ERU input connections, either directly with pins or via communication modules, such as USIC or MultiCAN. These communication modules provide their input signals (e.g. CAN receive input, or USIC data, clock, or control inputs) that have been selected in these modules.
Page 425 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) modules, such as the USIC (signals named with prefix UxCy to indicate which the communication channel) and the MultiCAN modules. These signals are input signals from the pin that has been selected as input for a USIC or MultiCAN function. The selection of the input is made within the respective USIC or MultiCAN module.
Page 426 An edge of an input can only be correctly detected if both, the high phase and the low phase of the input are each longer than 1/f Table 6-14 ERSx Connections in XC2200 Input from/to I/O to...
Page 427 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Table 6-14 ERSx Connections in XC2200 (cont’d) Input from/to I/O to Can be used to/as Module ERSx ERU_2B0 U2C0_DX1INS ERS2 input B ERU_2B1 MultiCAN_CAN2INS ERU_2B2 U2C1_DX0INS ERU_2B3 U2C1_DX2INS...
Page 428: External Request Select Unit (Ersx)
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.8.3 External Request Select Unit (ERSx) For each Input Channel x (x = 0-3), an ERSx unit handles the input selection for the associated ETLx unit. Each ERSx performs a logical combination of two signals (Ax, Bx) to provide one combined output ERSxO to the associated ETLx.
Page 429: Event Trigger Logic (Etlx)
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.8.4 Event Trigger Logic (ETLx) For each Input Channel x (x = 0-3), an event trigger logic ETLx derives a trigger event and a status from the input ERUxO delivered by the associated ERSx unit. Each ETLx is based on an edge detection block, where the detection of a rising or a falling edge can be individually enabled.
Page 430 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) detection where the actual status of the input is important (enabling both edge detections is not useful in this mode). The output of the status flag is connected to all following Output Gating Units (OGUy) in...
Page 431: Connecting Matrix
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.8.5 Connecting Matrix The connecting matrix distributes the trigger signals (TRxy) and status signals (EXICONx.FL) from the different ETLx units between the OGUy units. In addition, it receives peripheral trigger signals that can be OR-combined with the ETLx trigger signals in the OGUy units.
Page 432: Output Gating Unit (Oguy)
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.8.6 Output Gating Unit (OGUy) Each OGUy (y = 0-3) unit combines the available trigger events and status flags from the Input Channels and distributes the results to the system.
Page 433 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Each OGUy unit generates 4 output signals that are distributed to the system (not all of them are necessarily used, please refer to Section 6.8.7): • ERU_PDOUTy to directly output the pattern match information for gating purposes in other modules (pattern match = 1).
Page 434 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Table 6-15 OGUy Peripheral Trigger Connections in XC2200 Input from/to I/O to Can be used to/as Module OGUy OGU0 Inputs ERU_OGU01 CCU60_MCM_ST Peripheral triggers for OGU0 ERU_OGU02 CCU60_T13_PM...
Page 435 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) In addition, the pattern detection can deliver a trigger event if the pattern detection result changes from match to miss or vice-versa (if enabled by EXOCONy.GEEN = 1). The pattern result change event is logically OR-combined with the other enabled trigger events to support interrupt generation or to trigger other module functions (e.g.
Page 436: Eru Output Connections
ERU Output Connections This section describes the connections of the ERU output signals for gating or triggering other module functions, as well as the connections to the interrupt control registers. Table 6-16 ERU Output Connections in XC2200 Output from/to I/O to...
Page 437 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Table 6-16 ERU Output Connections in XC2200 (cont’d) Output from/to I/O to Can be used to/as Module OGUy ERU_TOUT2 not connected Trigger output ERU_IOUT2 ITC (CC2_CC18IC) Interrupt output...
Page 438: Eru Registers
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.8.8 ERU Registers 6.8.8.1 External Input Selection Register EXISEL This register selects the A and B inputs for all four ERS units. The possible input signals are given in Table 6-14.
Page 439 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description EXS2A [9:8] External Source Select for A2 (ERS2) This bit field defines which input is selected for A2. Input ERU_2A0 is selected Input ERU_2A1 is selected...
Page 440 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.8.8.2 External Input Control Registers EXICONx These registers control the inputs of the ERSx unit and the trigger functions of the ETLx units (x = 0..3). EXICON0 External Input Control 0 Register...
Page 441 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description Rebuild Level Detection for Status Flag for ETLx This bit selects if the status flag FL is used as “sticky” bit or if it rebuilds the result of a level detection.
Page 442 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description [9:8] Input Source Select for ERSx This bit field defines which logical combination is taken into account as ESRxO. Input A without additional combination...
Page 443 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.8.8.3 Output Control Registers EXOCONy These registers control the outputs of the Output Gating Unit y (y = 0..3). EXOCON0 External Output Trigger Control 0 Register SFR (FE30...
Page 444 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description [5:4] Gating Selection for Pattern Detection Result This bit field defines the gating scheme for the interrupt generation (relation between the OGU output ERU_PDOUTy and ERU_GOUTy).
Page 445: Scu Interrupt Generation
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) SCU Interrupt Generation The interrupt structure of the SCU is shown in Figure 6-29. clear INTCLR.x INTSTAT.x INTNPy.x Interrupt INTSET.x to ITC node 6C , int 0 Event...
Page 446: Scu Interrupt Sources
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) DMP_1. In this way, the occurrence of a request is registered even when the DMP_1 domain, including the SCU, is powered down. The registered event can then be processed when the SCU is in normal power mode again.
Page 447: Interrupt Control Registers
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.9.3 Interrupt Control Registers 6.9.3.1 Register INTSTAT This register contains the status flags for all interrupt request trigger sources of the SCU. For setting and clearing of these status bits by software see registers INTSET and INTCLR, respectively.
Page 448 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description PVCMI2 PVC_M Interrupt Request Flag 2 This bit is set if bit DMPMIT.PVCMI2 is set. No PVCMI2 interrupt trigger has occured since this bit was cleared the last time...
Page 449 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description GSCI GSC Interrupt Request Flag This bit is set if the GSC error bit is set and bit is INTDIS.GSCI = 0. No GSC interrupt trigger has occured since...
Page 450 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.9.3.2 Register INTCLR This register contains the software clear option for all status flags of all interrupt request trigger sources of the SCU. INTCLR Interrupt Clear Register SFR (FE82...
Page 451 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description WDTI Clear Watchdog Timer Interrupt Request Flag No action Bit INTSTAT.WDTI is cleared GSCI Clear GSC Interrupt Request Flag No action Bit INTSTAT.GSCI is cleared...
Page 452 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.9.3.3 Register INTSET This register contains the software set option for all status flags of all interrupt request trigger sources of the SCU. INTSET Interrupt Set Register SFR (FE80...
Page 453 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description WDTI Set Watchdog Timer Interrupt Request Flag No action Bit INTSTAT.WDTI is set GSCI Set GSC Interrupt Request Flag No action Bit INTSTAT.GSCI is set...
Page 454 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.9.3.4 Register INTDIS This register contains the software disable control for all interrupt request trigger sources of the SCU. INTDIS Interrupt Disable Register SFR (FE84 Reset Value: 0000...
Page 455 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description WDTI Disable Watchdog Timer Interrupt Request WDT interrupt request enabled WDT interrupt request disabled GSCI Disable GSC Interrupt Request GSC interrupt request enabled GSC interrupt request disabled...
Page 456 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.9.3.5 Registers INTNP0 and INPNP1 These registers contain the control for the interrupt node pointers of all interrupt request trigger sources of the SCU. INTNP0 Interrupt Node Pointer 0 Register...
Page 457 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description PVCM2 [7:6] Interrupt Node Pointer for PVC_M 2 Interrupts This bit field defines the interrupt node, which is requested due to the set condition for bit INTSTAT.PCVMI2 (if enabled by bit INTDIS.PVCMI2).
Page 458 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) INTNP1 Interrupt Node Pointer 1 Register SFR (FE88 Reset Value: 0001 6.9.3.6 Field Bits Type Description [1:0] Interrupt Node Pointer for WDT Interrupts This bit field defines the interrupt node, which is requested due to the set condition for bit INTSTAT.WDTI (if enabled by bit...
Page 459 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.9.3.7 Register DMPMIT This register contains additional sticky interrupt and trap flags. DMPMIT DMP_M Interrupt and Trap Trigger Register SFR (FE96 Reset Value: 0000 Field Bits Type Description...
Page 460 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description PVCMI2 3 PVC_M Interrupt Request Flag 2 This bit is set if bit PVCMCON0.LEV2OK is cleared and PVCMCON0.L2INTEN = 1 and INTDIS.PVCMI2 = 0.
Page 461 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description GSC Interrupt Request Flag This bit is set if a GSC trigger occurs and INTDIS.GSCI = 0. No GSC interrupt was requested since this bit was...
Page 462 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.9.3.8 Register DMPMITCLR This register contains the software clear option for all sticky status flags of all interrupt and trap request trigger sources of the DMP_M power domain.
Page 463 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description Clear GSC Interrupt Request Flag No action Bit DMPMIT.GSCI is cleared ESR0T Clear ESR0 Trap Request Flag No action Bit DMPMIT.ESR0T is cleared ESR1T...
Page 464 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.9.3.9 Alternate Interrupt Source Assignment In order to map the interrupt request sources in the complete system to the available interrupt nodes, interrupt nodes are shared between selected modules.
Page 465 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description ISS8 Interrupt Source Select for CC2_CC24IC CC2 channel 24 interrupt is selected External interrupt request ERU_IOUT0 is selected ISS9 Interrupt Source Select for CC2_CC25IC...
Page 466: Temperature Compensation Unit
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.10 Temperature Compensation Unit The temperature compensation for the port drivers provides driver output characteristics which are stable (within a certain band of parameter variation) over the specified temperature range.
Page 467 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Note: The temperature compensation circuit does not generate temperature compensation values continously. The idea is, that the SW frequently updates the pad control with the value currently found in the tempcomp register (e.g. by an interrupt generated by a timer).
Page 468: Temperature Compensation Registers
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.10.1 Temperature Compensation Registers 6.10.1.1 TCCR This register contains the control options. TCCR Temperature Compensation Control Register ESFR (F1AC Reset Value: 0003 TCDIV Field Bits Type Description [1:0]...
Page 469 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) TCLR Temperature Comp. Level Register ESFR (F0AC Reset Value: 0000 THCOUNT Field Bits Type Description THCOUNT [7:0] Threshold Counter Returns the result of the most recent count cycle of the temperature sensor, to be compared with the thresholds.
Page 470: Watchdog Timer (Wdt)
XC2200 in a user-specified time period. When enabled, the WDT will cause the XC2200 system to be reset if the WDT is not serviced within a user- programmable time period. The CPU must service the WDT within this time interval to prevent the WDT from causing a WDT reset request trigger.
Page 471: Functional Description
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.11.3 Functional Description The following part describes all functions of the WDT. 6.11.3.1 Timer Operation The timer is enabled when instruction ENWDT (Enable Watchdog Timer) is executed correctly.
Page 472 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Internal Application Reset Application Reset Normal Mode Timer DISWDT overflow / WDT interrupt trigger Reload WDT with FFFF ENWDT Pre-Warning Disable Mode Mode Overflow and Overflow and STMEM0.WDTCSOE = 0 and STMEM0.WDTCSOE = 1 and...
Page 473 A further feature of the WDT detects double errors and sets the whole system into a permanent WDT reset. This feature prevents the XC2200 from executing random wrong code for longer than the occurence of the overflow, and prevents the XC2200 from being repeatedly reset by the WDT.
Page 474 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) resulting (without any change in the reset configuration) in a permanent reset of the type configured by RSTCON1.WDT. The information about the first WDT reset request is stored in bit STMEM0.WDTCSOE...
Page 475: Wdt Kernel Registers
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.11.4 WDT Kernel Registers 6.11.4.1 WDT Reload Register This register defines the WDT reload value. WDTREL WDT Reload Register ESFR (F0C8 Reset Value: FFFC RELV Field Bits Type...
Page 476 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.11.4.2 WDT Control and Status Register The Control and Status Register can only be accessed in Secured Mode. WDTCS WDT Control and Status Register ESFR (F0C6 Reset Value: 0000...
Page 477 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description Input Frequency Request Bit Request to set input frequency to / 16384 Request to set input frequency to / 256 An update of this bit is taken into account after the...
Page 478 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.11.4.3 WDT Timer Register WDTTIM WDT Timer Register ESFR (F0CA Reset Value: FFFC Field Bits Type Description [15:0] Timer Value Reflects the current contents of the Watchdog Timer.
Page 479: Scu Trap Generation
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.12 SCU Trap Generation The basic trap structure of the SCU is shown in Figure 6-33. clear TRAPCLR.x TRAPSTAT.x TRAPNPn.y Trap TRAPSET.x Event TRQ0 to TFR.ACER TRQ1 to TFR.SR1 DMPMIT.x...
Page 480: Scu Trap Sources
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) domain, including the SCU, is powered down. The registered event can then be processed when the SCU is in normal power mode again. Please note that the disable...
Page 481: Scu Trap Control Registers
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.12.3 SCU Trap Control Registers 6.12.3.1 Register TRAPSTAT This register contains the status flags for all trap request trigger sources of the SCU. For setting and clearing of these status bits by software see registers TRAPSET and TRAPCLR, respectively.
Page 482 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description ESR2T ESR2 Trap Request Flag TRAPSTAT.ESR2T is set when bit DMPMIT.ESR0T is set and TRAPDIS.ESR2T = 0. No ESR2 trap trigger has occured since this bit...
Page 483 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.12.3.2 Register TRAPCLR This register contains the software clear control for the trap status flags in register TRAPSTAT. Clearing a bit in this register has no effect, reading a bit always returns zero.
Page 484 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description [15:8] Reserved Read as 0; should be written with 0 User’s Manual 6-224 V2.1, 2008-08 SCU, V1.13...
Page 485 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.12.3.3 Register TRAPSET This register contains the software set control for the trap status flags in register TRAPSTAT. Clearing a bit in this register has no effect, reading a bit always returns zero.
Page 486 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description [15:8] Reserved Read as 0; should be written with 0. User’s Manual 6-226 V2.1, 2008-08 SCU, V1.13...
Page 487 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.12.3.4 Register TRAPDIS This register contains the software disable control for all trap request trigger sources. Note that the bits ESRxT and RAT in this register also disable the setting of the...
Page 488 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description [15:8] Reserved Read as 0; should be written with 0. User’s Manual 6-228 V2.1, 2008-08 SCU, V1.13...
Page 489 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.12.3.5 Register TRAPNP This register contains the control for the trap node pointers of all SCU trap request trigger sources. TRAPNP Trap Node Pointer Register SFR (FE92 Reset Value: 8254...
Page 490 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description ESR2 [7:6] Trap Node Pointer for ESR2 Traps TRAPNP.ESR2 selects the trap request output for an enabled ESR2 trap request. Select request output SCU_TRQ0 (TFR.ACER) Select request output SCU_TRQ1 (TFR.SR1)
Page 491: Memory Content Protection
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.13 Memory Content Protection For supervising the content of the on-chip memories (Flash memory is not considered here) Parity Checking is provided. 6.13.1 Parity Error Handling The on-chip RAM modules check parity information during read accesses and in case of an error a signal can be generated if enabled.
Page 492 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) PMTSR. PESEN & Parity & U2RAM error & Parity & U1RAM error & Parity & U0RAM error & Parity & MCRAM p_trap >1 error pf_trap & Parity &...
Page 493 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.13.1.1 Parity Software Testing Support To support testing algorithms for the parity error trap routines a memory parity test logic is implemented for the C166SV2 subsystem memories (PSRAM, DSRAM, and DPRAM) and SBRAM.
Page 494 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.13.1.2 Parity Error Registers Register PECON The following register controls the functional parity check mechanism. PECON Parity Error Control Register ESFR (F0C4 Reset Value: 0000 Field Bits Type...
Page 495 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description PEENU2 Parity Error Trap Enable for USIC2 Memory No Parity trap is requested for USIC2 memory parity errors A Parity trap is requested for USIC2 memory...
Page 496 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description PEFPS Parity Error Flag for Program SRAM No Parity errors have been detected for program SRAM A Parity error is indicated and can trigger a trap...
Page 497 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Field Bits Type Description PEFMC Parity Error Flag for MultiCAN Memory No Parity errors have been detected for MultiCAN memory A Parity error is indicated and can trigger a trap...
Page 498 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) PMTPR Parity Memory Test Pattern RegisterESFR (F0E4 Reset Value: 0000 Field Bits Type Description [15:8] Parity Read Values for Memory Test For each byte of a memory module the parity bits generated during the most recent read access are indicated here.
Page 499 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) PMTSR Parity Memory Test Select RegisterESFR (F0E6 Reset Value: 0000 Field Bits Type Description MTENDP Memory Test Enable Control for Dual Port Memory Controls the test multiplexer for the dual port memory.
Page 500: Register Control
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.14 Register Control This block handles the register accesses of the SCU and the register access control for all system register that use one of the following protection modes: •...
Page 501 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) an application: In case the succeeding write to a protected register is delayed due to an interrupt and the ISR itself uses the “command 4” mechanism. After writing “command 4”...
Page 502 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) “command 0 - command 1 - command 2 - command 3”. This sequence establishes a new security level and/or a new password. Table 6-21 Commands for Security Level Control...
Page 503: Register Protection Registers
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.14.2 Register Protection Registers Register SLC This register is the interface for the protection commands. Security Level Command RegisterESFR (F0C0 Reset Value: 0000 COMMAND Field Bits Type Description...
Page 504 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Register SLS This register monitors the status of the register protection. Security Level Status Register ESFR (F0C2 Reset Value: 0000 STATE PASSWORD Field Bits Type Description PASSWORD [7:0]...
Page 505: Miscellaneous System Registers
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.15 Miscellaneous System Registers This chapter acts as container for various register that are not connected to one specific application topic. 6.15.1 System Registers 6.15.1.1 System Control Register The following register serve several different system tasks.
Page 506: Identification Block
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.15.2 Identification Block For identification of the most important silicon parameters a set of identification registers is defined that provide information on the chip manufacturer, the chip type and its properties.
Page 507 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.15.2.1 Identification Registers Register IDMANUF This register contains information about the manufacturer. IDMANUF Manufacturer Identification Register ESFR (F07E Reset Value: 1820 MANUF DEPT Field Bits Type Description DEPT...
Page 508 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Register IDCHIP This register contains information about the device. IDCHIP Chip Identification Register ESFR (F07C Reset Value: XXXX CHIPID Revision Field Bits Type Description Revision [7:0] Device Revision Code Identifies the device step.
Page 509 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Register IDMEM This register contains information about the program memory. IDMEM Program Memory Identification Register ESFR (F07A Reset Value: 3XXX TYPE SIZE Field Bits Type Description SIZE [11:0]...
Page 510 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Register IDPROG This register contains information about the flash programming voltage. IDPROG Programming Voltage Id. Register ESFR (F078 Reset Value: 1313 PROGVPP PROGVDD Field Bits Type Description PROGVDD...
Page 511: Marker Memory
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.15.3 Marker Memory 6.15.3.1 Marker Memory Registers The marker memory consists of following SFRs located in the DMP_M for free usage of the user software. MKMEM0 Marker Memory 0 Register...
Page 512: Scu Register Addresses
System Units (Vol. 1 of 2) System Control Unit (SCU) 6.16 SCU Register Addresses The SCU registers are within the (E)SFR space of the XC2200. Therefore, their specified addresses equal an offset from zero. Table 6-22 Registers Address Space Module...
Page 513 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Table 6-23 Register Overview of SCU Short Name Register Long Name Offset Protec Reset Power Addr. tion Domain RTCCLKCON RTC Clock Control FF4E Power-on DMP_1 Register Reset EXTCON...
Page 514 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Table 6-23 Register Overview of SCU Short Name Register Long Name Offset Protec Reset Power Addr. tion Domain SWDCON0 SWD Control 0 Register F080 Power-on DMP_M Reset SWDCON1...
Page 515 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Table 6-23 Register Overview of SCU Short Name Register Long Name Offset Protec Reset Power Addr. tion Domain PVCMCONA2 PVC_M Register for F1E8 Power-on DMP_M Step 2 Sequence A...
Page 516 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Table 6-23 Register Overview of SCU Short Name Register Long Name Offset Protec Reset Power Addr. tion Domain EVRMSET10V EVR_M Setting for 1.0V F090 Power-on DMP_M Register Reset EVRMSET15VLP EVR_M Setting for 1.5V...
Page 517 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Table 6-23 Register Overview of SCU Short Name Register Long Name Offset Protec Reset Power Addr. tion Domain PSCSTAT PSC Status Register FFE8 Power-on DMP_M Reset GSCSWREQ GSC SW Request...
Page 518 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Table 6-23 Register Overview of SCU Short Name Register Long Name Offset Protec Reset Power Addr. tion Domain INTCLR Interrupt Clear Register FE82 Application DMP_1 Reset INTSET Interrupt Set Register...
Page 519 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) Table 6-23 Register Overview of SCU Short Name Register Long Name Offset Protec Reset Power Addr. tion Domain TRAPDIS Trap Disable Register FE90 Power-on DMP_1 Reset TRAPNP Trap Node Pointer...
Page 520: Implementation
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.17 Implementation This section shows the connections of the module to the system. 6.17.1 Clock Generation Unit The following table shows the input connection of the Clock Genation Unit.
Page 521: Esr
XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) 6.17.2 The availability of pins ESR1 and ESR2 is device and package dependent. It is described in the data sheet. Pin ESR0 does not offer an overlay with other product functions.
Page 522 XC2200 Derivatives System Units (Vol. 1 of 2) System Control Unit (SCU) User’s Manual 6-262 V2.1, 2008-08 SCU, V1.13...
Page 523: Parallel Ports
XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports Parallel Ports The XC2200 provides a set of General Purpose Input/Output (GPIO) ports that can be controlled by software and by the on-chip peripheral units: Table 7-1 Ports of the XC2200...
Page 524: General Description
XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports General Description This chapter describes the architecture of the digital control circuit for a single port pin. 7.1.1 Basic Port Operation There are three types of digital control circuits: with/without hardware override for digital GPIOs, and for one for analog inputs.
Page 525 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports POCON.PPS SCU_PERCFG.PGRx HW_DIR Pn_IOCR control control Pn_OMR pull Pn_OUT devices Pn_IN input ALTIN stage HW_EN INV* output ALT1 stage ALT2 ALT3 HW_OUT ENDQ1 TC[1:0] PD[2:0] Standard_EBCport_structure_5.vsd Figure 7-2 Structure of the Ports with Hardware Override Functionality Note: If HW_EN is activated, INV* signal is always zero.
Page 526 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports ENABQ Pn_DIDIS Pn_IN Input stage Analog Input Analog_port_digital_structure_2.vsd Figure 7-3 Structure of Port 5 and Port 15 Note: There is always a standard digital input connected in parallel to each analog input.
Page 527: Input Stage Control
XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports 7.1.2 Input Stage Control An input stage consists of a Schmitt trigger, which can be enabled or disabled via software, and an input multiplexer that by default selects the output of the input Schmitt trigger.
Page 528: Port Register Description
4 pins of the respective port. Note: P2_POCON register in the XC2200 contains an exception regarding the additional strong output driver connected in parallel to the standard output driver of the P2.8 pin.
Page 529 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports Px_POCON (x=0-4) Port x Output Control Register XSFR (E8A0 +2*x) Reset Value: 0000 Px_POCON (x=6-11) Port x Output Control Register XSFR (E8A0 +2*x) Reset Value: 0000 PDM3 PDM2 PDM1 PDM0...
Page 530 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports Mapping of the POCON Registers to Pins and Ports The table below lists the defined POCON registers and the allocation of control bit fields and port pins. Table 7-2 Port Output Control Register Allocation Control Controlled Pins (by Px_POCON.[y:z])
Page 531: Port Output Register
XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports 7.2.2 Port Output Register The port output register defines the values of the output pins if the pin is used as GPIO output. Pn_OUT (n=0-4) Port n Output Register SFR (FFA2...
Page 532: Port Output Modification Register
XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports 7.2.3 Port Output Modification Register The port output modification register contains the bits to individually set, clear, or toggle the value of the port n output register. P2_OMRH Port 2 Output Modification Register HighXSFR (E9CA...
Page 533 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports Field Bits Type Description Port Set Bit x (x = 0-7) Setting this bit sets or toggles the corresponding bit in the port output register Pn_OUT (see Table 7-3). On a read access, this bit returns X.
Page 534: Port Input Register
XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports 7.2.4 Port Input Register The port input register contains the values currently read at the input pins, also if a port line is assigned as output. Pn_IN (n=0-11) Port n Input Register...
Page 535: Port Input/Output Control Registers
XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports 7.2.5 Port Input/Output Control Registers The port input/output control registers contain the bit fields to select the digital output and input driver characteristics, such as pull-up/down devices, port direction (input/output), open-drain and alternate output selections.
Page 536 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports Field Bits Type Description [7:4] Port Input/Output Control Bit Table 7-4 [3:0], reserved [15:8] Coding of the PC bit field The coding of the GPIO port behavior is done by the bit fields in the port control registers Pn_IOCRx.
Page 537 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports Table 7-4 PC Coding PC[3:0] Selected Pull-up/down / Behavior in Power Saving Selected Output Function Mode 1000 Output General purpose Output Output driver off. (Direct Input Schmitt trigger off. 1001...
Page 538 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports 7.2.6 Port Digital Input Disable Register Ports 5 and 15 have, additionally to the analog input functionality, digital input functionality too. In order to save switching of the internal Schmitt triggers of the digital inputs, they can be disabled by means of Px_DIDIS Register.
Page 539 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports Port Description The bit positions in the port registers always start right-aligned. For example, a port comprising only 8 pins only uses the bit positions [7:0] of the corresponding register. The remaining bit positions are filled with 0 (r).
Page 540: Port 15
XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports 7.3.1 Port 0 Port 0 is an 8-bit GPIO port. The registers of Port 0 are shown in Figure 7-4. For this port, all pins can be read as GPIO, from the Port Input Register.
Page 541 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports 7.3.2 Port 1 Port 1 is an 8-bit GPIO port. Theregisters of Port 1 are shown in Figure 7-5. Modification Data Control Registers Registers Registers P1_IOCR00 P1_OMRL P1_OUT P1_IN P1_IOCR07 P1_POCON Port1_Regs.vsd...
Page 542 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports 7.3.3 Port 2 Port 2 is an 13-bit GPIO port. The registers of Port 2 are shown in Figure 7-6. For this port, all pins can be read as GPIO, from the Port Input Register.
Page 543 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports Table 7-7 Port 2 Registers (cont’d) Register Register Long Name Address Reset Short Name Offset Value P2_IOCR10 Port 2 Input/Output Control Register 10 E854 0000 P2_IOCR11 Port 2 Input/Output Control Register 11...
Page 544 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports 7.3.4 Port 3 Port 3 is an 8-bit GPIO port. The registers of Port 3 are shown in Figure 7-7. For this port, all pins can be read as GPIO, from the Port Input Register.
Page 545 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports 7.3.5 Port 4 Port 4 is an 8-bit GPIO port. The registers of Port 4 are shown in Figure 7-8. For this port, all pins can be read as GPIO, from the Port Input Register.
Page 546 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports 7.3.6 Port 5 Port 5 is an 16-bit analog or digital input port. To use the Port 5 as an analog input, the Schmitt trigger in the input stage must be disabled.
Page 547 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports 7.3.7 Port 6 Port 6 is an 4-bit GPIO port. The registers of Port 6 are shown in Figure 7-10. For this port, all pins can be read as GPIO, from the Port Input Register.
Page 548 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports 7.3.8 Port 7 Port 7 is a 5-bit GPIO port. The port registers of Port 7 are shown in Figure 7-11. For this port, all pins can be read as GPIO, from the Port Input Register.
Page 549 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports 7.3.9 Port 8 Port 8 is an 7-bit GPIO port. The registers of Port 8 are shown in Figure 7-12. For this port, all pins can be read as GPIO, from the Port Input Register.
Page 550 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports 7.3.10 Port 9 Port 9 is an 8-bit GPIO port. The port registers of Port 9 are shown in Figure 7-13. For this port, all pins can be read as GPIO, from the Port Input Register.
Page 551 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports 7.3.11 Port 10 Port 10 is a 16-bit GPIO port. The registers of Port 10 are shown in Figure 7-14. For this port, all pins can be read as GPIO, from the Port Input Register.
Page 552 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports Table 7-15 Port 10 Registers (cont’d) Register Register Long Name Address Reset Short Name Offset Value P10_IOCR10 Port 10 Input/Output Control Register 10 E954 0000 P10_IOCR11 Port 10 Input/Output Control Register 11...
Page 553 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports 7.3.12 Port 11 Port 11 is an 6-bit GPIO port. The registers of Port 11 are shown in Figure 7-15. For this port, all pins can be read as GPIO, from the Port Input Register.
Page 554 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports 7.3.13 Port 15 Port 15 is an 8-bit analog or digital input port. To use the Port 15 as an analog input, the Schmitt trigger in the input stage must be disabled. This is achieved by setting the corresponding bit in the register P15_DIDIS.
Page 555: Pin Description
System Units (Vol. 1 of 2) Parallel Ports Pin Description Each port pin of the XC2200 can serve several functions of different modules. Also, most functions are available on several port pins. This enables an application so select the optimal connections for its specific circumstances.
Page 556 For normal system operation, pin TRST should be held low. A high level at this pin at the rising edge of PORST activates the XC2200’s debug system. In this case, pin TRST must be driven low once to reset the debug system.
Page 557 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports Table 7-18 Pin Definitions and Functions (cont’d) Symbol Ctrl. Type Function P7.1 O0 / I St/B Bit 1 of Port 7, General Purpose Input/Output EXTCLK St/B Programmable Clock Signal Output...
Page 558 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports Table 7-18 Pin Definitions and Functions (cont’d) Symbol Ctrl. Type Function P6.2 O0 / I St/A Bit 2 of Port 6, General Purpose Input/Output EMUX2 St/A External Analog MUX Control Output 2 (ADC0)
Page 559 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports Table 7-18 Pin Definitions and Functions (cont’d) Symbol Ctrl. Type Function P15.7 In/A Bit 7 of Port 15, General Purpose Input ADC1_CH7 In/A Analog Input Channel 7 for ADC1 PS/A Reference Voltage for A/D Converter ADC1...
Page 560 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports Table 7-18 Pin Definitions and Functions (cont’d) Symbol Ctrl. Type Function P5.8 In/A Bit 8 of Port 5, General Purpose Input ADC0_CH8 In/A Analog Input Channel 8 for ADC0 CCU6x_T12H...
Page 561 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports Table 7-18 Pin Definitions and Functions (cont’d) Symbol Ctrl. Type Function P2.11 O0 / I St/B Bit 11 of Port 2, General Purpose Input/Output U0C0_SELO St/B USIC0 Channel 0 Select/Control 2 Output...
Page 562 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports Table 7-18 Pin Definitions and Functions (cont’d) Symbol Ctrl. Type Function P4.0 O0 / I St/B Bit 0 of Port 4, General Purpose Input/Output CC2_24 O3 / I St/B CAPCOM2 CC24IO Capture Inp./ Compare Out.
Page 563 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports Table 7-18 Pin Definitions and Functions (cont’d) Symbol Ctrl. Type Function P11.1 O0 / I St/B Bit 1 of Port 11, General Purpose Input/Output CCU63_CCP St/B CCU63 Position Input 1 OS1A P11.0...
Page 564 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports Table 7-18 Pin Definitions and Functions (cont’d) Symbol Ctrl. Type Function P4.3 O0 / I St/B Bit 3 of Port 4, General Purpose Input/Output CC2_27 O3 / I St/B CAPCOM2 CC27IO Capture Inp./ Compare Out.
Page 565 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports Table 7-18 Pin Definitions and Functions (cont’d) Symbol Ctrl. Type Function P0.1 O0 / I St/B Bit 1 of Port 0, General Purpose Input/Output U1C0_DOUT O1 St/B USIC1 Channel 0 Shift Data Output...
Page 566 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports Table 7-18 Pin Definitions and Functions (cont’d) Symbol Ctrl. Type Function P0.2 O0 / I St/B Bit 2 of Port 0, General Purpose Input/Output U1C0_SCLK St/B USIC1 Channel 0 Shift Clock Output...
Page 567 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports Table 7-18 Pin Definitions and Functions (cont’d) Symbol Ctrl. Type Function P0.3 O0 / I St/B Bit 3 of Port 0, General Purpose Input/Output U1C0_SELO St/B USIC1 Channel 0 Select/Control 0 Output...
Page 568 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports Table 7-18 Pin Definitions and Functions (cont’d) Symbol Ctrl. Type Function TRef Sp/1 Control Pin for Core Voltage Generation Connect TRef to to use the on-chip EVRs. DDPB Connect TRef to...
Page 569 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports Table 7-18 Pin Definitions and Functions (cont’d) Symbol Ctrl. Type Function P0.5 O0 / I St/B Bit 5 of Port 0, General Purpose Input/Output U1C1_SCLK St/B USIC1 Channel 1 Shift Clock Output...
Page 570 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports Table 7-18 Pin Definitions and Functions (cont’d) Symbol Ctrl. Type Function P3.4 O0 / I St/B Bit 4 of Port 3, General Purpose Input/Output U2C1_SELO St/B USIC2 Channel 1 Select/Control 0 Output...
Page 571 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports Table 7-18 Pin Definitions and Functions (cont’d) Symbol Ctrl. Type Function P0.6 O0 / I St/B Bit 6 of Port 0, General Purpose Input/Output U1C1_DOUT O1 St/B USIC1 Channel 1 Shift Data Output...
Page 572 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports Table 7-18 Pin Definitions and Functions (cont’d) Symbol Ctrl. Type Function P10.7 O0 / I St/B Bit 7 of Port 10, General Purpose Input/Output U0C1_DOUT O1 St/B USIC0 Channel 1 Shift Data Output...
Page 573 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports Table 7-18 Pin Definitions and Functions (cont’d) Symbol Ctrl. Type Function P1.0 O0 / I St/B Bit 0 of Port 1, General Purpose Input/Output U1C0_MCLK St/B USIC1 Channel 0 Master Clock Output...
Page 574 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports Table 7-18 Pin Definitions and Functions (cont’d) Symbol Ctrl. Type Function P10.9 O0 / I St/B Bit 9 of Port 10, General Purpose Input/Output U0C0_SELO St/B USIC0 Channel 0 Select/Control 4 Output...
Page 575 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports Table 7-18 Pin Definitions and Functions (cont’d) Symbol Ctrl. Type Function P10.11 O0 / I St/B Bit 11 of Port 10, General Purpose Input/Output U1C0_SCLK St/B USIC1 Channel 0 Shift Clock Output...
Page 576 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports Table 7-18 Pin Definitions and Functions (cont’d) Symbol Ctrl. Type Function P9.3 O0 / I St/B Bit 3 of Port 9, General Purpose Input/Output CCU63_COU St/B CCU63 Channel 0 Output...
Page 577 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports Table 7-18 Pin Definitions and Functions (cont’d) Symbol Ctrl. Type Function P9.5 O0 / I St/B Bit 5 of Port 9, General Purpose Input/Output CCU63_COU St/B CCU63 Channel 2 Output...
Page 578 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports Table 7-18 Pin Definitions and Functions (cont’d) Symbol Ctrl. Type Function P1.5 O0 / I St/B Bit 5 of Port 1, General Purpose Input/Output CCU62_COU St/B CCU62 Channel 0 Output...
Page 579 DDI1 PORST In/B Power On Reset Input A low level at this pin resets the XC2200 completely. A spike filter suppresses input pulses <10 ns. Input pulses >100 ns safely pass the filter. The minimum duration for a safe recognition should be 120 ns.
Page 580 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports Table 7-18 Pin Definitions and Functions (cont’d) Symbol Ctrl. Type Function ESR2 O0 / I St/B External Service Request 2 U1C1_DX0D St/B USIC1 Channel 1 Shift Data Input U1C1_DX2C St/B...
Page 581 XC2200 Derivatives System Units (Vol. 1 of 2) Parallel Ports Table 7-18 Pin Definitions and Functions (cont’d) Symbol Ctrl. Type Function PS/B Digital Pad Supply Voltage for Domain B DDPB Connect decoupling capacitors to adjacent pin pairs as close as possible to the pins.
Page 582: Dedicated Pins
Dedicated Pins Dedicated Pins Most of the input/output or control signals of the functional the XC2200 are realized as alternate functions of pins of the parallel ports. There is, however, a number of signals that use separate pins, including the oscillator, special control signals and, of course, the power supply.
Page 583 While the on-chip EVVRs DDIM DDI1 provide the power for the core logic of the XC2200 these pins connect the EVVRs to their external buffer capacitors. For external supply, the core voltage is applied to these pins. The respective pairs should be decoupled as close to the pins as possible.
Page 584 DDPA DDPB digital logic of the XC2200. Each power domain (DMP_A and DMP_B) can be supplied with an arbitrary voltage within the specified supply voltage range (please refer to the corresponding Data Sheets). These pins supply the output drivers as well as the on-chip EVVRs ( ), except for external core voltage supply.
Page 585: The External Bus Controller Ebc
XC2200 Derivatives System Units (Vol. 1 of 2) The External Bus Controller EBC The External Bus Controller EBC All external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external...
Page 586 XC2200 Derivatives System Units (Vol. 1 of 2) The External Bus Controller EBC The five register sets (FCONCSx/TCONCSx/ADDRSELx, x = 7, 4, 3, 2, 1) define five independent “address windows”, whereas all external accesses outside these windows are controlled via registers FCONCS0 and TCONCS0. Chip Select signals CS0 … CS4 and their associated programmable address windows belong to access to resources on the external bus.
Page 587: External Bus Signals
XC2200 Derivatives System Units (Vol. 1 of 2) The External Bus Controller EBC External Bus Signals The External Bus uses the following I/O signals Table 9-1 EBC Bus Signals Signal Port Description Pins Signals available both in the 100-pin and 144-pin package Address Latch Enable;...
Page 588: Timing Principles
XC2200 Derivatives System Units (Vol. 1 of 2) The External Bus Controller EBC Table 9-2 Write Configurations (see Chapter 9.3.2) Written Byte General Write Configuration Separated Byte Low/High Writes High ADDR[0] WRL ADDR[0] – – inactive don’t care 0/1 inactive...
Page 589 XC2200 Derivatives System Units (Vol. 1 of 2) The External Bus Controller EBC 9.2.1.1 Demultiplexed Bus During demultiplexed access, the address and data signals exists on the bus in parallel. Phases ADDR, CS Valid Read DATA Valid Programmable 0 - 3 1 - 2...
Page 590 XC2200 Derivatives System Units (Vol. 1 of 2) The External Bus Controller EBC 9.2.1.2 Multiplexed Bus During time multiplexed access, the address and data signals share the same external lines. Phases ADDR, CS Valid RD DATA Address Valid Data In...
Page 591: Bus Cycle Phases
XC2200 Derivatives System Units (Vol. 1 of 2) The External Bus Controller EBC 9.2.2 Bus Cycle Phases This chapter provides a detail description of each phase of an external memory bus access cycle. 9.2.2.1 A Phase - CS Change Phase The A phase can take 0-3 clocks.
Page 592 XC2200 Derivatives System Units (Vol. 1 of 2) The External Bus Controller EBC 9.2.2.6 F Phase - Address/Write Data Hold Phase The F phase is at the end of an access. It can take 0-3 clocks. Addresses and write data are held while the command is inactive. The number of wait states inserted during the F phase is independently programmable for read and write accesses.
Page 593: Bus Cycle Examples: Fastest Access Cycles
XC2200 Derivatives System Units (Vol. 1 of 2) The External Bus Controller EBC 9.2.3 Bus Cycle Examples: Fastest Access Cycles The fastest possible bus cycle in a system depends also on the pad timing. Therefore, the number of required cycles for a bus access depends on the current system frequency.
Page 594 XC2200 Derivatives System Units (Vol. 1 of 2) The External Bus Controller EBC ADDR, CS Valid Muxed Address Out / Addr. Valid Data Valid Data In MCT05380 Figure 9-8 Fastest Read Cycle Multiplexed Bus ADDR, CS Valid Muxed Addr. Address Out /...
Page 595: Functional Description
XC2200 Derivatives System Units (Vol. 1 of 2) The External Bus Controller EBC Functional Description The following section describes the EBC registers and their settings. 9.3.1 Configuration Register Overview There are 3 groups of EBC registers: • EBC mode registers influencing the global functions.
Page 596 XC2200 Derivatives System Units (Vol. 1 of 2) The External Bus Controller EBC 00EE8E ADDRSEL7 00EE4E CS7 Channel Control FCONCS7 00EE4A TCONCS7 00EE48 ADDRSEL4 00EE36 CS4 Channel Control FCONCS4 00EE32 TCONCS4 00EE30 ADDRSEL3 00EE2E CS3 Channel Control FCONCS3 00EE2A TCONCS3...
Page 597 XC2200 Derivatives System Units (Vol. 1 of 2) The External Bus Controller EBC Table 9-3 EBC Memory Table (ordered by physical address) Name Physical Description Reset Address Value EBCMOD0 EE00 EBC Mode Register 0 5000 EBCMOD1 EE02 EBC Mode Register 1...
Page 598: The Ebc Mode Register 0
XC2200 Derivatives System Units (Vol. 1 of 2) The External Bus Controller EBC 9.3.2 The EBC Mode Register 0 EBCMODe Register 0 EBCMOD0 EBC Mode Register 0 XSFR (EE00 /--) Reset Value: 5000 CSPEN SAPEN Field Bits Type Description RDYPOL...
Page 599 XC2200 Derivatives System Units (Vol. 1 of 2) The External Bus Controller EBC Field Bits Type Description CSPEN [7:4] CSx Pins Enable (only external CSx) 0000 All external Chip Select pins disabled. 0001 CS0 pin enabled 0010 CS1 and CS0 pin enabled …...
Page 600 XC2200 Derivatives System Units (Vol. 1 of 2) The External Bus Controller EBC 9.3.3 The EBC Mode Register 1 EBC MODe register 1 controls the general use of port pins for external bus. EBCMOD1 EBC Mode Register 1 XSFR (EE02...
Page 601: The Timing Configuration Registers Tconcsx
XC2200 Derivatives System Units (Vol. 1 of 2) The External Bus Controller EBC 9.3.4 The Timing Configuration Registers TCONCSx The timing control registers are used to program the described cycle timing for the different access phases (see Section 9.2.2). The timing control registers may be reprogrammed during code fetches from the affected address window.
Page 602 XC2200 Derivatives System Units (Vol. 1 of 2) The External Bus Controller EBC Field Bits Type Description [1:0] Phase A 0 clock cycles … … 3 clock cycles (default) TCONCSx (x = 1-4) Timing Cfg. Reg. for CSx XSFR (EE10...
Page 603 XC2200 Derivatives System Units (Vol. 1 of 2) The External Bus Controller EBC Field Bits Type Description [1:0] Phase A 0 clock cycles … … 3 clock cycles Note: The register TCONCS4 controls the chip select CS4, that is available only in the 144-pin package.
Page 604: The Function Configuration Registers Fconcsx
XC2200 Derivatives System Units (Vol. 1 of 2) The External Bus Controller EBC 9.3.5 The Function Configuration Registers FCONCSx The Function Control registers are used to control the bus and READY functionality for a selected address window. It can be distinguished between 8 and 16-bit bus and multiplexed and demultiplexed accesses.
Page 605 XC2200 Derivatives System Units (Vol. 1 of 2) The External Bus Controller EBC FCONCSx (x = 1-4) Function Cfg. Reg. for CSx XSFR (EE12 + x*8/--) Reset Value: 0000 BTYP Field Bits Type Description BTYP [5:4] Bus Type Selection 8 bit Demultiplexed...
Page 606 XC2200 Derivatives System Units (Vol. 1 of 2) The External Bus Controller EBC FCONCS7 Function Cfg. Reg. for CS7 XSFR (EE4A /--) Reset Value: 0027 BTYP Field Bits Type Description BTYP [5:4] Bus Type Selection 16 bit Demultiplexed RDYMOD Ready Mode...
Page 607: The Address Window Selection Registers Addrselx
The enabled register sets FCONCSx/TCONCSx/ADDRSELx (x = 1 … 4, 7) define separate address areas within the address space of the XC2200. Within each of these address areas the conditions of external accesses and LXBus accesses (x = 7) can be User’s Manual...
Page 608 XC2200 Derivatives System Units (Vol. 1 of 2) The External Bus Controller EBC controlled separately, whereby the different address areas (windows) are defined by the ADDRSELx registers. Each ADDRSELx register cuts out an address window, where the corresponding parameters of the registers FCONCSx and TCONCSx are used to control external accesses.
Page 609 XC2200 Derivatives System Units (Vol. 1 of 2) The External Bus Controller EBC 9.3.6.3 Address Window Arbitration For each external access the EBC compares the current address with all address select registers (programmable ADDRSELx and hard wired address select registers for startup memory) of enabled windows.
Page 610: Ready Controlled Bus Cycles
XC2200 Derivatives System Units (Vol. 1 of 2) The External Bus Controller EBC 9.3.7 Ready Controlled Bus Cycles In cases, where the response (access) time of a peripheral is not constant, or where the programmable wait states are not enough, the EBC provides external bus cycles that are terminated via a READY input signal.
Page 611 READY inactive a little late, after the first sample point of the XC2200, the controller samples an active READY and terminates the current bus cycle too early. By inserting predefined wait states the first READY sample point can be shifted to a time, where the peripheral has safely controlled the READY line.
Page 612: External Bus Arbitration
The XC2200 supports multi master systems on the external bus by its external bus arbitration. This bus arbitration allows an external master to request the external bus. The XC2200 will release the external bus and will float the data, address bus, and control lines.
Page 613 Figure 9-13 Releasing the Bus by the Arbitration Master Note: Figure 9-13 shows the first possibility for BREQ to get active. The XC2200 will complete the currently running bus cycle before granting the external bus as indicated by the broken lines.
Page 614 Note: The falling BREQ edge shows the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the XC2200 requesting the bus. 9.3.8.3 Arbitration Slave Scheme If the EBC is configured as arbitration slave it is by default not owner of the external bus and has to request the bus first.
Page 615 9.3.8.5 Direct Master Slave Connection If one XC2200 is configured as master and the other as slave and both are working on the same external bus as bus master, they can be connected directly together for bus arbitration as shown in Figure 9-15.
Page 616: Shutdown Control
XC2200 Derivatives System Units (Vol. 1 of 2) The External Bus Controller EBC 9.3.9 Shutdown Control In case of a shutdown request from the SCU the EBC ensures that all the different functions of the EBC are in a non-active state before the whole chip is switched to a power save mode.
Page 617: Lxbus Access Control And Signal Generation
XC2200 Derivatives System Units (Vol. 1 of 2) The External Bus Controller EBC LXBus Access Control and Signal Generation Access control to the LXBus is required for the on-chip peripherals MultiCAN and USIC. For these accesses, CS7 and its fixed control registers ADDRSEL7, TCONCS7, and FCONCS7 are used.
Page 618: Startup Configuration And Bootstrap Loading
Software Reset Request: SCU_SWRSTCON.SWRSTREQ = 1. There is a differentiation of XC2200 behavior in case of Application reset which must be noted: • an Application reset triggered by hardware request (for example WDT, ESRx) does not cause evaluation of the P10 pins - the same start-up configuration is used as after the previous reset;...
Page 619: Device Status After Start-Up
2) x means that the level on the corresponding pin is irrelevant. 10.2 Device Status after Start-Up The main parameters of XC2200-status at the point of time when the first user instruction is executed are summarized below. 10.2.1 Registers modified by the Start-Up Procedure...
Page 620 XC2200 Derivatives System Units (Vol. 1 of 2) Startup Configuration and Bootstrap Loading Table 10-2 XC2200 Registers installed by the Start-Up Procedure Register Value Comments 1. After any start-up: TRAPDIS 009F All SCU-controlled traps disabled except PET and RAT RSTCON1...
Page 621: System Frequency
10.2.3 Watchdog Timer handling The Watchdog Timer (WDT) in XC2200 is always enabled by the start-up procedure and configured to generate Application Reset. Therefore, the user software must: •...
Page 622: Start-Up Error State
Start-up Error state To prevent possible negative consequences for the device and/or the system, upon unrecoverable error during startup XC2200 is put onto a stable, passive and neutral to the external world state - power-save mode with DMP_1 shut down and DMP_M powered with 1V.
Page 623: Special Start-Up Features
System Units (Vol. 1 of 2) Startup Configuration and Bootstrap Loading 10.3 Special Start-up Features XC2200 supports some special features, which allow the user software to influence the device start-up, providing additional functionality next to the above (in Chapter 10.1) described.
Page 624 XC2200 Derivatives System Units (Vol. 1 of 2) Startup Configuration and Bootstrap Loading STMEM0 Start-up Memory 0 Register ESFR (F0A0 Reset Value: 0000 10 9 8 7 6 5 USSET FNOP RINDP RINDS RINPS CSOE STAT Field Bits Typ Description...
Page 625: Support For Power-Saving Modes
XC2000 Programmer’s Guide. One rule regarding power-system handling in XC2200 is: if a power-state is entered with DMP_1 supply below the minimum value at which the Flash is operable, this state must be exited only by power-on (wake-up from power-save mode) but not by a functional reset.
Page 626 XC2200 Derivatives System Units (Vol. 1 of 2) Startup Configuration and Bootstrap Loading the memories in which the parity will be activated (refer to STMEM0-description Figure 10-1). – trigger application reset to cause a new device start-up During this new device start-up the RAMs are initialized as requested in STMEM0[13:11].
Page 627 XC2200 Derivatives System Units (Vol. 1 of 2) Startup Configuration and Bootstrap Loading Power-On or Functional reset Device Startup Parity will be used ? Parity Preparation SCU_STMEM0[15] = 0 ? Yes RAM Initialization has not been requested Power-on – SCU_RSTSTAT1.ST1 = 11...
Page 628: Internal Start
2 pins. 10.5 External Start When external start mode is configured, the XC2200 begins executing code out of an off-chip memory (first instruction from location 00’0000 ), connected to the XC2200’s external bus interface.
Page 629 XC2200 Derivatives System Units (Vol. 1 of 2) Startup Configuration and Bootstrap Loading Table 10-3 EBC Configuration: EBC Mode EBC Startup Mode Cfg. Pins Pins Used by the EBC P10[10:8] P2.0 … P2.2, P10.0 … P10.15 8-Bit Data, Multiplexed P0.0 … P0.7, P1.0 … P1.7, P2.0 … P2.2, 8-Bit Data, Demultiplexed P10.0 …...
Page 630: Specific Settings
XC2200 Derivatives System Units (Vol. 1 of 2) Startup Configuration and Bootstrap Loading 10.5.1 Specific Settings When the XC2200 has entered External Start mode, the configuration is automatically set: according to Table 10-6 Table 10-7. Note, that the startup procedure does not configure any address window within ADDRSELx registers.
Page 631: Bootstrap Loading
Startup Configuration and Bootstrap Loading 10.6 Bootstrap Loading Bootstrap Loading is the technique of transferring code to the XC2200 via a certain interface (usually serial) before the regular code execution out of non-volatile program memory commences. Instead, the XC2200 executes the previously received code.
Page 632 DISWDT to allow for an extended download period. The XC2200 will start executing out of user memory as externally configured after a non- BSL reset .
Page 633: Bootstrap Loaders Using Uart Protocol
Figure 10-2 Bootstrap Loader Sequence The XC2200 scans the RxD line to receive a zero byte after entering UART BSL mode and the respective initialization. The zero byte is considered as containing one start bit, eight 0 data bits and one stop bit. From the duration of this zero byte it calculates the corresponding baudrate factor with respect to the current CPU clock, initializes the serial interface U0C0 accordingly and switches pin TxD to output.
Page 634 XC2200 Derivatives System Units (Vol. 1 of 2) Startup Configuration and Bootstrap Loading Once the identification byte is transmitted, the BSL enters a loop to receive 32 bytes via U0C0. These bytes are stored sequentially into locations E0’0000 through E0’001F the internal PSRAM and then executed.
Page 635 XC2200 Derivatives System Units (Vol. 1 of 2) Startup Configuration and Bootstrap Loading Specific Settings The following configuration is automatically set when the XC2200 has entered Standard UART BSL mode: Table 10-8 Standard UART BSL-Specific State Item Value Comments U0C0_CCR...
Page 636 The initial steps of this bootloader are the same as of the Standard UART Bootstrap Loader. XC2200 first scans the RxD line to receive a zero byte, i.e. one start bit, eight 0 data bits and one stop bit. From the duration of this zero byte it calculates the corresponding baudrate factor with respect to the current CPU clock, initializes the serial interface U0C0 accordingly and switches pin TxD to output.
Page 637 0020 P2.4 is input with pull-up (RxD) The identification byte identifies the device to be booted. XC2200 is the first microcontroller family supporting Enhanced UART BSL mode, the code defined for it is Note: The identification byte does not directly identify a specific derivative. This information can, in this case, be obtained from the identification registers.
Page 638 The calculation of the serial baudrate for U0C0 from the length of the first zero byte that is received, allows the operation of the bootstrap loader of the XC2200 with a wide range of baudrates. However, the upper and lower limits have to be kept, in order to ensure proper data transfer.
Page 639 XC2200 Derivatives System Units (Vol. 1 of 2) Startup Configuration and Bootstrap Loading The minimum baudrate (B Figure 10-3) is determined by the maximum count capacity of bitfield PDIV, when measuring the zero byte, i.e. it depends on the system clock.
Page 640: Synchronous Serial Channel Bootstrap Loader
EEPROM via channel 0 of USIC0 (U0C0) into the PSRAM. The XC2200 is the master, so no additional elements (except for the EEPROM) are required. The SSC bootstrap loading is a convenient way for initial and basic (go/fail) testing during software development - it allows many various code-versions to be easy started on the target system by re-programming a serial EEPROM.
Page 641 Startup Configuration and Bootstrap Loading 10.6.3.1 Supported EEPROM Types The XC2200’s SSC bootstrap loader assumes an SPI-compatible EEPROM (25xxx series). It supports devices with 8-bit addressing as well as with 16-bit addressing. The connected EEPROM type is determined by examining the received header bytes, as...
Page 642 XC2200 Derivatives System Units (Vol. 1 of 2) Startup Configuration and Bootstrap Loading 10.6.3.2 Specific Settings When the XC2200 has entered the SSC BSL mode, the following configuration is automatically set: Table 10-11 SSC BSL-Specific State Item Value Comments U0C0_CCR...
Page 643: Can Bootstrap Loader
The first BSL task is to determine the CAN baud rate at which the external host is communicating. Therefore the external host must send initialization frames continuously to the XC2200. The first two data bytes of the initialization frame must include a 2-byte baud rate detection pattern (5555...
Page 644 In the data transmission phase, data frames are sent by the external host and received by the XC2200. The data frames use the 11-bit data message identifier DMSGID that has been sent with the initialization frame. Eight data bytes are transmitted with each data frame.
Page 645 Data length code, 8 bytes within CAN frame Data bytes Data bytes, assigned to increasing destination 0 to 7 (PSRAM) addresses 10.6.4.1 Specific Settings When the XC2200 has entered the CAN BSL mode, the following configuration is automatically set: Table 10-13 CAN BSL-Specific State Item Value Comments...
Page 646: Summary Of Bootstrap Loader Modes
XC2200 Derivatives System Units (Vol. 1 of 2) Startup Configuration and Bootstrap Loading 10.6.5 Summary of Bootstrap Loader Modes This table summarizes the external hardware provisions that are required to activate a bootstrap loader in a system. Table 10-14 Configuration Data for Bootstrap Loader Modes...
Page 647: Debug System
(Figure 11-1). The break interface supports very low latency triggers between XC2200 and tool and/or system environment if needed. The memory mapped OCDS registers are accessible via the JTAG interface using Cerberus. In addition there is a limited set of special Cerberus debug IO instructions.
Page 648: Debug Interface
XC2200 Derivatives System Units (Vol. 1 of 2) Debug System OCDS System Features • Hardware, software and external pin breakpoints • Reaction on break with CPU-Halt, monitor call, data transfer and external signal • Read/write access to the whole address space •...
Page 649: Routing Of Debug Signals
IO pins as possible. In the XC2200, these signals are only provided as alternate functions (no dedicated pins). To minimize the impact caused by the debug interface pins, these signals can be mapped to several pins.
Page 650 XC2200 Derivatives System Units (Vol. 1 of 2) Debug System Field Bits Type Description DPRTDI [3:2] Debug Pin Routing for TDI P5.2 P10.10 P7.2 P8.3 DPRTMS [5:4] Debug Pin Routing for TMS P5.4 P10.11 P7.3 P8.4 DPRTCK [7:6] Debug Pin Routing for TCK P2.9...
Page 651: Ocds Module
XC2200 Derivatives System Units (Vol. 1 of 2) Debug System 11.2 OCDS Module The application of the OCDS Module is to debug the user software running on the CPU in the customer’s system. This is done with an external debugger that controls the OCDS...
Page 652: Debug Events
XC2200 Derivatives System Units (Vol. 1 of 2) Debug System Debug Event Sources Debug Actions Hardware HALT the CPU Triggers Programmable Combination Debug CALL a Monitor Event Processing Transfer Triggered SBRK Instruction Break_Out Pin Activated Break_In Pin Activated MCB05389 Figure 11-2 OCDS Concept: Block Diagram 11.2.1...
Page 653 XC2200 Derivatives System Units (Vol. 1 of 2) Debug System SBRK Instruction This is a mechanism through which the software can explicitly generate a debug event. It can be used for instance by a debugger to temporarily patch code held in RAM in order to implement Software Breakpoints.
Page 654: Debug Actions
• to inject an instruction to the Core - using this mechanism, an arbitrary instruction can be injected into the XC2200 pipeline Halt Mode Upon this Action the OCDS Module sends a Break-Request to the Core.
Page 655: Cerberus
(via the Debug Interface), the OCDS Module and the internal system of XC2200. Features • JTAG interface is used as control and data channel • Generic memory read/write functionality (RW mode) with access to the whole address space •...
Page 656 XC2200 Derivatives System Units (Vol. 1 of 2) Debug System The access to any memory location is performed with injected instructions, as PEC transfer. The following Cerberus IO Instructions can be used in their generic meaning: • IO_READ_WORD, IO_WRITE_WORD • IO_READ_BLOCK, IO_WRITE_BLOCK •...
Page 657: Boundary-Scan
Debug System 11.4 Boundary-Scan The XC2200 eases board-level analysis in the application system by providing Boundary-Scan according to the IEEE standard 1149.1. It supports testing of the interconnections between several devices mounted on a PCB. Boundary-Scan is accomplished via the JTAG module, using standard JTAG instructions (IEEE1149.1).
Page 658: Instruction Set Summary
Grouping the various instruction into classes aids in identifying similar instructions (e.g. SHR, ROR) and variations of certain instructions (e.g. ADD, ADDB). This provides an easy access to the possibilities and the power of the instructions of the XC2200. Note: The used mnemonics refer to the detailed description.
Page 659 XC2200 Derivatives System Units (Vol. 1 of 2) Instruction Set Summary Table 12-3 Compare and Loop Control Instructions Comparison of two words or bytes: CMPB Comparison of two words with post-increment by CMPI1 CMPI2 either 1 or 2: Comparison of two words with post-decrement by...
Page 660 XC2200 Derivatives System Units (Vol. 1 of 2) Instruction Set Summary Table 12-7 Data Movement Instructions Standard data movement of a word or byte: MOVB Data movement of a byte to a word location with either MOVBS MOVBZ sign or zero byte extension:...
Page 661 XC2200 Derivatives System Units (Vol. 1 of 2) Instruction Set Summary Table 12-10 Call Instructions Conditional calling of an either absolutely or indirectly CALLA CALLI addressed subroutine within the current code segment: Unconditional calling of a relatively addressed CALLR –...
Page 662 DISWDT instruction in WDT compatibility mode): Instruction PWRDN is used to enter Power Down mode in previous 16-bit architectures. In the XC2200 devices, however, PWRDN has no effect and is executed like a NOP instruction.
Page 663 – Protected Instructions Some instructions of the XC2200 which are critical for the functionality of the controller are implemented as so-called Protected Instructions. These protected instructions use the maximum instruction format of 32 bits for decoding, while the regular instructions only use a part of it (e.g.
Page 664: Device Specification
AC characteristics like timing characteristics and requirements. Other than the architecture, the instruction set, or the basic functions of the XC2200 core and its peripherals, these DC and AC characteristics are subject to changes due to device improvements or specific derivatives of the standard device.
Page 665 XC2200 Derivatives System Units (Vol. 1 of 2) Device Specification DDPB P3.7 DDPB P0.7 TESTM P7.2 P10.7 P8.4 P3.6 TRST P10.6 P8.3 P0.6 P7.0 P3.5 P7.3 P10.5 P8.2 P3.4 P7.1 P10.4 P7.4 P3.3 P8.1 P0.5 P8.0 P10.3 P2.10 DDIM P6.0 P3.2...
Page 666 XC2200 Derivatives System Units (Vol. 1 of 2) Device Specification DDPB P0.7 DDPB TESTM P10.7 P7.2 P10.6 TRST P0.6 P7.0 P10.5 P7.3 P10.4 P7.1 P0.5 P7.4 P10.3 P2.10 DDIM P6.0 TRef P6.1 LQFP-100 DDI1 P0.4 P6.2 P10.2 DDPA P15.0 P0.3 P10.1...
Page 667 Keyword Index Keyword Index This section lists a number of keywords which refer to specific details of the XC2200 in terms of its architecture, its functional units or functions. This helps to quickly find the answer to specific questions about the XC2200.
Page 668 XC2200 Derivatives System Units (Vol. 1 of 2) Keyword Index MOFGPRnL 20-93 [2] Switching 5-34 [1] MOIPRnH 20-87 [2] Count direction 14-6 [2], 14-36 [2] MOIPRnL 20-87 [2] Counter 14-20 [2], 14-45 [2] MSIDk 20-60 [2] Counter Mode (GPT1) 14-10 [2], 14-40 [2]...
Page 669 XC2200 Derivatives System Units (Vol. 1 of 2) Keyword Index Frequency output signal 6-20 [1] OCDS Requests 5-39 [1] Gated timer mode (GPT1) 14-9 [2] Gated timer mode (GPT2) 14-39 [2] PEC 2-10 [1], 5-20 [1] GPT 2-20 [1] Latency 5-40 [1]...
Page 670 XC2200 Derivatives System Units (Vol. 1 of 2) Keyword Index Registers Protocol interrupts 19-120 [2] T14 15-8 [2] Protocol registers 19-123 [2] T14REL 15-8 [2] Pulse shaping 19-118 [2] Receive buffer 19-122 [2] Signals 19-111 [2] Segmentation 4-37 [1] Sync-break detection 19-122 [2]...
Page 671 XC2200 Derivatives System Units (Vol. 1 of 2) Keyword Index Frame and word length 19-188 [2] FMRH 19-69 [2] Mode control 19-188 [2] FMRL 19-68 [2] Protocol interrupts 19-196 [2], INPRH 19-33 [2] 19-197 [2] INPRL 19-32 [2] Protocol overview 19-186 [2]...
Page 672 XC2200 Derivatives System Units (Vol. 1 of 2) Keyword Index Mode control 19-19 [2] Module registers USIC0_IDH 19-207 [2] USIC0_IDL 19-206 [2] USIC1_IDH 19-207 [2] USIC1_IDL 19-206 [2] USIC2_IDH 19-207 [2] USIC2_IDL 19-206 [2] Output signals 19-7 [2] Protocol control and status 19-18 [2]...
Page 673 System Units (Vol. 1 of 2) Register Index Register Index This section lists the registers of the XC2200. This helps to quickly find the reference to the description of the respective register. This User’s Manual consists of two Volumes, “System Units” and “Peripheral Units”. For your convenience this register index refers to both volumes, so you can immediately find the reference to the desired section in the corresponding document ([1] or [2]).
Page 674 XC2200 Derivatives System Units (Vol. 1 of 2) Register Index CAN_MSPNDkL 20-59 [2] CCU6x_PISELL 18-106 [2] CAN_NBTRxH 20-72 [2] CCU6x_PSLR 18-82 [2] CAN_NBTRxL 20-72 [2] CCU6x_T12 18-32 [2] CAN_NCRx 20-62 [2] CCU6x_T12DTC 18-35 [2] CAN_NECNTxH 20-73 [2] CCU6x_T12MSEL 18-40 [2]...
Page 675 XC2200 Derivatives System Units (Vol. 1 of 2) Register Index GPT12E_T2CON 14-15 [2] Pn_OUT 7-9 [1] GPT12E_T3CON 14-4 [2] Pn_POCON 7-7 [1] GPT12E_T4CON 14-15 [2] Ports GPT12E_T5,-T6 14-57 [2] Pn_IN 7-12 [1] GPT12E_T5/6IC 14-58 [2] Pn_IOCRx 7-13 [1] GPT12E_T5CON 14-41 [2]...
Page 676 XC2200 Derivatives System Units (Vol. 1 of 2) Register Index T14REL 15-8 [2] UxCy_OUTRH 19-107 [2] T2, T3, T4 14-30 [2] UxCy_OUTRL 19-107 [2] T2/3/4IC 14-31 [2] UxCy_PCRH 19-34 [2], 19-126 [2], T2CON 14-15 [2] 19-153 [2], 19-178 [2], 19-200 [2]...
Page 677 . i n f i n e o n . c o m B158-H9132-G1-X-7600 Published by Infineon Technologies AG...

Infineon Technologies XC2200 User Manual

Summary of Chapters

Table of Contents

1 Introduction

2 Architectural Overview

3 Memory Organization

4 Central Processing Unit (CPU)

5 Interrupt and Trap Functions

6 System Control Unit (SCU)

7 Parallel Ports

8 Dedicated Pins

9 The External Bus Controller EBC

10 Startup Configuration and Bootstrap Loading

11 Debug System

12 Instruction Set Summary

13 Device Specification

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Summary of Contents for Infineon Technologies XC2200