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Infineon Technologies TC1796 User Manual

Infineon Technologies TC1796 User Manual

32-bit single-chip microcontroller

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U s e r ' s M a nu a l , V2 . 0 , J u l y 2 0 0 7

TC1796

3 2 - B i t S i n g l e - C h i p M i c ro c o n t r o ll e r

V o l u m e 1 ( o f 2 ) : S y s t e m U n i ts

V o l u m e 2 ( o f 2 ): P e r i p h e r a l U n i t s

M i c r o c o n t r o l l e rs

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Page 1 U s e r ’ s M a nu a l , V2 . 0 , J u l y 2 0 0 7 TC1796 3 2 - B i t S i n g l e - C h i p M i c ro c o n t r o ll e r...
Page 2 Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life.
Page 3 U s e r ’ s M a nu a l , V2 . 0 , J u l y 2 0 0 7 TC1796 3 2 - B i t S i n g l e - C h i p M i c ro c o n t r o ll e r...
Page 4 Page Subjects (major changes since last revision) TC1796 User’s Manual Version 2.0 includes the contents of the TC1796 Documentation Addendum, V1.2, Apr. 2007. Furthermore, the complete document and especially the register description have been updated to allow document-automation processes based on XML technologies.
Page 5 TC1796 System and Peripheral Units (Vol. 1 and 2) TC1796 User’s Manual Volume 1 (of 2) System Units & Volume 2 (of 2) Peripheral Units Revision History: V2.0, 2007-07 Figure 6-2 is updated. 6-7, DBCU_ID and PBCU_ID are added. Bit description of is updated.
Page 6 TC1796 System and Peripheral Units (Vol. 1 and 2) TC1796 User’s Manual Volume 1 (of 2) System Units & Volume 2 (of 2) Peripheral Units Revision History: V2.0, 2007-07 12-99 Address range for AEN21 is updated. 12-111, MCHK_ID is added.
Page 7 TC1796 System and Peripheral Units (Vol. 1 and 2) TC1796 User’s Manual Volume 1 (of 2) System Units & Volume 2 (of 2) Peripheral Units Revision History: V2.0, 2007-07 22-58, 22-59, CAN_ID register is added. 22-61 22-60 Figure 22-24 is updated.
Page 8 FADC_ID register is added. 26-29 Trademarks TriCore® is a trademark of Infineon Technologies AG. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document.
Page 9: Table Of Contents
1.2.1 TC1796 Block Diagram ........1-9 [1] 1.2.2...
Page 10 Trap System ......... . 2-8 [1] TC1796 CPU Subsystem Registers ......2-9 [1] 2.4.1...
Page 11 TC1796 System and Peripheral Units (Vol. 1 and 2) Table of Contents 2.7.2.4 Store Instruction Timing ....... 2-51 [1] Floating Point Pipeline Timings .
Page 12 5.1.3.3 States of TC1796 Units in Power Management Modes ..5-7 [1] Configuration Input Sampling ....... 5-8 [1] External Request Unit (ERU) .
Page 13 TC1796 System and Peripheral Units (Vol. 1 and 2) Table of Contents 5.10.2 MSC Emergency Control Selection ......5-58 [1] 5.10.3...
Page 14 TC1796 System and Peripheral Units (Vol. 1 and 2) Table of Contents 6.5.4.2 Signal Status Triggers ....... . 6-29 [1] 6.5.4.3...
Page 15 TC1796 System and Peripheral Units (Vol. 1 and 2) Table of Contents 7.2.10.1 Power Supply ........7-38 [1] 7.2.10.2...
Page 16 TC1796 System and Peripheral Units (Vol. 1 and 2) Table of Contents 10.2.5 Emergency Stop Register ......10-16 [1] 10.2.6...
Page 17 TC1796 System and Peripheral Units (Vol. 1 and 2) Table of Contents 10.9.1 Port 6 Configuration ........10-59 [1] 10.9.2...
Page 18 TC1796 System and Peripheral Units (Vol. 1 and 2) Table of Contents Peripheral Control Processor (PCP) ..... . . 11-1 [1] 11.1...
Page 19 TC1796 System and Peripheral Units (Vol. 1 and 2) Table of Contents 11.6.2 Channel Watchdog ........11-39 [1] 11.6.3...
Page 20 TC1796 System and Peripheral Units (Vol. 1 and 2) Table of Contents 11.11.9 CLR, Clear Bit ........11-83 [1] 11.11.10...
Page 21 Implementing Multiply Algorithms ..... . . 11-123 [1] 11.14 Implementation of the PCP in the TC1796 ....11-125 [1] 11.14.1 PCP Memories .
Page 22 TC1796 System and Peripheral Units (Vol. 1 and 2) Table of Contents 12.1.9.2 Pattern Detection for 8-bit Data Width ....12-36 [1] 12.1.9.3...
Page 23 TC1796 System and Peripheral Units (Vol. 1 and 2) Table of Contents 13.3.3.2 Sole Master Arbitration Mode ......13-10 [1] 13.3.3.3...
Page 24 TC1796 System and Peripheral Units (Vol. 1 and 2) Table of Contents 13.9 Burst Mode Read Accesses ......13-65 [1] 13.9.1...
Page 25 Interrupt Vector Table ........14-15 [1] 14.8 Usage of the TC1796 Interrupt System ..... . 14-18 [1] 14.8.1 Spanning Interrupt Service Routines Across Vector Entries .
Page 26 TC1796 System and Peripheral Units (Vol. 1 and 2) Table of Contents 16.4.2.1 Time-Out Mode ........16-8 [1] 16.4.2.2...
Page 27 TC1796 System and Peripheral Units (Vol. 1 and 2) Table of Contents 17.3.3 Concurrent Debugging ....... . . 17-11 [1] 17.4...
Page 28 TC1796 System and Peripheral Units (Vol. 1 and 2) Table of Contents Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) ..19-1 [2] 19.1 ASC Kernel Description ........19-1 [2] 19.1.1...
Page 29 TC1796 System and Peripheral Units (Vol. 1 and 2) Table of Contents 20.1.2.7 Receive FIFO Operation ......20-14 [2] 20.1.2.8...
Page 30 TC1796 System and Peripheral Units (Vol. 1 and 2) Table of Contents 21.2 MSC Kernel Registers ........21-36 [2] 21.2.1...
Page 31 TC1796 System and Peripheral Units (Vol. 1 and 2) Table of Contents 22.3.4 Suspend Mode ........22-22 [2] 22.3.5...
Page 32 TC1796 System and Peripheral Units (Vol. 1 and 2) Table of Contents 22.5.3.1 Local Time and Synchronization Marks ....22-115 [2] 22.5.3.2 Time Marks ........22-116 [2] 22.5.3.3...
Page 33 TC1796 System and Peripheral Units (Vol. 1 and 2) Table of Contents 22.9.3.1 Clock Control Registers ......22-202 [2] 22.9.4...
Page 34 Receiver Interrupt Registers ......23-117 [2] 23.5 Implementation of the MLI0/MLI1 in TC1796 ....23-124 [2] User’s Manual L-26 V2.0, 2007-07...
Page 35 TC1796 System and Peripheral Units (Vol. 1 and 2) Table of Contents 23.5.1 Interfaces of the MLI Modules ......23-124 [2] 23.5.2...
Page 36 TC1796 System and Peripheral Units (Vol. 1 and 2) Table of Contents 24.2.6.2 PDL-Algorithm ........24-121 [2] 24.2.6.3...
Page 37 TC1796 System and Peripheral Units (Vol. 1 and 2) Table of Contents 24.6.3.3 Pad Driver Characteristics Selection ....24-253 [2] 24.6.3.4 Emergency Control of GPTA Output Ports Lines ..24-255 [2] 24.6.4...
Page 38 TC1796 System and Peripheral Units (Vol. 1 and 2) Table of Contents 25.1.8.4 Load Capacitance ........25-42 [2] 25.1.9...
Page 39 TC1796 System and Peripheral Units (Vol. 1 and 2) Table of Contents 26.1.1 Analog Inputs ......... 26-4 [2] 26.1.1.1...
Page 40: System Units (Vol. 1 Of 2)
This TC1796 User’s Manual describes the features of the TC1796 with respect to the TriCore Architecture. Where the TC1796 directly implements TriCore architectural functions, this manual simply refers to those functions as features of the TC1796. In all cases where this manual describes a TC1796 feature without referring to the TriCore Architecture, this means that the TC1796 is a direct implementation of the TriCore Architecture.
Page 41 System Units (Vol. 1 of 2) Introduction • Functional units of the TC1796 are given in plain UPPER CASE. For example: “The EBU provides an interface to external peripherals”. • Pins using negative logic are indicated by an overline. For example: “The external reset pin, HDRST, has a dual function.”.
Page 42: Reserved, Undefined, And Unimplemented Terminology
Certain bit combinations in a bit field can be marked “Reserved”, Reserved indicating that the behavior of the TC1796 is undefined for that combination of bits. Setting the register to such undefined bit or bit field combinations may lead to unpredictable results. Such bit combinations are reserved.
Page 43: Register Access Modes
TC1796 System Units (Vol. 1 of 2) Introduction 1.1.4 Register Access Modes Read and write access to registers and memory locations are sometimes restricted. In memory and register access tables, the terms as defined in Table 1-2 are used. Table 1-2...
Page 44: Abbreviations And Acronyms
TC1796 System Units (Vol. 1 of 2) Introduction 1.1.5 Abbreviations and Acronyms The following acronyms and termini are used in this document: Alternate Boot Mode Analog-to-Digital Converter AGPR Address General Purpose Register Arithmetic and Logic Unit Asynchronous/Synchronous Serial Controller Bus Control Unit BROM Boot ROM &...
Page 45 TC1796 System Units (Vol. 1 of 2) Introduction Floating Point Unit GPIO General Purpose Input/Output General Purpose Register GPTA General Purpose Timer Array ICACHE Instruction Cache Input / Output LDRAM Local Data RAM Local Memory-to-FPI Bus Interface Local Memory Bus...
Page 46 TC1796 System Units (Vol. 1 of 2) Introduction SBCU System Peripheral Bus Control Unit SBRAM Stand-by Data Memory System Control Unit Special Function Register System Peripheral Bus SPRAM Scratch-Pad RAM SRAM Static Data Memory Service Request Node Synchronous Serial Controller...
Page 47: System Architecture Of The Tc1796
Analog-to-Digital converters. Within the TC1796, all these peripheral units are connected to the TriCore CPU/system via two Flexible Peripheral Interconnect (FPI) Buses. Several I/O lines on the TC1796 ports are reserved for these peripheral units to communicate with the external world.
Page 48: Tc1796 Block Diagram
TC1796 System Units (Vol. 1 of 2) Introduction 1.2.1 TC1796 Block Diagram Figure 1-1 shows the block diagram of the TC1796. SPRAM: Scratch-Pad RAM 56 KB LDRAM TriCore 48 KB SPRAM ICACHE: Instruction cache (TC1M) 16 KB ICACHE LDRAM Local data RAM...
Page 49: Features
TC1796 System Units (Vol. 1 of 2) Introduction 1.2.2 Features The TC1796 has the following features: High-performance 32-Bit CPU • 32-bit architecture with 4 Gbyte unified data, program, and input/output address space • Fast automatic context-switching • Multiply-accumulate unit •...
Page 50 TC1796 System Units (Vol. 1 of 2) Introduction – 16 Kbyte Instruction Cache (ICACHE) – 16 Kbyte Boot ROM (BROM) • Data memory – 64 Kbyte Data Memory (SRAM) – 16 Kbyte data memory (SBRAM) for standby operation during power-down –...
Page 51 TC1796 System Units (Vol. 1 of 2) Introduction • DMA Controller operates as bus bridge between System Peripheral Bus and Remote Peripheral Bus Parallel I/O Ports • 127 digital General-Purpose Input/Output (GPIO) port lines • Input/output functionality individually programmable for each port line •...
Page 52 Two Flexible Peripheral Interconnect Buses (FPI Bus) for on-chip interconnections and its FPI Bus control units (SBCU, RBCU). • The System Timer (STM) with high-precision, long-range timing capabilities. • The TC1796 includes a power management system, a watchdog timer as well as reset logic. User’s Manual 1-13 V2.0, 2007-07...
Page 53: On-Chip Peripheral Units Of The Tc1796
The TC1796 microcontroller offers several versatile on-chip peripheral units such as serial controllers, timer units, and Analog-to-Digital converters. Several I/O lines on the TC1796 ports are reserved for these peripheral units to communicate with the external world. The peripherals mentioned in this overview section are all described in detail in the chapters of the “TC1796 Peripheral Units (Vol.
Page 54: Asynchronous/Synchronous Serial Interfaces
MCB05574 Figure 1-2 General Block Diagram of the ASC Interface The ASC provides serial communication between the TC1796 and other microcontrollers, microprocessors, or external peripherals. The ASC supports full-duplex asynchronous communication and half-duplex synchronous communication. In Synchronous Mode, data is transmitted or received synchronous to a shift clock that is generated by the ASC internally.
Page 55 TC1796 System Units (Vol. 1 of 2) Introduction Features • Full-duplex asynchronous operating modes – 8-bit or 9-bit data frames, LSB first – Parity-bit generation/checking – One or two stop bits – Baud rate from 4.69 MBaud to 1.12 Baud (@ 75 MHz clock) –...
Page 56: High-Speed Synchronous Serial Interfaces
TC1796 System Units (Vol. 1 of 2) Introduction 1.3.1.2 High-Speed Synchronous Serial Interfaces Figure 1-3 shows a global view of the Synchronous Serial Interface (SSC). MRSTA MRSTB Master MTSR MTSR Clock Control MTSRA MTSRB Slave MRST MRST Address Port SCLKA...
Page 57 TC1796 System Units (Vol. 1 of 2) Introduction – Programmable clock polarity: Idle low or idle high state for the shift clock – Programmable clock/data phase: Data shift with leading or trailing edge of the shift clock • Baud rate generation from 37.5 MBaud to 572.2 Baud (@ 75 MHz module clock) •...
Page 58: Micro Second Channel Interfaces
TC1796 System Units (Vol. 1 of 2) Introduction 1.3.1.3 Micro Second Channel Interfaces The Micro Second Channel (MSC) interfaces provide serial communication links typically used to connect power switches or other peripheral devices. The serial communication link includes a fast synchronous downstream channel and a slow asynchronous upstream channel.
Page 59 TC1796 System Units (Vol. 1 of 2) Introduction Features • Fast synchronous serial interface to connect power switches in particular, or other peripheral devices via serial buses • High-speed synchronous serial transmission on downstream channel – Serial output clock frequency: –...
Page 60: Multican Controller
TC1796 System Units (Vol. 1 of 2) Introduction 1.3.1.4 MultiCAN Controller The MultiCAN module contains four independent CAN nodes, representing four serial communication interfaces. MultiCAN Module Kernel TXDC3 RXDC3 Clock Node 3 Control TXDC2 Message RXDC2 Object Node 2 Linked...
Page 61 TC1796 System Units (Vol. 1 of 2) Introduction The message objects are organized in double-chained linked lists, where each CAN node has its own list of message objects. A CAN node stores frames only into message objects that are allocated to the message object list of the CAN node, and it transmits only messages belonging to this message object list.
Page 62 TC1796 System Units (Vol. 1 of 2) Introduction – List reorganizations can be performed at any time, even during full operation of the CAN nodes. – A powerful, command-driven list controller manages the organization of the list structure and ensures consistency of the list.
Page 63: Micro Link Serial Bus Interface
TC1796 System Units (Vol. 1 of 2) Introduction 1.3.1.5 Micro Link Serial Bus Interface The Micro Link Interface is a fast synchronous serial interface that makes it possible to exchange data between microcontrollers of the 32-bit AUDO microcontroller family without intervention of a CPU or other bus masters.
Page 64 TC1796 System Units (Vol. 1 of 2) Introduction Figure 1-7 shows a general block diagram of the MLI Module. TREADY[D:A] TVALID[D:A] Fract . TDATA Divider Transmitter Control TCLK Port BRKOUT MLI Module ML I Control RCLK[D:A] SR[7:0] RREADY[D:A] Move RVALID[D:A]...
Page 65: General Purpose Timer Array
System Units (Vol. 1 of 2) Introduction 1.3.2 General Purpose Timer Array The TC1796 contains two General Purpose Timer Arrays (GPTA0 and GPTA1) with identical functionality, plus an additional Local Timer Cell Array (LTCA2). Figure 1-8 shows a global view of the GPTA modules.
Page 66: Functionality Of Gpta0 And Gpta1
TC1796 System Units (Vol. 1 of 2) Introduction 1.3.2.1 Functionality of GPTA0 and GPTA1 Each of the General Purpose Timer Arrays (GPTA0 and GPTA1) provides a set of hardware modules required for high-speed digital signal processing: • Filter and Prescaler Cells (FPC) support input noise filtering and prescaler operation.
Page 67 TC1796 System Units (Vol. 1 of 2) Introduction • Duty Cycle Measurement (DCM) – Four independent units – 0 - 100% margin and time-out handling – maximum resolution GPTA – /2 maximum input signal frequency GPTA • Digital Phase Locked Loop (PLL) –...
Page 68: Functionality Of Ltca2
TC1796 System Units (Vol. 1 of 2) Introduction I/O Sharing Unit • Interconnecting inputs and outputs from internal clocks, FPC, GTC, LTC, ports, and MSC interface 1.3.2.2 Functionality of LTCA2 • 64 Local Timer Cells (LTCs) – Three basic operating modes (Timer, Capture and Compare) for 63 units –...
Page 69: Analog-To-Digital Converters
1.3.3.1 Analog-to-Digital Converters (ADC0 and ADC1) The two on-chip ADC modules of the TC1796 are analog-to-digital converters with 8-bit, 10-bit, or 12-bit resolution including sample & hold functionality. The A/D converters operate by the method of successive approximation. A multiplexer selects up to 32 analog inputs that can be connected to the 16 conversion channels in each ADC module.
Page 70 TC1796 System Units (Vol. 1 of 2) Introduction AGND AREF EMUX0 EMUX0 EMUX1 Port EMUX1 Control GRPS GRPS Clock Control AIN0 Group 0 AIN15 Address Decoder AIN16 Module Group 1 Kernel AIN31 SR[7:0] Interrupt Control ASGT SW0TR, SW0GT External ETR, EGT...
Page 71: Fast Analog-To-Digital Converter Unit (Fadc)
System Units (Vol. 1 of 2) Introduction 1.3.3.2 Fast Analog-to-Digital Converter Unit (FADC) The on-chip FADC module of the TC1796 is primarily a four-channel A/D converter with 10-bit resolution that operates by the method of successive approximation. Features • Extreme fast conversion, 21 cycles of...
Page 72 TC1796 System Units (Vol. 1 of 2) Introduction As shown in Figure 1-10, the main FADC functional blocks are: • The Input Stage – contains the differential inputs and the programmable amplifier • The A/D Converter – is responsible for the analog-to-digital conversion •...
Page 73: Tc1796 Pin Definitions And Functions
TC1796 System Units (Vol. 1 of 2) Introduction TC1796 Pin Definitions and Functions Figure 1-11 shows the logic symbol of the TC1796. TSTRES D[31:0] TESTMODE A[23:0] HDRST General Control Chip PORST External Bus Select Unit Interface Control BYPASS BFCLKI XTAL1...
Page 74: Tc1796 Pin Configuration
FAGND DDMF COMB SCLK MTSR HOLD MR/W N.C. AN37 AN39 AN43 AN29 AN31 P4.6 P4.9 P4.10 P4.14 N.C. CLKI CLKO AGND0 FAREF SSMF MCA05584 Figure 1-12 TC1796 Pinning for P-BGA-416 Package (top view) User’s Manual 1-35 V2.0, 2007-07 Intro, V2.0...
Page 75 TC1796 System Units (Vol. 1 of 2) Introduction Table 1-3 Pin Definitions and Functions Symbol Pins I/O Pad Power Functions Driver Supply Class External Bus Interface (EBU) D[31:0] EBU Data Bus Lines DDEBU The EBU Data Bus Lines D[31:0] serve as external data bus.
Page 76 TC1796 System Units (Vol. 1 of 2) Introduction Table 1-3 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Power Functions Driver Supply Class A[23:0] EBU Address Bus Lines A[23:0] DDEBU The EBU Address Bus Lines serve as external address bus.
Page 77 TC1796 System Units (Vol. 1 of 2) Introduction Table 1-3 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Power Functions Driver Supply Class BFCLKO AF25 Burst Mode Flash Clock Output (non- DDEBU differential) BFCLKI AF24 Burst Mode Flash Clock Input...
Page 78 The states of the Port 0 pins are latched into the software configuration input register SCU_SCLIR at the rising edge of HDRST. In the different TC1796 device versions several Port 0 pins are reserved for device configuration purposes (see Page 10-25).
Page 79 TC1796 System Units (Vol. 1 of 2) Introduction Table 1-3 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Power Functions Driver Supply Class I/O A1/A2 Port 1 Port 1 is a 16-bit bi-directional general- purpose I/O port which can be alternatively used for the MLI0 interface or as external trigger input lines.
Page 80 TC1796 System Units (Vol. 1 of 2) Introduction Table 1-3 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Power Functions Driver Supply Class I/O A1/A2 Port 2 Port 2 is a 14-bit bi-directional general- purpose I/O port which can be used alternatively for the six upper SSC slave select outputs or for GPTA I/O lines.
Page 81 TC1796 System Units (Vol. 1 of 2) Introduction Table 1-3 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Power Functions Driver Supply Class Port 3 Port 3 is a 16-bit bi-directional general- purpose I/O port which can be alternatively used for GPTA I/O lines.
Page 82 TC1796 System Units (Vol. 1 of 2) Introduction Table 1-3 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Power Functions Driver Supply Class A1/A2 Port 4 Port 4 is a 16-bit bi-directional general- purpose I/O port which can be alternatively used for GPTA I/O lines.
Page 83 TC1796 System Units (Vol. 1 of 2) Introduction Table 1-3 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Power Functions Driver Supply Class I/O A2 Port 5 Port 5 is an 8-bit bi-directional general- purpose I/O port which can be alternatively used for ASC0/1 or MSC0/1 lines.
Page 84 TC1796 System Units (Vol. 1 of 2) Introduction Table 1-3 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Power Functions Driver Supply Class I/O A2 Port 6 Port 6 is a 12-bit bi-directional general- purpose I/O port which can be alternatively used for SSC1, ASC0/1, and CAN I/O lines.
Page 85 TC1796 System Units (Vol. 1 of 2) Introduction Table 1-3 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Power Functions Driver Supply Class I/O A1 Port 7 Port 7 is a 8-bit bi-directional general- purpose I/O port which can be alternatively used as external trigger input lines and for ADC0/1 external multiplexer control.
Page 86 TC1796 System Units (Vol. 1 of 2) Introduction Table 1-3 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Power Functions Driver Supply Class I/O A1/A2 Port 8 Port 8 is an 8-bit bi-directional general- purpose I/O port which can be alternatively used for the MLI1 interface or as GPTA I/O lines.
Page 87 TC1796 System Units (Vol. 1 of 2) Introduction Table 1-3 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Power Functions Driver Supply Class I/O A2 Port 9 Port 9 is a 9-bit bi-directional general- purpose I/O port which can be alternatively used as GPTA or MSC0/1 I/O lines.
Page 88 TC1796 System Units (Vol. 1 of 2) Introduction Table 1-3 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Power Functions Driver Supply Class – Hardware Configuration Inputs / Port 10 These inputs are boot mode (hardware configuration) control inputs. They are latched with the rising edge of HDRST.
Page 89 TC1796 System Units (Vol. 1 of 2) Introduction Table 1-3 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Power Functions Driver Supply Class MSC Outputs LVDS MSC Clock and Data Outputs FCLP0A MSC0 differential driver clock output positive A...
Page 90 TC1796 System Units (Vol. 1 of 2) Introduction Table 1-3 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Power Functions Driver Supply Class Analog Inputs AN[43:0] – ADC Analog Input Port The ADC Analog Input Port provides 44 analog input lines for the A/D converters ADC0, ADC1, and FADC.
Page 91 TC1796 System Units (Vol. 1 of 2) Introduction Table 1-3 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Power Functions Driver Supply Class – ADC Analog Input Port (cont’d) AN32 Analog input 32 AN33 Analog input 33 AN34 Analog input 34...
Page 92 NMI inputs are switched off. TEST – Test Mode Select Input MODE For normal operation of the TC1796, this pin should be connected to high level. TSTRES G24 – Test Reset Input For normal operation of the TC1796, this pin must be connected to low level.
Page 93 TC1796 System Units (Vol. 1 of 2) Introduction Table 1-3 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Power Functions Driver Supply Class N.C. – – – Not Connected These pins are reserved for future extension and should not be connected externally.
Page 94 TC1796 System Units (Vol. 1 of 2) Introduction Table 1-3 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Power Functions Driver Supply Class – – – EBU Power Supply (2.3 - 3.3 V) DDEBU AC18 AC22 – – –...
Page 95 TC1796 System Units (Vol. 1 of 2) Introduction 1) In order to minimize noise coupling to the on-chip A/D converters, it is recommended to use these pins as less as possible in strong driver mode. 2) In case of a power-fail condition (one or more power supply voltages drop below the specified voltage range), an undefined output driving level may occur at these pins.
Page 96: Pad Driver Classes Overview
System Units (Vol. 1 of 2) Introduction 1.4.2 Pad Driver Classes Overview Table 1-5 gives a overview of the pad driver classes of the TC1796. Further details can be found in the “TC1796 Data Sheet“. Table 1-5 Pad Driver and Input Classes Overview Class Power...
Page 97: Pull-Up/Pull-Down Behavior Of The Pins
TC1796 System Units (Vol. 1 of 2) Introduction 1.4.3 Pull-Up/Pull-Down Behavior of the Pins Table 1-6 List of Pull-Up/Pull-Down Reset Behavior of the Pins Pins PORST = 0 PORST = 1 TSTRES, Weak pull-up device active TDI, TMS, TESTMODE, BRKOUT, BRKIN,...
Page 98: Cpu Subsystem
CPU Subsystem CPU Subsystem The TC1796 processor contains a TriCore 1 V1.3 CPU. This chapter describes the implementation-specific options of the CPU, and should be read in conjunction with the TriCore 1 Architecture Manual, which describes the complete TriCore Architecture including the register and instruction set description.
Page 99: Central Processing Unit Features
TC1796 System Units (Vol. 1 of 2) CPU Subsystem Central Processing Unit Features The 150 MHz TriCore TC1796 CPU includes: Architecture • 32-bit load/store architecture • 4 Gbyte address range (2 • 16-bit and 32-bit instructions for reduced code size •...
Page 100: Cpu Diagram
TC1796 System Units (Vol. 1 of 2) CPU Subsystem • Optional Memory Management instruction set not implemented (Memory management configuration registers are always read as MMU not present) 2.2.1 CPU Diagram The Central Processing Unit (CPU) is comprised of an Instruction Fetch Unit, an Execution Unit, a General Purpose Register File (GPR), a CPU Slave interface (CPS), and optional Floating Point Unit (FPU).
Page 101: Instruction Fetch Unit
TC1796 System Units (Vol. 1 of 2) CPU Subsystem 2.2.2 Instruction Fetch Unit The Instruction Fetch Unit pre-fetches and aligns incoming instructions from the 64-bit wide Program Memory Interface (PMI). The Issue Unit directs the instruction to the appropriate pipeline. The Instruction Protection Unit checks the validity of accesses to the PMI and also checks for instruction breakpoint conditions.
Page 102: Execution Unit
TC1796 System Units (Vol. 1 of 2) CPU Subsystem 2.2.3 Execution Unit The Execution Unit contains the Integer Pipeline, the Load/Store Pipeline and the Loop Pipeline. The Integer Pipeline and Load/Store Pipeline have four stages: Fetch, Decode, Execute, and Write-back. The Execute stage may extend beyond one cycle to accommodate multi-cycle operations such as load instructions.
Page 103: General Purpose Register File
TC1796 System Units (Vol. 1 of 2) CPU Subsystem 2.2.4 General Purpose Register File The CPU has a General Purpose Register (GPR) file, divided into an Address Register File (registers A0 through A15) and a Data Register File (registers D0 through D15).
Page 104: Implementation-Specific Features
2.3.3 Reset System Several events can cause the TC1796 system to be reset. The CPU does not differ in its behavior on reset. The status register RST_SR allows the CPU to determine which event caused the reset. Refer to Chapter 4 of this TC1796 User’s Manual.
Page 105: Interrupt System
CPU Subsystem 2.3.5 Interrupt System An interrupt request can be generated by the TC1796 on-chip peripheral units, or it can be generated by external events. Requests can be targeted to either the CPU, or to the Peripheral Control Processor (PCP).
Page 106: Tc1796 Cpu Subsystem Registers
This section only describes the implementation-specific features of the registers listed in Table 2-1. For complete descriptions of all registers, please refer to the TriCore 1 Architecture Manual. TC1796 implementation-specific CPU registers are referred directly in this section. Table 2-1 CPU and Processor Subsystem Registers Registers...
Page 107: Core Special Function Registers (Csfr)
TC1796 System Units (Vol. 1 of 2) CPU Subsystem 2.4.1 Core Special Function Registers (CSFR) Program State Context Stack Information Management Management Registers Registers Registers Interrupt & Trap PCXI Control Registers System Control Registers Identification Register SYSCON CPU_ID MMUCON MCA05590_mod...
Page 108: Implementation-Specific Core Special Function Registers
TC1796 System Units (Vol. 1 of 2) CPU Subsystem 2.4.1.1 Implementation-specific Core Special Function Registers This section describes the implementation-specific Program Status Word (PSW) which is an extension of the PSW description in the TriCore 1 Architecture Manual. The PSW status flags used for FPU operations overlay the status flags used for Arithmetic Logic Unit (ALU) operations of the CPU.
Page 109 TC1796 System Units (Vol. 1 of 2) CPU Subsystem In the TC1796, the MMU_CON register indicates the non-availability of the TriCore 1’s memory management unit (bit MXT is always set). MMU_CON MMU Configuration Register (F7E18000 Reset Value: 0000 8000 Field...
Page 110: Cpu Slave Interface (Cps) Registers
2.4.2 CPU Slave Interface (CPS) Registers In the TC1796, the CPU Slave Interface (CPS) of the TriCore CPU directly accesses the interrupt service request registers in the CPU from the TC1796 System Peripheral Bus. The CPS registers are described in detail in the TriCore 1 Architecture Manual - Core Registers.
Page 111: Implementation-Specific Cpu Slave Interface Registers
2.4.2.1 Implementation-specific CPU Slave Interface Registers All registers from Table 2-3 have a TC1796-specific implementation detail, the Type of Service Control (TOS) bit/bit field. CPU_SBSRC0 is described on Page 2-19. The non- shaded areas in the CPU_SRCn register description defines the implementation-specific bits/bit fields.
Page 112: Cpu General Purpose Registers
TC1796 System Units (Vol. 1 of 2) CPU Subsystem 2.4.3 CPU General Purpose Registers Address General Data General Purpose Registers Purpose (AGPR) Registers (DGPR) A15 (implicit address) D15 (implicit data) A11 (return address) A10 (stack pointer) A9 (global address) A8 (global address)
Page 113 TC1796 System Units (Vol. 1 of 2) CPU Subsystem Table 2-4 GPR Registers (cont’d) Register Short Register Long Name Address Name Data Register 11 F7E1 FF2C Data Register 12 F7E1 FF30 Data Register 13 F7E1 FF34 Data Register 14 F7E1 FF38...
Page 114: Core Debug Registers
System Units (Vol. 1 of 2) CPU Subsystem 2.4.4 Core Debug Registers In the TC1796, several Core Debug registers are available for debug purposes. These Core Debug registers are described in detail in the TriCore 1 Architecture Manual chapter - Core Debug Controller. Core Debug...
Page 115: Implementation-Specific Core Debug Registers
TC1796 System Units (Vol. 1 of 2) CPU Subsystem 2.4.4.1 Implementation-specific Core Debug Registers This section describes the implementation-specific Core Debug Registers which differ from the description in the TriCore 1 Architecture Manual. These are: • Trigger Event 0 Specifier Register •...
Page 116 TC1796 System Units (Vol. 1 of 2) CPU Subsystem CPU_SBSRC0 CPU Software Breakpoint Service Request Control Register 0 (F7E0 FFBC Reset Value: 0000 0000 SRR SRE SRPN Field Bits Type Description Type of Service Control Service Provider = CPU Reserved Reserved Read as 0;...
Page 117: Memory Protection Registers
Set 0 and Set 1, which specify memory protection ranges and permissions for code and data. Set 2 and Set 3 are not implemented in the TC1796. The PSW.PRS bit field determines which of these sets is currently in use by the CPU.
Page 118 TC1796 System Units (Vol. 1 of 2) CPU Subsystem Table 2-6 Memory Protection Registers Register Register Long Name Address Short Name DPR0_0L Data Segment Protection Register Set 0, Range 0, F7E1 C000 Lower Boundary DPR0_0U Data Segment Protection Register Set 0, Range 0,...
Page 119 TC1796 System Units (Vol. 1 of 2) CPU Subsystem Table 2-6 Memory Protection Registers (cont’d) Register Register Long Name Address Short Name CPR0_0L Code Segment Protection Register Set 0, Range 0, F7E1 D000 Lower Boundary CPR0_0U Code Segment Protection Register Set 0, Range 0,...
Page 120: Implementation-Specific Memory Protection Registers
Field Bits Type Description [31:16] r Reserved Read as 0; should be written with 0. These bits refer to code memory ranges 2 and 3, which are are not available in the TC1796. User’s Manual 2-23 V2.0, 2007-07 CPU, V2.0...
Page 121: Program Memory Interface (Pmi)
TC1796 System Units (Vol. 1 of 2) CPU Subsystem Program Memory Interface (PMI) Program Memory Interface (PMI) PMEM To/From 16 KB Data Switch ICACHE & Data Alignment & Interface Control 48 KB SPRAM Control Registers Parity Control/Check Slave Master PLMB Interface...
Page 122: Parity Protection For Pmi Memories
2.5.2 Parity Protection for PMI Memories In the TC1796, the PMI memory blocks SPRAM, ICACHE, and Tag RAM are equipped with a parity error detection logic that makes it possible to detect parity errors separately for SPRAM/ICACHE or the ICACHE Tag RAM. In case of a parity error a NMI is generated.
Page 123: Pmi Registers
TC1796 System Units (Vol. 1 of 2) CPU Subsystem 2.5.3 PMI Registers Three control registers are implemented in the Program Memory Interface. These registers and their bits are described in this section. Module Identification Control Registers Register PMI_ID PMI_CON0 PMI_CON1...
Page 124: Pmi Module Identification Register
TC1796 System Units (Vol. 1 of 2) CPU Subsystem 2.5.3.1 PMI Module Identification Register PMI_ID PMI Module Identification Register (F87FFD08 Reset Value: 000B C0XX 16 15 MODNUM MODTYPE MODREV Field Bits Type Description MODREV [7:0] Module Revision Number MODREV defines the module revision number. The value of a module revision starts with 01 (first revision).
Page 125: Pmi Control Register 0
TC1796 System Units (Vol. 1 of 2) CPU Subsystem 2.5.3.2 PMI Control Register 0 PMI_CON0 PMI Control Register 0 (F87FFD10 Reset Value: 0000 0002 Field Bits Type Description CC2SPR Code Cache Memory to SPR This bit is used for cache test mode purposes.
Page 126: Pmi Control Register 1
TC1796 System Units (Vol. 1 of 2) CPU Subsystem 2.5.3.3 PMI Control Register 1 PMI_CON1 PMI Control Register 1 (F87FFD14 Reset Value: 0000 0000 Field Bits Type Description CCINV Code Cache Invalidate Normal code cache (ICACHE) operation All cache lines are invalidated As long as CCINV is set, all instruction fetch accesses generate a cache refill.
Page 127: Pmi Control Register 2
PCSZ [1:0] Program Cache Size This bit field indicates the ICACHE size and TAGRAM configuration of the PMI. The TC1796 has a fixed ICACHE size of 16 Kbyte. Therefore, PCSZ is always read as 11 16 Kbyte cache PMEMSZ [6:4]...
Page 128: Data Memory Interface (Dmi)
TC1796 System Units (Vol. 1 of 2) CPU Subsystem Data Memory Interface (DMI) Data Memory Interface (DMI) DMEM 8 KB Data Switch DPRAM & Data Alignment & To/From Interface Control 56 KB Remote LDRAM Periphera Interface Control Registers (RPB) Parity...
Page 129: Dual-Ported Memory Operation
TC1796 System Units (Vol. 1 of 2) CPU Subsystem 2.6.2 Dual-Ported Memory Operation The dual-ported memory (DPRAM) allows the CPU and Remote Peripheral Bus (RPB) masters to access the same memory locations simultaneously, reading or writing invalid data without conflict. In the case of simultaneous accesses to the same address, the CPU has a higher priority than the RPB master.
Page 130: Parity Protection For Dmi Memories
2.6.3 Parity Protection for DMI Memories In the TC1796, the LDRAM and DPRAM memory blocks of the DMI are equipped with a parity error detection logic that makes it possible to detect parity errors separately for LDRAM or DPRAM. In case of a parity error a NMI is generated.
Page 131: Dmi Registers
TC1796 System Units (Vol. 1 of 2) CPU Subsystem 2.6.4 DMI Registers Two control registers and two trap flag registers are implemented in the DMI. These registers and their bits are described in this section. Module Identification Control Registers Trap Flag Registers...
Page 132: Dmi Register Description
TC1796 System Units (Vol. 1 of 2) CPU Subsystem 2.6.4.1 DMI Register Description The DMI Module Identification Register ID contains read-only information about the DMI module version. DMI_ID DMI Module Identification Register (F87FFC08 Reset Value: 0008 C0XX 16 15 MODNUM...
Page 133 Type Description DCSZ [1:0] Data Cache Size This bit field indicates the DMI data cache configuration. In the TC1796 no data cache is available, therefore DCSZ is always read as 00 No cache available DMEMSZ [6:4] Data Memory Size This bit field indicates the DMI data memory size.
Page 134 Field Bits Type Description DC2SPR Cache Test Mode Enable This bit must always be written with 0. Setting to 1 will have no effect in TC1796. [31:1] Reserved Returns 0 when read; should be written with 0. User’s Manual 2-37 V2.0, 2007-07...
Page 135 TC1796 System Units (Vol. 1 of 2) CPU Subsystem The DMI Synchronous Trap Flag Register, DMI_STR, holds the flags that identify the root cause of a Data-access Synchronous Bus Error (DSE). Reading DMI_STR in supervisor mode returns the register contents and then clears its contents. Reading DMI_STR in user mode returns the contents of the register but does not clear its contents.
Page 136 TC1796 System Units (Vol. 1 of 2) CPU Subsystem The DMI Asynchronous Trap Flag Register, DMI_ATR, holds the flags that inform about the root cause of a Data Access Asynchronous Bus Error (ASE). Reading DMI_ATR in supervisor mode returns the register contents and then clears its contents. Reading DMI_ATR in user mode returns the contents of the register but does not clear its contents.
Page 137: Instruction Timing
TC1796 System Units (Vol. 1 of 2) CPU Subsystem Instruction Timing This section gives information on instruction timing by execution unit. The Integer Pipeline and Load/Store Pipeline are always present, and the Floating Point Unit (FPU) is optional. The Load/Store unit implements the optional TLB instructions.
Page 138: Integer-Pipeline Instructions
TC1796 System Units (Vol. 1 of 2) CPU Subsystem 2.7.1 Integer-Pipeline Instructions 2.7.1.1 Simple Arithmetic Instruction Timings Each instruction is single issued. Table 2-10 Simple Arithmetic Instruction Timing Instruction Result Repeat Instruction Result Repeat Latency Rate Latency Rate Integer Pipeline Arithmetic Instructions MAX.H...
Page 139 TC1796 System Units (Vol. 1 of 2) CPU Subsystem Table 2-10 Simple Arithmetic Instruction Timing (cont’d) Instruction Result Repeat Instruction Result Repeat Latency Rate Latency Rate CSUB SUBS.H CSUBN SUBS.HU SUBS.U MAX.B SUBX MAX.BU Compare Instructions LT.B EQ.B LT.BU EQ.H LT.H...
Page 140 TC1796 System Units (Vol. 1 of 2) CPU Subsystem Table 2-10 Simple Arithmetic Instruction Timing (cont’d) Instruction Result Repeat Instruction Result Repeat Latency Rate Latency Rate AND.GE.U OR.NE AND.LT OR.NOR.T AND.LT.U OR.OR.T AND.NE OR.T AND.NOR.T AND.OR.T ORN.T AND.T XNOR ANDN XNOR.T...
Page 141 TC1796 System Units (Vol. 1 of 2) CPU Subsystem Table 2-10 Simple Arithmetic Instruction Timing (cont’d) Instruction Result Repeat Instruction Result Repeat Latency Rate Latency Rate SH.NAND.T Coprocessor 0 Instructions BMERGE DVINIT.WS BSPLIT DVINIT.WU DVADJ DVSTEP.S DVINIT DVSTEP.U DVINIT.U IXMAX DVINIT.B...
Page 142: Multiply Instruction Timings
TC1796 System Units (Vol. 1 of 2) CPU Subsystem 2.7.1.2 Multiply Instruction Timings Each instruction is single issued. Table 2-11 Multiple Instruction Timing Instruction Result Repeat Instruction Result Repeat Latency Rate Latency Rate IP Arithmetic Instructions MUL.H MUL.U MUL.Q 1/2/3...
Page 143: Mac Instruction Timings
TC1796 System Units (Vol. 1 of 2) CPU Subsystem 2.7.1.3 MAC Instruction Timings Each instruction is single issued. Table 2-12 MAC Instruction Timing Instruction Result Repeat Instruction Result Repeat Latency Rate Latency Rate IP Arithmetic Instructions MADD MSUB MADD.U MSUB.U...
Page 144: Control Flow Instruction Timing
TC1796 System Units (Vol. 1 of 2) CPU Subsystem For MADD.Q, MADDS.Q, MSUB.Q, MSUBS.Q Instructions: Result Latency Repeat Rate 16 × 16 16 × 32 32 × 32 2.7.1.4 Control Flow Instruction Timing Note all Integer Pipeline Control flow instructions are conditional.
Page 145: Load-Store Pipeline Instructions
TC1796 System Units (Vol. 1 of 2) CPU Subsystem 2.7.2 Load-Store Pipeline Instructions 2.7.2.1 Address Arithmetic Timing Each instruction is single issued. Table 2-14 Address Arithmetic Instruction Timing Instruction Result Repeat Instruction Result Repeat Latency Rate Latency Rate LS Arithmetic Instructions ADD.A...
Page 146: Control Flow Instruction Timing
TC1796 System Units (Vol. 1 of 2) CPU Subsystem 2.7.2.2 Control Flow Instruction Timing • Each instruction is single issued. • All targets yield a full instruction in one access (not 16-bits of a 32-bit instruction). • All code fetches take a single cycle.Timing is best case; no cache misses for context operations, no pending stores.
Page 147: Load Instruction Timing
TC1796 System Units (Vol. 1 of 2) CPU Subsystem For JLI, JEQ.A, JNE.A JNZ.A, JZ.A Instructions: Flow Latency Repeat Rate Correctly predicted, not taken Correctly predicted, taken Wrongly predicted 2.7.2.3 Load Instruction Timing Load instructions can produce two results if they use the pre-increment, post-increment, circular or bit-reverse addressing modes.
Page 148: Store Instruction Timing
TC1796 System Units (Vol. 1 of 2) CPU Subsystem 2.7.2.4 Store Instruction Timing Cache and Store instructions similar to Load instructions will have a result for the pre- increment, post-increment, circular or bit-reverse addressing modes, but do not produce a ‘memory’ result.
Page 149: Floating Point Pipeline Timings
TC1796 System Units (Vol. 1 of 2) CPU Subsystem Floating Point Pipeline Timings These instructions are only valid if the optional Floating Point Unit is implemented. • Each instruction is single issued. Table 2-18 Floating Point Instruction Timing Instruction Result...
Page 150: Clock System And Control
• Reduces electromagnetic interference (EMI) by switching off unused modules The clock system must be operational before the TC1796 can function, so it contains special logic to handle power-up and reset operations. Its services are fundamental to the operation of the entire system, so it contains special fail-safe logic.
Page 151 The module clock for these modules is For these modules . Its module clock switched off after reset (module is disabled ). can only be switched on or off (no clock divider ). MCA05599_mod Figure 3-1 TC1796 Clocking System User’s Manual V2.0, 2007-07 Clock, V2.0...
Page 152: Clock Generation Unit
It can execute emergency actions if it loses its lock on the external clock. The Clock Generation Unit (CGU) in the TC1796, shown in Figure 3-2, consists basically of an oscillator circuit and a Phase-Locked Loop (PLL).
Page 153: Main Oscillator Circuit
TC1796 System Units (Vol. 1 of 2) Clock System and Control 3.2.1 Main Oscillator Circuit The oscillator circuit, a Pierce oscillator, is designed to work with both, an external crystal oscillator or an external stable clock source. It basically consists of an inverting amplifier and a feedback element with XTAL1 as input, and XTAL2 as output.
Page 154: Oscillator Bypass Mode
TC1796 System Units (Vol. 1 of 2) Clock System and Control DDOSC DDOSC3 DDOSC DDOSC3 External Clock XTAL1 XTAL1 Signal - 40 4 - 25 TC1796 TC1796 Oscillator Oscillator XTAL2 XTAL2 Fundamental Mode Crystal SSOSC SSOSC 1) in case of PLL bypass 0 MHz...
Page 155: Oscillator Run Detection
The circuit can start without a reset and becomes defined after at least 32 pulses of counter B. Setting bit OSC_CON.ORDRES makes it possible to start the oscillator run detection during normal operation of the TC1796, e.g. in case of a PLL loss-of-lock condition.
Page 156: Oscillator Gain Control
TC1796 System Units (Vol. 1 of 2) Clock System and Control 3.2.1.3 Oscillator Gain Control The oscillator starts with a high drive level (gain) during and after a power-on reset to ensure safe start-up behavior in the beginning (force the crystal oscillation). When a stable oscillation has been reached after oscillation start-up, the gain of the oscillator can be reduced.
Page 157: Oscillator Control Register
TC1796 System Units (Vol. 1 of 2) Clock System and Control 3.2.1.4 Oscillator Control Register Note: Register OSC_CON is Endinit-protected. OSC_CON Oscillator Control Register (F0000018 Reset Value: see Table 3-1 Field Bits Type Description MOSC Main Oscillator Test Mode This bit determines the mode of the main oscillator.
Page 158 TC1796 System Units (Vol. 1 of 2) Clock System and Control Field Bits Type Description ORDRES Oscillator Run Detection Reset This bit allows the oscillator run detection to start during normal operating mode. No operation The oscillator run detection logic is reset and restarted.
Page 159: Phase Looked Loop (Pll) Circuitry
The PLL is a main component of the CGU that is dedicated to generate the CPU and system clock inside the TC1796. The PLL basically converts a low-frequency external clock signal into high-speed internal CPU and system clocks for maximum performance.
Page 160 TC1796 System Units (Vol. 1 of 2) Clock System and Control PLL Mode In PLL Mode, the PLL is running. The VCO clock is derived from , divided by the P factor, multiplied by the PLL (N-Divider). This mode is selected by setting PLL_CLC.VCOBYP = 0.
Page 161: Pll Parameters
TC1796 System Units (Vol. 1 of 2) Clock System and Control 3.2.2.2 PLL Parameters As shown in Equation (3.2) Equation (3.3), the PLL operation depends on the setup of up to four main PLL parameters: P-Divider, N-Divider, K-Divider, and VCO range selection.
Page 162 TC1796 System Units (Vol. 1 of 2) Clock System and Control N-Divider The N-Divider in the feedback path of the PLL divides the VCO clock by factor N for the N-divider output clock . This feedback clock is used as input clock for the PLL phase detection unit, which compares it with the PLL input clock .
Page 163 46.67 46.67 145 31.25 37.5 43.75 1) These KDIV selections are not allowed in PLL Mode of the TC1796. 2) This is a restriction in for odd K-divider factors. CPUmax 3) This is the default value after a power-on reset.
Page 164 TC1796 System Units (Vol. 1 of 2) Clock System and Control VCO Operating Range The VCO can be selected for three operating ranges by programming the PLL_CLC.VCOSEL bit field. Table 3-5 defines the min./max. frequency as well as the VCO base frequency .
Page 165: Pll Clock Control And Status Register
TC1796 System Units (Vol. 1 of 2) Clock System and Control 3.2.2.3 PLL Clock Control and Status Register The PLL Clock Control and Status Register PLL_CLC is located in the address range of the System Control Unit (see Page 5-62). It holds the hardware configuration bits of the PLL and provides the control for the N, P and K-Dividers as well as the PLL lock status bit.
Page 166 TC1796 System Units (Vol. 1 of 2) Clock System and Control Field Bits Type Description VCOSEL [7:6] VCO Range Selection This bit field selects operating range of the VCO. The coding is defined in Table 3-5. KDIV [11:8] PLL K-Divider Selection This bit field selects the K-Divider value.
Page 167: Changing Pll Parameters
VCOBYP can be changed without precautions • PDIV and KDIV can be switched at any time in VCO Bypass Mode. However, the maximum operating frequency of the TC1796 must not be exceeded. • Before changing VCOSEL, the VCO Bypass Mode must be selected.
Page 168: Lock Detection
This is done to avoid unstable operation due to the PLL trying to lock again. The TC1796 remains in the PLL unlocked state until the next power-on reset or a successful lock recovery occurs.
Page 169 TC1796 System Units (Vol. 1 of 2) Clock System and Control 3. If bit OSCR is set, then Select the VCO Bypass Mode (PLL_CLC.VCOBYP = 1) Re-connect the oscillator to the PLL (PLL_CLC.OSCDISC = 0) Set the restart lock detection bit PLL_CLC.RESLD = 1 Wait until the PLL becomes locked (PLL_CLC.LOCK = 1)
Page 170: Power-On Startup Operation
In order to support a wide range of input clock frequencies, the TC1796 requires a generic procedure to start-up the system clock. When the TC1796 is powered up, a low level (0) must be applied to the power-on reset pin, PORST. While PORST is active (at low level), the device is asynchronously held in reset and the state of the BYPASS pin controls the operation of the clock circuitry.
Page 171: Module Power Management And Clock Gating
Clock System and Control Module Power Management and Clock Gating Because power dissipation is related to the frequency of gate transitions, the TC1796 performs power management principally by clock gating – that is, controlling whether the clock is supplied to its various functional units. Gating off the clock to unused functional modules also reduces electro-magnetic interference (EMI) since EMI is related to both the frequency and the number of gate transitions.
Page 172: Module Clock Generation
System Units (Vol. 1 of 2) Clock System and Control 3.3.1 Module Clock Generation As shown in Figure 3-5, module clock generation of the TC1796 on-chip modules have two registers implemented: • Clock Control Register CLC • Fractional Divider Register FDR The following sections describes the general functionality of CLC and FDR.
Page 173: Clock Control Register Clc
TC1796 System Units (Vol. 1 of 2) Clock System and Control 3.3.2 Clock Control Register CLC All CLC registers have basically the same bit and bit field layout. However, not all CLC register functions are implemented for each peripheral unit.
Page 174 TC1796 System Units (Vol. 1 of 2) Clock System and Control Field Bits Type Description SPEN Module Suspend Enable Used for enabling the suspend mode. Module cannot be suspended (suspend is disabled). Module can be suspended (suspend is enabled). This bit can be written only if SBWE is set to 1 during the same write operation.
Page 175 TC1796 begins (or resumes) executing a special debug monitor program. When the application is suspended, a suspend request signal is generated by the TC1796 and sent to all modules. If bit SPEN is set to 1, the operation User’s Manual 3-26 V2.0, 2007-07...
Page 176 TC1796 System Units (Vol. 1 of 2) Clock System and Control of the peripheral module is stopped when the suspend signal is asserted. If SPEN is set to 0, the module does not react to the suspend request signal but continues its normal operation.
Page 177 Note: In all TC1796 modules except MultiCAN and DMA, the only shut down operating mode that is available is the Fast Shut-off ModeTC1796, regardless of the state of the FSOE bit.
Page 178: Fractional Divider Operation
TC1796 System Units (Vol. 1 of 2) Clock System and Control A value of 00 in RMC disables the clock signals to these modules (CLC clock is switched off). If RMC is not equal to 00 , the CLC clock for a unit is generated as (3.4)
Page 179 TC1796 System Units (Vol. 1 of 2) Clock System and Control STEP (10-bit) Fractional Divider Adder & RESULT (10-bit) Enable Debug Suspend Request Reset External Divider Debug Suspend Acknowledge Control Kernel Disable External Clock Enable Request Module Disable Request MCB05604...
Page 180 This output signal makes it possible to control (stop/reset) Divider external divider stages which have as input. Note: In the TC1796, the fractional divider input clock is also referred to as the fractional divider input clock is also referred to as...
Page 181: Fractional Divider Operating Modes
TC1796 System Units (Vol. 1 of 2) Clock System and Control 3.3.3.2 Fractional Divider Operating Modes The fractional divider has two operating modes: • Normal divider mode • Fractional divider mode Normal Divider Mode In normal divider mode (FDR.DM = 01...
Page 182 TC1796 System Units (Vol. 1 of 2) Clock System and Control Fractional Divider Mode When the fractional divider mode is selected (FDR.DM = 10 ), the output clock derived from the input clock by division of a fraction of n/1024 for any value of n from 0 to 1023.
Page 183 TC1796 System Units (Vol. 1 of 2) Clock System and Control Suspend Mode Control The operation of the fractional divider can be controlled by the Debug Suspend Request input. This input is activated in suspend mode by the on-chip debug control logic. In suspend mode, module registers are accessible for read and write actions, but other module internal functions are frozen.
Page 184: Fractional Divider Register
TC1796 System Units (Vol. 1 of 2) Clock System and Control 3.3.3.3 Fractional Divider Register Fractional Divider Register Reset Value: 0000 0000 RESULT STEP Field Bits Type Description STEP [9:0] Step Value In normal divider mode, STEP contains the reload value for RESULT.
Page 185 TC1796 System Units (Vol. 1 of 2) Clock System and Control Field Bits Type Description [13:12] Suspend Control This bit field determines the behavior of the fractional divider in suspend mode (bit SUSREQ and SUSACK set). Clock generation continues. Clock generation is stopped and the clock output signal is not generated.
Page 186 TC1796 System Units (Vol. 1 of 2) Clock System and Control Field Bits Type Description SUSREQ Suspend Mode Request Suspend mode is not requested. Suspend mode is requested. Suspend mode is entered when SUSREQ and SUSACK are set. ENHW Enable Hardware Clock Control...
Page 187 10 sets RESULT to 3FF Implementation FDR registers are implemented for several modules of the TC1796. The name of these FDR registers is always preceded by the module name (e.g. SSC0_FDR is the FDR register for the SSC0 module).
Page 188: Module Clock Register Implementations
– 1) Further info on FDR implementations see Table 3-10. 2) Automatic clock switch-off capability if PCP is idle. Note: The ports of the TC1796, SCU, and WDT do not provide CLC registers. User’s Manual 3-39 V2.0, 2007-07 Clock, V2.0...
Page 189: Fractional Divider Register Implementations
TC1796 System Units (Vol. 1 of 2) Clock System and Control 3.3.5 Fractional Divider Register Implementations Table 3-10 shows the implementations specific differences of the fractional divider functionalities. Table 3-10 FDR Register Implementations FDR Register Suspend Mode Acknowledge ENHW Reset Ext.
Page 190: System Clock Output Control
TC1796 System Units (Vol. 1 of 2) Clock System and Control System Clock Output Control The System Clock SYSCLK (alternate function of GPIO port line P1.12) is generated by a fractional divider block with a subsequent divide-by-2 stage (see Figure 3-10).
Page 191: System Clock Fractional Divider Register
TC1796 System Units (Vol. 1 of 2) Clock System and Control 3.4.1 System Clock Fractional Divider Register SCU_SCLKFDR SCU System Clock Fractional Divider Register (F000000C Reset Value: 0000 0000 RESULT STEP Field Bits Type Description STEP [9:0] Step Value Reload or addition value for RESULT.
Page 192 TC1796 System Units (Vol. 1 of 2) Clock System and Control Field Bits Type Description Reserved [27:26] Read as 0; should be written with 0. Note: This is only a short summary of the fractional divider behavior. The details on the...
Page 193: Reset And Boot Operation
Reset and Boot Overview When the TC1796 device is first powered up, several boot parameters such as the start location of the code have to be defined to enable proper start operation of the device. To...
Page 194 Therefore, activation of the HDRST signal earlier than the maximum Power-on Reset Boot Time must be prevented. Please refer to the maximum Power-on Reset Boot Time defined in the Power, Pad and Reset Timing section of the TC1796 Data Sheet. User’s Manual V2.0, 2007-07...
Page 195: Reset Status And Control Registers
After a reset, the reset status register RST_SR indicates the type of reset which has occurred and which parts of the TC1796 were affected by the last reset operation. RST_SR also holds the state of the boot configuration pins HWCFG[3:0] (Port 10) that have been sampled with the HDRST inactive (low-to-high) transition.
Page 196 TC1796 System Units (Vol. 1 of 2) Reset and Boot Operation Field Bits Type Description HWBRKIN Latched State of BRKIN Input This bit indicates the logical state of the BRKIN input that has been latched at the end of a power-on reset.
Page 197: Reset Request Register
TC1796 System Units (Vol. 1 of 2) Reset and Boot Operation 4.1.1.2 Reset Request Register The reset request register RST_REQ is used to generate a software reset. Unlike the other reset causes, the software reset can exclude functions (System Timer reset and hardware reset (HDRST) generation) from the reset.
Page 198 TC1796 System Units (Vol. 1 of 2) Reset and Boot Operation Field Bits Type Description SWBOOT Software Boot Configuration Selection The previously latched hardware configuration stored in RST_SR.HWCFG is used as boot selection. The software configuration as programmed in bit field SWCFG is used as boot selection.
Page 199: Reset Operations
TC1796 System Units (Vol. 1 of 2) Reset and Boot Operation Reset Operations 4.2.1 Power-On Reset The PORST pin performs a power-on reset, also called cold reset. Driving the PORST pin low causes an asynchronous reset of the entire device. The device then enters its power-on reset sequence.
Page 200: Software Reset
Watchdog Timer Reset A Watchdog Timer overflow or access error occurs only in response to severe and/or unknown malfunctions of the TC1796, either caused by software or hardware errors. Therefore, a Watchdog Timer reset occurs when an overflow of the Watchdog Timer takes place.
Page 201 Watchdog Timer will time out, causing a Watchdog Timer reset. If the TC1796 system is so corrupted that it is chronically unable to service the Watchdog Timer, the danger could arise that the system would be continuously reset every time the Watchdog Timer times out.
Page 202: Debug System Reset
Watchdog Timer reset. However, this time the reset circuitry detects that WDTOE is still set while a Watchdog Timer error has occurred, indicating danger of cyclic resets. The reset circuitry then puts the TC1796 in Reset Lock. This state can only be deactivated again through a power-on reset.
Page 203 TC1796 System Units (Vol. 1 of 2) Reset and Boot Operation Table 4-2 Effect of Reset on Device Functions Module / Function Watchdog Software Hardware Power-On Reset Reset Reset Reset Boot Configuration Bit field Bit fields Bit field Bit field...
Page 204: Booting Scheme
4.2.7 Booting Scheme When the TC1796 is reset, it needs an indication how it has to start after the reset sequence is finished. The TC1796 internal state is usually cleared through a reset, especially in the case of a power-up reset. Thus, boot configuration information needs to be applied by the external hardware through input pins.
Page 205 TC1796 System Units (Vol. 1 of 2) Reset and Boot Operation Table 4-3 TC1796 Boot Selections (cont’d) BRKIN HWCFG Type of Boot Boot ROM Exit [3:0] Jump Address 0100 Start from external memory with EBU as master, A100 0000 using CS0; automatic EBU configuration...
Page 206: Normal Boot Options
System Units (Vol. 1 of 2) Reset and Boot Operation 4.2.7.1 Normal Boot Options The normal boot options are invoked when BRKIN is inactive (at high level). The TC1796 has three options for booting into normal operation: • Starting code execution from external memory •...
Page 207: Debug Boot Options
ABM header. 4.2.7.2 Debug Boot Options The debug boot options are invoked when BRKIN is active (at low level). The TC1796 has three options for booting into debug operation: • Tri-state chip •...
Page 208: Boot Rom
As the original architectural position of the BROM is on the FPI Bus and the boot vector to the Boot ROM is hardwired in the CPU to this location. The internal BROM in the TC1796 is visible from the PMI side at three different locations, as can be seen in the memory map: •...
Page 209 Emulation Support If the device currently used is an emulation device (TC1796ED), a boot capability from emulation memory is supported. For the standard TC1796 this boot option cannot be activated. Test and Stress Routines The 8 Kbyte TestROM is reserved for special routines, which are used for testing, stressing and qualification of the component.
Page 210 TC1796 System Units (Vol. 1 of 2) Reset and Boot Operation TC1796 Reset Operation Flash Ramp-up and Chip Initialization Startup Procedure Checking boot configuration selections: BRKIN pin, HWCFG[3:0] pins, SWOPT[2:0], TESTMODE pin Branch to test modes TESTMODE = 0? (Test ROM)
Page 211: Initial State After Boot Rom Exit
The Boot ROM code is always executed after every reset operation. Depending on the program flow through the Boot ROM code and the Boot ROM exit path, several resources of the TC1796 on-chip hardware have been used and have been programmed. This means that the state of on-chip hardware resources that have been used by the Boot ROM code may differ from the device reset state as described by the register reset values.
Page 212: Bootstrap Loader (Bsl)
Reset and Boot Operation Bootstrap Loader (BSL) The bootstrap loader (BSL) is a software part which is integrated in the TC1796 Boot ROM. The BSL provides a mechanism to load a program code via a serial interface (ASC or CAN) into the scratchpad RAM (SPRAM) of the PMI. After loading of the code, the...
Page 213: Bootstrap Loader Mode 1 - Asc Boot Via Asc0 Pins
This task requires the external host to transmit an initialization byte to the TC1796 at the RXD0A input line of the ASC0. The initialization byte is built up by one low level start bit, eight low-level data bits, and 1 stop bit (a low pulse with a width of nine serial bit cells).
Page 214 TC1796 System Units (Vol. 1 of 2) Reset and Boot Operation identification byte has been transmitted, the ASC0 receive pin is enabled again. The bootstrap loader software now enters two receive loops. The inner loop waits until it has received four bytes. The outer loop writes one word (four bytes) to the scratchpad RAM (SPRAM) program memory of the PMI.
Page 215 TC1796 System Units (Vol. 1 of 2) Reset and Boot Operation Initialization of ASC0 Bootstrap Loader Mode 1 Transmit identification D5 RXD0A pin = 1? Ident. byte transmitted? Enable receiver RXD0A pin = 0? Initialize data pointer Byte counter = 4...
Page 216: Bootstrap Loader Mode 2 - Can Boot Via Can Pins
Data frame(s) - sent by the external host to the TC1796 The initialization frame is used in the TC1796 for baud rate detection. After a successful baud rate detection is reported to the external host by the acknowledge frame, data is transmitted by data frames.
Page 217 (data bytes 0 and 1 of the initialization frame), the CAN bootstrap loader program calculates the CAN baud rate and programs the baud rate registers of the MultiCAN module. The TC1796 is now ready to receive CAN frames with the baud rate of the external host.
Page 218 If no acknowledge frame is sent back within a certain time as defined in the external host (e.g. after a dedicated number of initialization frame transmissions), the external host can decide that the TC1796 is not able to establish the CAN boot communication link. User’s Manual 4-26 V2.0, 2007-07...
Page 219 TC1796 System Units (Vol. 1 of 2) Reset and Boot Operation MultiCAN Module in TC1796 External Host Controller Initialization of CAN Defining parameters for bootstrap loader mode 2 initialization frame Sampling RXDCAN0 Sending Init. Frame for 5555 pattern and checking ACK slot Init.
Page 220: Bootstrap Loader Mode 3 - Asc Boot Via Can Pins
TC1796 System Units (Vol. 1 of 2) Reset and Boot Operation 4.4.3 Bootstrap Loader Mode 3 - ASC Boot via CAN Pins Except for different connections to serial port lines of ASC0, the bootstrap loader mode 3 is identical with bootstrap loader mode 1. The serial data input of the ASC0 is connected to RXD0B which is an alternate function of P6.8/RXDCAN0 and the serial...
Page 221 1) This value is default after reset without connecting P0.[2:0] to a low or high level. Port 0 pins are inputs after reset with a pull-up device connected. Note: For CRC generation and error checking, the Boot ROM software uses the TC1796 on-chip memory checker module with an initial value of FFFF FFFF for the memory checker result register before the checksum is generated.
Page 222 TC1796 System Units (Vol. 1 of 2) Reset and Boot Operation Table 4-9 shows the structure of the ABM headers. Table 4-9 Structure of ABM Headers Address Value Function XXXX XXE0 32-bit start address Program/code start address XXXX XXE4 DEAD BEEF...
Page 223: System Control Unit
System Units (Vol. 1 of 2) System Control Unit System Control Unit The System Control Unit (SCU) of the TC1796 handles system control tasks. All the system functions described in this chapter are tightly coupled; thus, they are conveniently handled by one unit, the SCU.
Page 224: Power Management
System Control Unit Power Management This section describes the power management system of the TC1796. Topics covered here include the internal system interfaces, external interfaces, state diagrams, and the operations of the CPU and peripherals. The power management state machine is also described.
Page 225: Power Management Control And Status Register, Pmg_Csr
5.1.2 Power Management Control and Status Register, PMG_CSR The set of registers used for power management is divided between central TC1796 components and peripheral components. The PMG_CSR register provides software control and status information for the PMSM. There are individual clock control registers for peripheral components because the Sleep Mode behavior of each peripheral component is programmable.
Page 226 TC1796 System Units (Vol. 1 of 2) System Control Unit PMG_CSR Power Management Control and Status Register (F0000034 Reset Value: 0000 0100 PMST REQSLP Field Bits Type Function REQSLP [1:0] Idle Mode and Sleep Mode Request Normal Run Mode Request Idle Mode Request Sleep Mode Reserved;...
Page 227: Power Management Modes
If any of these conditions arise, the TC1796 immediately awakens and returns to Run Mode. If it is awakened by a hardware or software reset signal, the TC1796 system begins its reset sequence. If it is awakened by a Watchdog Timer overflow event, it executes the instruction following the one that was last executed before Idle Mode was entered.
Page 228: Sleep Mode
These clock control registers must have been previously configured by software. TC1796 State During Sleep Mode Sleep Mode is disabled for a unit if its clock control register bit EDIS is set to 1. The sleep signal is ignored in this case and the corresponding unit continues normal operation.
Page 229: States Of Tc1796 Units In Power Management Modes
System Control Unit 5.1.3.3 States of TC1796 Units in Power Management Modes Table 5-2 summarizes the state of the various units of the TC1796 during Run Mode, Idle Mode, and Sleep Mode. Table 5-2 States of TC1796 Units in Power Management Modes...
Page 230: Configuration Input Sampling
System Control Unit Configuration Input Sampling Several device pins of the TC1796 are latched either by a hardware reset or power-on reset operation. The latched states of such pins may directly determine the start-up configuration and conditions of the TC1796. The latched pins are divided into two types: •...
Page 231: External Request Unit (Eru)
Therefore, it can become necessary to check for patterns (gating of functions) or to reroute trigger events from one block to another. In the TC1796, a flexible External Request Unit (ERU) makes it possible to generate trigger events that are able to generate interrupts, trigger a DMA transfers, or start analog-to-digital conversions.
Page 232: Input Channel
TC1796 System Units (Vol. 1 of 2) System Control Unit The External Request Select unit (ERS) has three parts: • The External Request Selection unit (ERS) selects one input signal for each input channel. • The External Trigger Logic unit (ETL) selects the input channel’s input signal trigger condition, and provides output signals to the output channel.
Page 233 TC1796 System Units (Vol. 1 of 2) System Control Unit The ETL of the input channel analyzes the synchronized output signal INx of the ERS by an edge-detection logic. This edge-detection block generates a pulse (one clock cycle long) when a signal transition is detected. The selection which signal transition (edge) should generate a pulse (event) is done by two control bits, one for the rising edge (EICRn.RENx) and one for the falling edge (EICRn.FENx).
Page 234: Output Channel
TC1796 System Units (Vol. 1 of 2) System Control Unit 5.3.2 Output Channel The output channel logic shown in Figure 5-3 is built in for each of the four output channels. IGCRn PDRR IPENy3 IPENy2 IPENy1 IPENy0 GEENy IGPy PDRy...
Page 235 GOUTy Output Signal The gating output GOUTy represents the programmable level of PDOUTy. This output signal is not connected/used in TC1796 but referred in the register descriptions. TOUTy Output Signal The trigger output TOUTy combines all related event trigger sources. This output can be used to request ADC conversions or to start other peripheral actions.
Page 236: External Request Unit Implementation
TC1796 System Units (Vol. 1 of 2) System Control Unit when a pattern is detected, when a pattern is no longer detected, or if both conditions are true. 5.3.3 External Request Unit Implementation This section describes how the ERU is interconnected within other on-chip modules.
Page 237 TC1796 System Units (Vol. 1 of 2) System Control Unit TGADCx.SW0GTSEL SW0GT PDOUT0 GOUT0 ASGT Output N.C. IOUT0 Channel 0 TOUT0 TGADCx.EGTSEL PDOUT1 GOUT1 TGADCx. Output N.C. ETRSEL IOUT1 Channel 1 TOUT1 PDOUT2 GOUT2 Output N.C. IOUT2 Channel 2 TOUT2 TGADCx.
Page 238: External Request Unit Registers
External Request Unit Registers Table 5-4 refer to the registers associated with the ERU Kernel as well as the two TC1796 implementation-specific ERU registers, which control the ERU connections with the A/D converters ADC0 and ADC1. Table 5-4 External Trigger Request Unit Kernel Registers...
Page 239 TC1796 System Units (Vol. 1 of 2) System Control Unit The External Input Channel Register EICR0 and EICR1 for the external input channels 0 to 3 contain bits to configure the input gating logic IGL and the event trigger logic ETL.
Page 240 TC1796 System Units (Vol. 1 of 2) System Control Unit Field Bits Type Description LDEN0 Level Detection Enable 0 This bit determines if bit INTF0 is cleared automatically if an edge of the input signal IN0 is detected, which has not been selected (rising edge with REN0 = 0 or falling edge with FEN0 = 0).
Page 241 TC1796 System Units (Vol. 1 of 2) System Control Unit Field Bits Type Description REN1 Rising Edge Enable 1 This bit determines if the rising edge of signal IN1 is used to set bit INTF1. The rising edge is not used.
Page 242 TC1796 System Units (Vol. 1 of 2) System Control Unit EICR1 External Input Channel Register 1 (F0000084 Reset Value: 0000 0000 INP3 EXIS3 INP2 EXIS2 Field Bits Type Description EXIS2 [5:4] External Input Selection 2 This bit field determines which input line is selected for signal IN2.
Page 243 TC1796 System Units (Vol. 1 of 2) System Control Unit Field Bits Type Description LDEN2 Level Detection Enable 2 This bit determines if bit INTF2 is cleared automatically if an edge of the input signal IN2 is detected, which has not been selected (rising edge with REN2 = 0 or falling edge with FEN2 = 0).
Page 244 TC1796 System Units (Vol. 1 of 2) System Control Unit Field Bits Type Description REN3 Rising Edge Enable 3 This bit determines if the rising edge of signal IN3 is used to set bit INTF3. The rising edge is not used.
Page 245 TC1796 System Units (Vol. 1 of 2) System Control Unit The External Input Flag Register EIFR contains all interrupt flags for the external input channels. The bits in this register can be cleared by software by setting FMR.FCx, and set by setting FMR.FSx.
Page 246 TC1796 System Units (Vol. 1 of 2) System Control Unit The Flag Modification Register is a write-only register that is used to set and to clear the bits INTFx in register EIFR. If a set event and a clear event (hardware or software) for bit INTFx occur at the same time, the set event is taken into account.
Page 247 TC1796 System Units (Vol. 1 of 2) System Control Unit The Pattern Detection Result Register monitors the combinatorial output status of the pattern detection units. PDRR Pattern Detection Result Register (F0000090 Reset Value: 0000 000F Field Bits Type Description PDRy...
Page 248 TC1796 System Units (Vol. 1 of 2) System Control Unit The Interrupt Gating Control Registers IGCR0 and IGCR1 contain bits to enable the pattern detection and to control the gating for output channel 0 to 3 (e.g. for interrupt nodes or peripherals).
Page 249 TC1796 System Units (Vol. 1 of 2) System Control Unit Field Bits Type Description IGP0 [15:14] rw Interrupt Gating Pattern 0 Bit field IGP0 determines how the pattern detection influences the output lines GOUT0 and IOUT0. The detected pattern is not taken into account.
Page 250 TC1796 System Units (Vol. 1 of 2) System Control Unit Field Bits Type Description IGP1 [31:30] rw Interrupt Gating Pattern 1 Bit field IGP1 determines how the pattern detection influences the output lines GOUT1 and IOUT1. The detected pattern is not taken into account.
Page 251 TC1796 System Units (Vol. 1 of 2) System Control Unit IGCR1 Interrupt Gating Register 1 (F0000098 Reset Value: 0000 0000 IPEN IPEN IPEN IPEN IGP3 IPEN IPEN IPEN IPEN IGP2 Field Bits Type Description IPEN2x Interrupt Pattern Enable for Channel 2...
Page 252 TC1796 System Units (Vol. 1 of 2) System Control Unit Field Bits Type Description IGP2 [15:14] rw Interrupt Gating Pattern 2 Bit field IGP2 determines how the pattern detection influences the output lines GOUT2 and IOUT2. The detected pattern is not taken into account.
Page 253 TC1796 System Units (Vol. 1 of 2) System Control Unit Field Bits Type Description IGP3 [31:30] rw Interrupt Gating Pattern 3 Bit field IGP3 determines how the pattern detection influences the output lines GOUT3 and IOUT3. The detected pattern is not taken into account.
Page 254 TC1796 System Units (Vol. 1 of 2) System Control Unit The Trigger Gating ADC0 Register TGADC0 contains bit fields that determine the assignment of the output signals of the external request unit to the trigger and gating inputs of ADC0. The Trigger Gating ADC1 Register TGADC1 contains bit fields that determine the assignment of the output signals of the external request unit to the trigger and gating inputs of ADC1.
Page 255 TC1796 System Units (Vol. 1 of 2) System Control Unit Field Bits Type Description SW0TRSEL [6:4] SW0 Trigger Request Selection This bit determines which trigger source will be used for the SW0 trigger request input SW0TR of ADCx. SW0TR is constant at 0 level (trigger function switched off).
Page 256 TC1796 System Units (Vol. 1 of 2) System Control Unit Field Bits Type Description EGTSEL [18:16] External Gating Selection This bit determines which trigger source will be used for the external gating input EGT of ADCx. EGT is constant at 0 level (externally triggered conversions permanently disabled).
Page 257: Special System Interrupts
TC1796 System Units (Vol. 1 of 2) System Control Unit Special System Interrupts For some of the possible interrupts in the system, the interrupt control logic is not directly controlled in the module, but via the SCU, e.g. for the FPU interrupts, which are generated in the CPU, but have to be processed outside the CPU.
Page 258: Flash Interrupt
TC1796 System Units (Vol. 1 of 2) System Control Unit The FPU interrupt uses the system interrupt node DMA_SYSSRC0 located in the DMA controller. A description of this register can be found on Page 12-108. Note that DMA_SYSSRC0.TOS should be written with 00 because FPU interrupt should only be serviced by the CPU (and not by the PCP).
Page 259: Sram Parity Control
System Units (Vol. 1 of 2) System Control Unit SRAM Parity Control In TC1796, several on-chip memory blocks are equipped with a parity error detection logic. Each memory block as defined in Table 5-5 provides a parity error detection logic.
Page 260 TC1796 System Units (Vol. 1 of 2) System Control Unit SCU_PETSR SCU_PETCR PFL0 PEN0 Data Memory ≥1 Parity Error Non-Maskable Interrupt SCU_PETSR SCU_PETCR PFL6 PEN6 CAN Module Memory Parity Error MCA06448 Figure 5-7 Control of SRAM Parity Error Detection in SCU User’s Manual...
Page 261: Parity Error Trap Registers
TC1796 System Units (Vol. 1 of 2) System Control Unit 5.5.1 Parity Error Trap Registers Additional details about the NMI handling of SRAM parity errors are described in section “SRAM Parity Error NMI” on Page 14-26. SCU_PETCR SCU Parity Error Trap Control Register...
Page 262 TC1796 System Units (Vol. 1 of 2) System Control Unit SCU_PETSR SCU Parity Error Trap Status Register (F00000D4 Reset Value: 0000 0000 Field Bits Type Description PFLx Parity Error Flag for SRAM Module x (x = 0-6) These bits indicate whether a parity error has been detected in the associated SRAM memory module.
Page 263: Pad Driver Temperature Compensation Control
System Units (Vol. 1 of 2) System Control Unit Pad Driver Temperature Compensation Control In the TC1796, two groups of pads can be controlled separately by a temperature compensation control logic: • Class B1/B2 pads of the EBU interface when used as outputs •...
Page 264 TC1796 System Units (Vol. 1 of 2) System Control Unit System TCE1 TCS1 Control THMIN1 Unit THMED1 To Pad Logic of THMAX1 Outputs 100 KHz Control 1/TCDIV POSCEN TCV1 TCC1 THCOUNT TCV0 TCC0 THMAX0 To Pad THMED0 Logic of THMIN0...
Page 265 TC1796 System Units (Vol. 1 of 2) System Control Unit The switching thresholds are evaluated hierarchically (see Table 5-6). For proper operation the relationship THMIN > THMED > THMAX must be true. With increasing temperature, the compensation value SCU_TCLRx.THCOUNT decreases.
Page 266: Temperature Compensation Registers
TC1796 System Units (Vol. 1 of 2) System Control Unit 5.6.2 Temperature Compensation Registers Note: Control/status bits with index 0 are assigned for output control of class A2 GPIO output lines. Control/status bits with index 1 are assigned for EBU output control.
Page 267 TC1796 System Units (Vol. 1 of 2) System Control Unit Field Bits Type Description TCS0 Temperature Compensation 0 Source Temperature compensation logic 0 is controlled by the temperature compensation control hardware. Temperature compensation logic 0 is controlled by software via bit field TCC0.
Page 268 TC1796 System Units (Vol. 1 of 2) System Control Unit SCU_TCLR0 SCU Temperature Compensation 0 Level Register (F0000058 Reset Value: 02FF FFFF THCOUNT THMAX0 THMED0 THMIN0 Field Bits Type Description THMIN0 [7:0] Minimum Threshold for Temp. Compensation 0 Driver level = Low or Min...
Page 269 TC1796 System Units (Vol. 1 of 2) System Control Unit SCU_TCLR1 SCU Temperature Compensation 1 Level Register (F000005C Reset Value: 02FF FFFF THCOUNT THMAX1 THMED1 THMIN1 Field Bits Type Description THMIN1 [7:0] Minimum Threshold for Temp. Compensation 1 Driver level = Low or Min...
Page 270: Die Temperature Sensor
System Control Unit Die Temperature Sensor The TC1796 provides an on-chip Die Temperature Sensor (DTS). The output voltage of the DTS can be measured using analog input AIN31 of the ADC1 module. For measuring the DTS output voltage, the following conditions must be met: •...
Page 271: Gpta1 Input In1 Control
System Control Unit GPTA1 Input IN1 Control In the TC1796, the input line IN1 of the GPTA0, GPTA1, and LTCA2 module can be used to measure the baud rate of an ASC0 or ASC1 receiver input signal with GPTA1. This feature is controlled by a bit of the SCU, SCU_CON.GIN1S.
Page 272: Pad Test Mode Control
The pad test mode control logic in the SCU can be used for in-system tests of board connections for dedicated pins (pins without GPIO functionality). The pad test mode can be enabled in the normal operating mode of the TC1796. A special enable procedure (two-word write sequence) avoids unintentionally enabling the pad test mode.
Page 273: Pad Test Mode Enabling
TC1796 System Units (Vol. 1 of 2) System Control Unit read back. The ENOUTn bits determine whether or not the logic level state as defined by the bits in the SCU_PTDATn register is output to the pad/pin. 5.9.1 Pad Test Mode Enabling To enable the pad test mode, the following two-word write sequence must be executed: 1.
Page 274 TC1796 System Units (Vol. 1 of 2) System Control Unit SCU_PTCON SCU Pad Test Control Register (F00000B0 Reset Value: 0000 0000 PTMLC Field Bits Type Description PTMLC [7:0] Pad Test Mode Lock Code This bit field must be written with a special two-word write sequence to enable the pad test mode.
Page 275 TC1796 System Units (Vol. 1 of 2) System Control Unit Field Bits Type Description 17, 18 Reserved Read as 0; bits must be written with 0. PTMEN Pad Test Mode Enable Flag Pad test mode disabled (default after reset) Pad test mode enabled...
Page 276 TC1796 System Units (Vol. 1 of 2) System Control Unit SCU_PTDAT1 SCU Pad Test Data Register 1 (F00000B8 Reset Value: XXXX XXXX CS3 CS2 CS1 CS0 Field Bits Type Description Pad Test Value for/of TRn (n = 0-15) BRKIN Pad Test Value for/of BRKIN...
Page 277 TC1796 System Units (Vol. 1 of 2) System Control Unit Note: In pad test mode, the bits in SCU_PTDAT1 are output to the pad/pin in inverted state: a 0 generates a high level and a 1 generates a low level at the pad/pin.
Page 278 TC1796 System Units (Vol. 1 of 2) System Control Unit Field Bits Type Description SCLK0 Pad Test Value for/of SCLK0 SLSI0 Pad Test Value for/of SLSI0 Note: In pad test mode, the bits in SCU_PTDAT2 are output to the pad/pin in inverted state: a 0 generates a high level and a 1 generates a low level at the pad/pin.
Page 279: Emergency Stop Output Control For Gpta And Msc
5.10 Emergency Stop Output Control for GPTA and MSC The emergency stop feature of the TC1796 allows for a fast emergency reaction on an external event for the GPTA and MSC modules without the intervention of software. In an emergency case, the GPTA outputs of the TC1796 can be selectively put immediately to a well-defined logic level.
Page 280: Gpta Output Emergency Control In The Gpio Ports
HWCFG1 signal and EMGSTOP signal generation. If the system clock is switched off (not applicable in TC1796), the synchronous mode control logic is frozen and not able to react to transitions at input HWCFG1. In this case, the asynchronous mode can be used to put GPTA outputs to dedicated logic levels.
Page 281: Emergency Stop Register
TC1796 System Units (Vol. 1 of 2) System Control Unit 5.10.3 Emergency Stop Register The Emergency Stop Register SCU_EMSR contains control and status bits/flags of the emergency stop input logic. SCU_EMSR SCU Emergency Stop Register (F0000044 Reset Value: 0000 0000...
Page 282: Analog Input 7 Testmode
TC1796 System Units (Vol. 1 of 2) System Control Unit Field Bits Type Description EMSF Emergency Stop Flag This bit indicates if an emergency stop condition has occurred. An emergency stop has not occurred. An emergency stop has occurred and signal EMGSTOP becomes active (if MODE = 0).
Page 283: Scu Registers And Address Map
Figure 5-14 SCU Registers The complete and detailed address map of all SCU registers is described in Table 18-3 Page 18-7 of the TC1796 User’s Manual System Units part (Volume 1). Table 5-9 SCU Registers Register Short Register Long Name...
Page 284 TC1796 System Units (Vol. 1 of 2) System Control Unit Table 5-9 SCU Registers (cont’d) Register Short Register Long Name Offset Description Name Address OSC_CON Oscillator Control Register Page 3-8 WDT_CON0 Watchdog Timer Control Register 0 Page 16-29 WDT_CON1 Watchdog Timer Control Register 1...
Page 285 TC1796 System Units (Vol. 1 of 2) System Control Unit Table 5-9 SCU Registers (cont’d) Register Short Register Long Name Offset Description Name Address SCU_PTCON SCU Pad Test Control Register Page 5-52 SCU_PTDAT0 SCU Pad Test Data Register 0 Page 5-53...
Page 286: Miscellaneous Scu Registers
TC1796 System Units (Vol. 1 of 2) System Control Unit 5.13 Miscellaneous SCU Registers This section includes descriptions of the following registers: • SCU Control Register SCU_CON • SCU Status Register SCU_STAT • SCU Module Identification Register SCU_ID • Manufacturer Identification Register MANID •...
Page 287 TC1796 System Units (Vol. 1 of 2) System Control Unit Field Bits Type Description CSOEN CSOVL Enable CSOVL will not activate CSCOMB (default after reset) CSOVL will activate CSCOMB See also Figure 13-10 Page 13-29. CSGEN CSGLB Enable CSGLB will not activate CSCOMB (default after reset).
Page 288 TC1796 System Units (Vol. 1 of 2) System Control Unit Field Bits Type Description SLSPDR SLSO0/SLSO1 Pad Driver Strength Selection Strong driver, sharp edge selected. Strong driver, soft edge selected. See also Page 10-83. SSC0PDR SSC0 Pad Driver Strength Selection...
Page 289: Scu Status Register
Boot ROM code and the Boot ROM exit path, several resources of the TC1796 on-chip hardware have been used and are programmed. This means that the state of on-chip hardware resources that have been used by the Boot ROM code, may differ from the device reset state as described by the register reset values.
Page 290 TC1796 System Units (Vol. 1 of 2) System Control Unit Field Bits Type Description FPU Invalid Operation Error Indication Flag Indicates the state of the FPU’s FI status flag latched during the last FPU interrupt. Emulation Extension Available Indicates if the emulation extension (= 1796ED) is available or not (= production device) EEC is not available.
Page 291: Device Identification Registers
Manufacturer Identification Register (F0000070 Reset Value: 0000 1820 16 15 MANUF DEPT Field Bits Type Description DEPT [4:0] Department Identification Number = 00 : indicates the Automotive & Industrial microcontroller department within Infineon Technologies. User’s Manual 5-69 V2.0, 2007-07 SCU, V2.0...
Page 292 Type Description CHREV [7:0] Chip Revision Number This bit field indicates the revision number of the TC1796 device (01 = first revision). CHREV can be used e.g. for major step identification purposes. The value of this bit field is defined in the TC1796 Data Sheet.
Page 293 TC1796 System Units (Vol. 1 of 2) System Control Unit The Redesign Tracing Register RTID provides a means of signalling minor redesigns that are not reflected in the CHIPID.CHREV bit field. RTID Redesign Tracing Identification Register (F0000078 Reset Value: 0000 XXXX...
Page 294: On-Chip System Buses And Bus Bridges
TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges On-Chip System Buses and Bus Bridges The TC1796 has four independent on-chip buses • Program Local Memory Bus (PLMB) • Data Local Memory Bus (DLMB) • System Peripheral Bus (SPB) •...
Page 295: Program And Data Local Memory Buses
TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges The SPB is accessible by the CPU via the LFI Bridge. The RPB connects the peripherals with high data rates (SSC, ADC, FADC) to the Dual- port memory (DPRAM) in the DMI, relieving the SPB and the two LMBs from these data transfers.
Page 296: Transaction Types
TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges 6.1.2 Transaction Types 6.1.2.1 Single Transfers Single transfers are all transactions that are initiated by any instruction (code or data) of the TriCore 1 CPU and that require a system resource which not part of the TriCore 1 PMI or DMI.
Page 297: Lmb Basic Operation
TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges Note: For the LMB default master, the one cycle gap does not result in a performance loss because it is granted the LMB in this cycle as default master if no other master requests the LMB for some other reasons.
Page 298: Local Memory Bus Controller Units
LMB Block Transactions Local Memory Bus Controller Units Each of the two LMBs in the TC1796 have a LMB Bus Control Unit (LBCU), one for the DLMB (DBCU) and one for the PLMB (PBCU). Where the description in this section refers to LBCU, the related topic is also valid for DBCU and PBCU.
Page 299: Lmb Bus Default Master
TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges 6.2.2.1 LMB Bus Default Master When no LMB master is requesting the LMB, it is granted to the LMB default master. This means if the default master needs the LMB in the next cycle, it can enter the address cycle without running through a request/grant cycle.
Page 300: Dlmb And Plmb Bus Registers
This section describes the registers of the DBCU/PBCU modules. The complete and detailed address maps of DBCU/PBCU are described in Table 18-38/Table 18-41 Page 18-122/Page 18-125 of this TC1796 System Units (Vol. 1 of 2) User’s Manual. LMB Bus Register Overview Module Identification General Registers...
Page 301 TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges DBCU_ID DBCU Module Identification Register (08 Reset Value: 000F C0XX PBCU_ID PBCU Module Identification Register (08 Reset Value: 000F C0XX 16 15 MODNUM MODTYPE MODREV Field Bits...
Page 302 TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges DBCU_LEATT DBCU LMB Error Attribute Register Reset Value: XXXX XXX0 PBCU_LEATT PBCU LMB Error Attribute Register Reset Value: XXXX XXX0 WR SVM FPITAG Field Bits Type Description...
Page 303 TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges Field Bits Type Description [18:16] LMB Bus Slave Response State This bit indicates status information of the LMB slave device in case of an LMB bus error.
Page 304 TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges Field Bits Type Description [31:28] LMB Bus Error Transaction Type This bit field indicates the type of transfer at which the LMB bus error occurred. 0000 8-bit data single transfer...
Page 305 TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges DBCU_LEADDR DBCU LMB Error Address Register Reset Value: XXXX XXXX PBCU_LEADDR PBCU LMB Error Address Register Reset Value: XXXX XXXX LEADDR Field Bits Type Description LEADDR [31:0]...
Page 306 TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges DBCU_LEDATH DBCU LMB Error Data High Register (2C Reset Value: XXXX XXXX PBCU_LEDATH PBCU LMB Error Data High Register (2C Reset Value: XXXX XXXX LEDAT[63:32] Field Bits...
Page 307 [31:16] Read as 0; should be written with 0. Note: Further details on interrupt handling and processing are described in Chapter 14 of this TC1796 System Units (Vol. 1 of 2) User’s Manual. User’s Manual 6-14 V2.0, 2007-07 Buses, V2.0...
Page 308: Local Memory To Fpi Bus Interface (Lfi Bridge)
TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges Local Memory to FPI Bus Interface (LFI Bridge) 6.3.1 Functional Overview The LFI Bridge is a bi-directional bus bridge between the DLMB and the System Peripheral FPI Bus (SPB). The bridge supports all transactions types of both the LMB Bus and FPI Bus.
Page 309: Lfi Register
Figure 6-5 LFI Register The complete and detailed address map of LFI is described in Table 18-42 Page 18-126 of this TC1796 System Units (Vol. 1 of 2) User’s Manual. Table 6-7 Registers Address Space - LFI Bridge Module Base Address...
Page 310 TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges LFI_ID LFI Module Identification Register Reset Value: 000C C0XX 16 15 MODNUM MODTYPE MODREV Field Bits Type Description MODREV [7:0] Module Revision Number MODREV defines the module revision number. The value of a module revision starts with 01 (first revision).
Page 311 Field Bits Type Description LTAG [6:4] LMB Bus (DLMB) Tag ID In the TC1796, the bit field LTAG = 000 FTAG [11:8] FPI Bus (SPB) Tag ID In the TC1796, the bit field FTAG = 1011 , which reflects the tag number of the LFI Bridge on the SPB.
Page 312: System And Remote Peripheral Bus
• Designed to minimize EMI and power consumption The functional units of the TC1796 are connected to the FPI bus via FPI bus interfaces. An FPI Bus interface act as bus agent, requesting bus transactions on behalf of their functional unit, or responding to bus transaction requests.
Page 313 Some functional units operate only as slaves, while others can operate as either masters or slaves. In the TC1796, DMI and PMI (via the LFI Bridge), PCP, DMA, and Cerberus operate as FPI Bus masters. On-chip peripheral units are typically FPI Bus slaves.
Page 314: Bus Transaction Types
2 word, 4 word, or 8 word transfers. Note: In general, block transfers (2 word, 4 word, or 8 word) cannot be executed in the TC1796 with peripheral units that operate as FPI Bus slaves during an FPI Bus transaction.
Page 315: Address Alignment Rules
TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges 6.4.4 Address Alignment Rules FPI Bus address generation is compliant with the following rules: • Half-word transactions must have a half-word aligned address (A0 = 0). Half-word accesses on byte lanes 1 and 2 addresses are illegal.
Page 316 TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges Bus Cycle Request/ Address Data Data Data Data Transfer 1 Grant Cycle Cycle Cycle Cycle Cycle Request/ Data Transfer 2 Address Cycle Grant Cycle MCA05635 Figure 6-8 FPI Bus Block Transactions User’s Manual...
Page 317: Fpi Bus Control Units (Sbcu And Rbcu)
BCU itself will drive the FPI Bus to prevent it from floating electrically. 6.5.1.1 Arbitration on the System Peripheral Bus The TC1796 SPB has five bus agents that can become a SPB bus master. Each agent is supplied a arbitration priority as shown in Table 6-9. DMA controller and OCDS agents can be assigned to low or high priorities by software.
Page 318: Starvation Prevention
To protect against bus starvation of lower-priority masters, an optional feature of the TC1796 will detect such cases and momentarily raise the priority of the lower-priority requestor to the highest priority (above all other priorities), thereby guaranteeing it access.
Page 319 Code (ACK) Description NSC: No Special Condition. SPT: Split Transaction (not used in the TC1796). RTY: Retry. Slave can currently not respond to the access. Master needs to repeat the access later. ERR: Bus Error, last data cycle is aborted.
Page 320: Clock Management
Transactions on the FPI Bus are classified via a 4-bit operation code (see Table 6-12). Note that split transactions (OPC = 1000 to 1110 ) are not used in the TC1796. Table 6-12 FPI Bus Operation Codes (OPC) Description 0000...
Page 321: Bcu Debug Support
TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges 6.5.4 BCU Debug Support For debugging purposes, the BCU has the capability for breakpoint generation support. This OCDS debug capability is controlled by the Cerberus module and must be enabled by it (indicated by bit xBCU_DBCNTL.EO).
Page 322: Signal Status Triggers
TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges 6.5.4.2 Signal Status Triggers The signal status debug trigger event conditions are defined by the contents of the xBCU_DBBOS and xBCU_DBCNTL registers. Depending on the selected configuration a wide range of possibilities arise for the creation of a debug trigger event based on FPI Bus status signals.
Page 323: Combination Of Triggers
TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges SBCU_DBGRNT SBCU_DBCNTL ≥1 & Cerberus is granted as bus master, low priority & DMA is granted as bus master, low priority & LFI Bridge is granted as Grant &...
Page 324: Bcu Breakpoint Generation Examples
TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges 6.5.4.5 BCU Breakpoint Generation Examples This section gives three examples of how BCU debug trigger events are programmed. OCDS Debug Example 1 • Task: Generation of a BCU debug trigger event on any SPB write access to address...
Page 325 TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges OCDS Debug Example 2 • Task: generation of a BCU debug trigger event on any half-word access in user mode to address area 01FFFFFF to 02FFFFFF by any master.
Page 326 TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges greater or equal to SBCU_DBADR1. ONG = 1 means that the grant debug trigger is enabled. CONCOM[2:0] = 101 means that the address trigger is created by address trigger 1...
Page 327: Sbcu And Rbcu Registers
MCA05640_mod Figure 6-13 SBCU Registers The complete and detailed address maps of SBCU/RBCU are described in Table 18-4/Table 18-26 Page 18-11/Page 18-79 of this TC1796 System Units (Vol. 1 of 2) User’s Manual. Table 6-13 Registers Address Space Module Base Address...
Page 328 TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges Table 6-14 Registers Overview - SBCU Registers (cont’d) Register Register Long Name Offset Description Short Name Address SBCU_DBGRNT SBCU Debug Grant Mask Register 0034 Page 6-45 RBCU_DBGRNT RBCU Debug Grant Mask Register...
Page 329: Bcu Control Registers
TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges 6.5.5.1 BCU Control Registers The xBCU Module Identification Register ID contains read-only information about the xBCU module version. SBCU_ID SBCU Module Identification Register (08 Reset Value: 0000 6AXX...
Page 330 TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges SBCU_CON SBCU Control Register Reset Value: 4009 FFFF RBCU_CON RBCU Control Register Reset Value: 4009 FFFF SPE PSE TOUT Field Bits Type Description TOUT [15:0] BCU Bus Time-Out Value The bit field determines the number of System Peripheral Bus time-out cycles.
Page 331: Bcu Error Registers
TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges Field Bits Type Description [23:20] r Reserved Read as 0; should be written with 0. 1) When an access occurs from an SPB bus master to the RPB while the RPB is busy, the SPB bus master has to wait until the RPB is granted.
Page 332 TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges SBCU_ECON SBCU Error Control Capture Register (20 Reset Value: 0000 0000 RBCU_ECON RBCU Error Control Capture Register (20 Reset Value: 0000 0000 RDN WRN SVM ABT RDY...
Page 333 The FPI Bus operation codes are defined in Table 6-12. 1) For the SBCU_ECON.ERRCNT bit field, the following additional sentence must be added: in the TC1796, aborted accesses to a 0 wait state SPB slave may also increment ERRCNT when the slave generates an error acknowledge.
Page 334 TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges SBCU_EADD SBCU Error Address Capture Register (24 Reset Value: 0000 0000 RBCU_EADD RBCU Error Address Capture Register (24 Reset Value: 0000 0000 FPIADR Field Bits Type Description...
Page 335: Ocds Registers
TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges 6.5.5.3 OCDS Registers SBCU_DBCNTL SBCU Debug Control Register Reset Value: 0000 7003 RBCU_DBCNTL RBCU Debug Control Register Reset Value: 0000 7003 ONA2 ONA1 Field Bits Type Description...
Page 336 TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges Field Bits Type Description CONCOM0 Grant and Address Trigger Relation Grant trigger condition and the address trigger condition are combined with a logical OR for further control.
Page 337 TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges Field Bits Type Description ONA2 [25:24] rw Address 2 Trigger Control No address 2 trigger is generated. An address 2 trigger event is generated if the FPI Bus address is equal to DBADR2.
Page 338 TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges Field Bits Type Description [3:2], Reserved [11:5], Read as 0; should be written with 0. [19:17], [23:22], [27:26] SBCU_DBGRNT SBCU Debug Grant Mask Register Reset Value: 0000 FFFF...
Page 339 TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges Field Bits Type Description DMAH DMA Grant Trigger Enable, High Priority FPI Bus transactions on SPB with low-priority DMA channels as bus master are enabled for grant trigger event generation.
Page 340 TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges RBCU_DBGRNT RBCU Debug Grant Mask Register Reset Value: 0000 FFFF Field Bits Type Description [3:0], Reserved Read as 1 after reset; reading these bits will return the [15:7] value last written.
Page 341 TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges SBCU_DBADR1 SBCU Debug Address 1 Register Reset Value: 0000 0000 RBCU_DBADR1 RBCU Debug Address 1 Register Reset Value: 0000 0000 ADR1 Field Bits Type Description ADR1 [31:0]...
Page 342 TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges SBCU_DBBOS SBCU Debug Bus Operation Signals Register Reset Value: 0000 0000 RBCU_DBBOS RBCU Debug Bus Operation Signals Register Reset Value: 0000 0000 Field Bits Type Description [3:0]...
Page 343 TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges Field Bits Type Description Write Signal for Status Debug Trigger This bit determines the state of the WR signal of an FPI Bus transaction for which a signal status debug trigger event is generated (if enabled by DBCNTL.ONBOS2 = 1).
Page 344 TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges SBCU_DBGNTT SBCU Debug Trapped Master Register Reset Value: FFFF FFFF Field Bits Type Description High-Priority Cerberus FPI Bus Master Status This bit indicates whether the high-priority Cerberus was SPB bus master when the break trigger event occurred.
Page 345 TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges Field Bits Type Description LFI Bridge FPI Bus Master Status This bit indicates whether the LFI Bridge was SPB bus master when the break trigger event occurred.
Page 346 TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges RBCU_DBGNTT RBCU Debug Trapped Master Register Reset Value: FFFF FFFF Field Bits Type Description [3:0], Reserved Read as 1. [15:7] DMAH High-Priority DMA FPI Bus Master Status...
Page 347 TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges Field Bits Type Description CHNR0y 16 + y DMA Channel Number Status (y = 0-7) These bits indicate which DMA channel with number 1y was active when a DMA break trigger event occurred at the RPB.
Page 348 TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges SBCU_DBBOST SBCU Debug Trapped Bus Operation Signals Register Reset Value: 0000 3180 RBCU_DBBOST RBCU Debug Trapped Bus Operation Signals Register Reset Value: 0000 3180 Field Bits Type Description...
Page 349 TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges Field Bits Type Description FPIACK [6:5] FPI Bus Acknowledge Status This bit field indicates the acknowledge signal status captured from the FPI Bus signal lines when the BCU break trigger event occurred.
Page 350 TC1796 System Units (Vol. 1 of 2) On-Chip System Buses and Bus Bridges Field Bits Type Description FPIRD FPI Bus Read Indication Status This bit indicates the read signal status captured from the FPI Bus signal lines when the BCU break trigger event occurred.
Page 351: Bcu Service Request Control Register
[31:16] Read as 0; should be written with 0. Note: Further details on interrupt handling and processing are described in Chapter 14 of this TC1796 System Units (Vol. 1 of 2) User’s Manual. User’s Manual 6-58 V2.0, 2007-07 Buses, V2.0...
Page 352: Program Memory Unit
TC1796 System Units (Vol. 1 of 2) Program Memory Unit Program Memory Unit The Program Memory Unit (PMU) shown in Figure 7-1 contains the following functional units: • 2 Mbyte of Program Flash Memory (PFLASH) • 128 Kbyte of Data Flash Memory (DFLASH) •...
Page 353: Program & Data Flash Memory
– Control logic that includes assembly buffers and voltage generators, for example The FIM and FAM are main parts of the Program Memory Unit (PMU). An overview of the PMU integration into the system architecture is shown in the TC1796 block and bus system diagrams (see...
Page 354 TC1796 System Units (Vol. 1 of 2) Program Memory Unit Flash Command 2 Mbyte State Machine Program Flash (FCS) (PFLASH) Flash Control Logic Data Bank 0 Error 128 Kbyte Correction Data Flash (ECC) (DFLASH) Bank 1 Flash Interface & Flash Array Module...
Page 355: Program Flash Overview
TC1796 System Units (Vol. 1 of 2) Program Memory Unit 7.2.1 Program Flash Overview The PFLASH memory has a capacity of 2 Mbyte. The internal structure of the PFLASH is based on a sector architecture. For flexible erase, programming, and protection...
Page 356 System Units (Vol. 1 of 2) Program Memory Unit The PFLASH array delivers 256-bit wide read data with one read access. In the TC1796, these 256 bits are transferred to the CPU and PMI via the 64-bit wide Program Local Memory Bus (PLMB) using single-cycle burst transfers with four 64-bit transfers.
Page 357 TC1796 System Units (Vol. 1 of 2) Program Memory Unit Table 7-1 defines the sectors with their sector numbers, sector sizes, and address ranges. The PFLASH contains thirteen sectors PS[12:0] with different sizes. Two 64 Kbyte physical sectors PPS[1:0] are defined for the PFLASH.
Page 358: Data Flash Overview
TC1796 System Units (Vol. 1 of 2) Program Memory Unit increase the endurance of a logical sector, its corresponding physical sector can be erased and reprogrammed after every 50 erase/program cycles of the logical sector. 7.2.2 Data Flash Overview The on-chip DFLASH has a capacity of 128 Kbyte, organized in two independent banks/sectors of 64 Kbyte each, DB0/DS0 and DB1/DS1.
Page 359 TC1796 System Units (Vol. 1 of 2) Program Memory Unit Features of Data Flash • 128 Kbyte on-chip data Flash memory, organized in two 64 Kbyte banks • Usable for data storage with EEPROM functionality • 128 byte program interface –...
Page 360: User Configuration Blocks Overview
TC1796 System Units (Vol. 1 of 2) Program Memory Unit Table 7-2 DFLASH Bank and Page Definitions (cont’d) Numbering Size Cached Non-Cached Address Range Address Range DP512 128 byte 8FE1 0000 - 8FE1 007F AFE1 0000 - AFE1 007F 128 byte...
Page 361 TC1796 System Units (Vol. 1 of 2) Program Memory Unit Table 7-3 User Configuration Block Definitions Numbering Size Address Range UCB0 UCP0 256 byte A000 0000 - A000 00FF UCP1 256 byte A000 0100 - A000 01FF UCP2 256 byte...
Page 362: Basic Flash Operating Modes
• Command Mode Since the TC1796 Flash array has three autonomous Flash banks, one PFLASH bank and two DFLASH banks, parallel write command execution (programming one bank while erasing the other bank) is supported for the two DFLASH banks, but not for the PFLASH bank and one DFLASH bank.
Page 363: Command Mode
TC1796 System Units (Vol. 1 of 2) Program Memory Unit For verify operations, the standard read can be combined with a margin check to find problematic bits (a 0 is read instead of a programmed 1) in advance. The change of...
Page 364: Page Mode
TC1796 System Units (Vol. 1 of 2) Program Memory Unit the Flash in its non-cached address space. Additionally, it is recommended to include a dummy read cycle to a PMU register after the last write cycle of a command sequence.
Page 365: Command Sequence Definitions
TC1796 System Units (Vol. 1 of 2) Program Memory Unit 7.2.5 Command Sequence Definitions Flash commands are executed by writing specific data to dedicated addresses in a well defined command specific sequence. The data to be transmitted within a command sequence must be transmitted right-aligned on data bus lines D[7:0] as byte (exception: 32-bit data, 64-bit data, 32-bit password).
Page 366: Reset-To-Read Command
TC1796 System Units (Vol. 1 of 2) Program Memory Unit 7.2.5.1 Reset-to-Read Command With the one-cycle Reset-to-Read command, the internal command state machine is reset to its initial state. This command can be issued at any time during a command sequence.
Page 367: Load Page Buffer Command
TC1796 System Units (Vol. 1 of 2) Program Memory Unit the actual Page Mode, indicated by sequence error flag FSR.SQER set, and restarts a new page operation. The selected assembly register remains unchanged (not cleared) with a new Enter Page Mode command.
Page 368 TC1796 System Units (Vol. 1 of 2) Program Memory Unit 1. Write AFE0 55F0 = word 0 (assembly buffer byte 3-0) 2. Write AFE0 55F4 = word 1 (assembly buffer byte 7-4) 3. Write AFE0 55F0 = word 2 (assembly buffer byte 11-8) 4.
Page 369: Write
TC1796 System Units (Vol. 1 of 2) Program Memory Unit 7.2.5.4 Write Page Command With the four-cycle Write Page command, the complete contents of the assembly buffer (256 bytes for PFLASH, 128 bytes for DFLASH) are transferred (programmed) into one page of PFLASH or DFLASH.
Page 370: Write User Configuration
TC1796 System Units (Vol. 1 of 2) Program Memory Unit The page programming algorithm includes a programming quality check that identifies and reprograms weak bits of a Flash page. If the reprogramming of weak bits is unsuccessful, the verify error flag FSR.VER is set.
Page 371: Erase Sector Command
TC1796 System Units (Vol. 1 of 2) Program Memory Unit 7.2.5.6 Erase Sector Command The six-cycle Erase Sector command is used to erase a sector in PFLASH or DFLASH. In PFLASH, either one of the 13 sectors PSx (x = 0-12) or one of the 2 physical sectors PPS0 or PPS1 that each include four sectors can be erased.
Page 372 TC1796 System Units (Vol. 1 of 2) Program Memory Unit With the last cycle of the Erase Sector command, Command Mode is entered and the following status flags are updated: • FSR.ERASE is set, indicating that a erase operation is running.
Page 373: Erase User Configuration Block Command
(including keywords and protection confirmation code) can be written to the pages of the user configuration block. But note that the user configuration blocks UCB0 and UCB1 can only be modified up to 4 times during the lifetime of a TC1796 device. UCB2 can be programmed only once.
Page 374: Disable Write Protection Command
TC1796 System Units (Vol. 1 of 2) Program Memory Unit 7.2.5.8 Disable Write Protection Command The six-cycle Disable Write Protection command temporarily disables the write protection of all protected PFLASH sectors as defined for user 0 (indicated in register PROCON0) or user 1 (indicated in register PROCON1).
Page 375: Disable Read Protection Command
TC1796 System Units (Vol. 1 of 2) Program Memory Unit 7.2.5.9 Disable Read Protection Command The six-cycle Disable Read Protection command temporarily disables an installed Flash read protection. Table 7-13 Disable Read Protection Command Cycle No. Address Data Cycle 1...
Page 376: Clear Status Command
TC1796 System Units (Vol. 1 of 2) Program Memory Unit 7.2.5.11 Clear Status Command The one-cycle Clear Status command clears/resets the following flags of the Flash status register FSR: • Error flags: PFOPER, DFOPER, SQER, PROER, PFSBER, DFSBER, PFDBER, and DFDBER •...
Page 377: Data Flash And Eeprom Emulation
TC1796 System Units (Vol. 1 of 2) Program Memory Unit 7.2.6 Data Flash and EEPROM Emulation The 128 Kbyte Data Flash is able to support an emulation of an EEPROM. This EEPROM emulation is fully based on a software administration by a user program. The...
Page 378: Read And Write Protection
Write User Configuration Page command, and erased block-wise by the Erase User Configuration Block command. User configuration blocks UCB0 and UCB1 can be programmed/erased during TC1796 device life-time only up to 4 times. UCB2 can be programmed only once. Table 7-16 defines the contents of the three UCBs.
Page 379 TC1796 System Units (Vol. 1 of 2) Program Memory Unit Table 7-16 Layout of User Configuration Blocks Page Address Byte(s) Content UCB0 UCP0 A000 0000 [1:0] Protection configuration bits (content as defined for PROCON0) A000 0008 [9:8] Copy of bytes [1:0]...
Page 380 TC1796 System Units (Vol. 1 of 2) Program Memory Unit Table 7-16 Layout of User Configuration Blocks (cont’d) Page Address Byte(s) Content UCB2 UCP8 A000 0800 [1:0] Protection configuration bits (content as defined for PROCON2) A000 0808 [9:8] Copy of bytes [1:0] –...
Page 381: Write And Otp Protection For Pflash
7.2.7.2 Write and OTP Protection for PFLASH Write protection is a feature that must be installed by the user of the TC1796 device. In the delivery state of the TC1796, no write protection is installed meaning that the UCBs are in erased state. If sector write protection is active for a PFLASH sector, erasing and programming of this sector is only possible if the corresponding UCB keywords are known.
Page 382 TC1796 System Units (Vol. 1 of 2) Program Memory Unit protection is hierarchically controlled. This means, if user 0 (assigned to UCB0) disables write protection for his sector(s), also write protection for user 1 (assigned to UCB1) is disabled but not vice versa (user 1 can only disable his own protected sectors).
Page 383: Read Protection For Pflash And Dflash
TC1796 System Units (Vol. 1 of 2) Program Memory Unit 7.2.7.3 Read Protection for PFLASH and DFLASH When read protection is active, read accesses from PFLASH and DFLASH memory locations are generally disabled, if code execution is not started from internal Flash after reset.
Page 384: Password Check Control
(read- and/or write-protected) and the protection error flag FSR.PROER is set. In this case, a new Disable Write Protection command or a Disable Read Protection command is only accepted after the next TC1796 reset operation.
Page 385: Error Correction And Margin Control
On the other hand, an ECC of FF is generated when all bits of a 64-bit data portion are programmed with a 1. In general, the TC1796 Flash module supports the following error detection and correction functionality for PFLASH and DFLASH read accesses: •...
Page 386: Margin Check Control
7.2.8.2 Margin Check Control The margin control feature of the TC1796 Flash module makes it possible to change the sensing levels of the sense amplifiers of the Flash array bit lines for read operations. With this feature, problematic Flash array bits can be found in advance, before they convert to stable erratic bits.
Page 387: Flash Interrupt Generation And Control
TC1796 System Units (Vol. 1 of 2) Program Memory Unit 7.2.9 Flash Interrupt Generation and Control One interrupt request can be issued by the Flash module. The related interrupt control register is located in the DMA controller. The Flash interrupt can be issued when any of the following events occur: •...
Page 388 TC1796 System Units (Vol. 1 of 2) Program Memory Unit FCON End-of-Busy Conditions PBUSY EOBM Edge D0BUSY Detection D1BUSY FCON SQER PROER SQERM PROERM Command Sequence Error Protection ≥1 Error FCON DFSBER PFSBER DFSBERM PFSBERM DFLASH Single Bit FLASH Error...
Page 389: Flash Power Supply, Power Saving And Reset
7.2.10.2 Sleep Mode The TC1796 Flash module provides a sleep mode which makes it possible to reduce the power consumption of the Flash module. Flash sleep mode is only entered if the Flash module is in idle state with all pending or active operations processed and terminated.
Page 390: Reset Control
TC1796 System Units (Vol. 1 of 2) Program Memory Unit program but controlled by the Boot ROM startup procedure that is executed after each reset operation. 7.2.10.4 Reset Control The Flash module uses • The system reset, which is represented by the fast LMB reset; this reset includes all reset sources (power-on, hardware, software and watchdog reset), and •...
Page 391: Flash Registers
Figure 7-7 Flash Registers The complete and detailed address map of the FLASH registers is described in Table 18-36 Page 18-117 of the TC1796 User’s Manual System Units part (Volume 1). Table 7-17 Registers Address Space -Flash Registers Module Base Address...
Page 392: Flash And Pmu Module Identification Registers
TC1796 System Units (Vol. 1 of 2) Program Memory Unit 1) The Flash register short names are also referenced in other parts of this chapter without the module prefix name “FLASH_”. 2) This register is located in the address range for the DMA controller.
Page 393 TC1796 System Units (Vol. 1 of 2) Program Memory Unit The PMU Module Identification Register ID contains read-only information about the PMU module version. PMU_ID PMU Module Identification Register Reset Value: 002E C0XX 16 15 MODNUM MODTYPE MODREV Field Bits...
Page 394: Flash Status Register
TC1796 System Units (Vol. 1 of 2) Program Memory Unit 7.2.11.2 Flash Status Register The read-only Flash Status Register indicates the overall status of the Flash module. It includes busy, program, erase, error, protection, and sleep mode flags. FLASH_FSR Flash Status Register...
Page 395 TC1796 System Units (Vol. 1 of 2) Program Memory Unit Field Bits Type Description D0BUSY DFLASH Bank 0 Busy This flag indicates the busy state of DFLASH bank 0 during program or erase operations. It also indicates when the DFLASH bank 0 is not in Read Mode, e.g.
Page 396 TC1796 System Units (Vol. 1 of 2) Program Memory Unit Field Bits Type Description ERASE Erase State This flag indicates whether PFLASH or DFLASH is currently erased or have been erased. ERASE is set with the last cycle of an erase command sequence.
Page 397 TC1796 System Units (Vol. 1 of 2) Program Memory Unit Field Bits Type Description DFOPER DFLASH Operation Error This flag indicates a flash array error during DFLASH operation. DFOPER is cleared by a reset operation, by a Reset-to-Read command, or by a Clear Status command.
Page 398 TC1796 System Units (Vol. 1 of 2) Program Memory Unit Field Bits Type Description DFSBER DFLASH Single-Bit Error and Correction This flag indicates the occurrence of a single-bit error in the DFLASH that has been corrected. DFSBER is cleared by a Reset-to-Read command, or by a Clear Status command, or by any reset operation.
Page 399 TC1796 System Units (Vol. 1 of 2) Program Memory Unit Field Bits Type Description RPROIN Read Protection Installed This flag indicates whether read protection is correctly installed. This bit is updated only if a modified read protection installation is detected at a reset operation.
Page 400 TC1796 System Units (Vol. 1 of 2) Program Memory Unit Field Bits Type Description WPROIN2 UCB2 Write Protection (OTP) Installed This flag indicates whether sector write protection (OTP) in user configuration block UCB2 is correctly installed and confirmed. No OTP write protection installed in UCB2.
Page 401 TC1796 System Units (Vol. 1 of 2) Program Memory Unit Field Bits Type Description Verify Error This flag indicates whether a Flash page has been correctly programmed. VER is cleared by any reset operation and by the Clear Status command.
Page 402: Margin Control Registers
TC1796 System Units (Vol. 1 of 2) Program Memory Unit 7.2.11.3 Margin Control Registers The Margin Control Registers for Program Flash (MARP) and for Data Flash (MARD) are defined as follows: FLASH_MARP Flash Margin Control Register PFLASH (1018 Reset Value: 0000 8000...
Page 403 TC1796 System Units (Vol. 1 of 2) Program Memory Unit FLASH_MARD Flash Margin Control Register DFLASH (101C Reset Value: 0000 8000 MARGIN MARGIN Field Bits Type Description MARGIN0 [1:0] DFLASH Margin Selection for Low Level Standard margin selected High margin for 0 (low) level selected...
Page 404: Flash Configuration Register
TC1796 System Units (Vol. 1 of 2) Program Memory Unit 7.2.11.4 Flash Configuration Register The Flash Configuration Register FCON controls general Flash configuration functions: • Number of internal wait states for Flash accesses (without or with word-line hit) • Indication of installed and active read protection •...
Page 405 TC1796 System Units (Vol. 1 of 2) Program Memory Unit Field Bits Type Description WSECPF Wait State for PFLASH Error Correction This bit determines whether an additional wait state is inserted for error correction during read accesses to PFLASH. No additional wait state inserted.
Page 406 TC1796 System Units (Vol. 1 of 2) Program Memory Unit Field Bits Type Description WSECDF Wait State for DFLASH Error Correction This bit determines whether an additional wait state is inserted for error correction during read accesses to DFLASH. No additional wait state inserted.
Page 407 TC1796 System Units (Vol. 1 of 2) Program Memory Unit Field Bits Type Description Disable Code Fetch from Flash Memory This bit enables/disables the code fetches from the internal PFLASH memory when read protection is active. Once set, this bit can only be cleared when read protection is inactive (RPA = 0).
Page 408 TC1796 System Units (Vol. 1 of 2) Program Memory Unit Field Bits Type Description DDFDMA Disable Data Fetch from DMA Controller This bit enables/disables PFLASH and DFLASH data read accesses that are initiated by the DMA controller. Once set, this bit can only be cleared when RPA = 0.
Page 409 TC1796 System Units (Vol. 1 of 2) Program Memory Unit Field Bits Type Description PFDBERM PFLASH Double-Bit Error Interrupt Mask This bit disables/enables the PFLASH double-bit error interrupt. PFLASH double-bit error interrupt is disabled. PFLASH double-bit error interrupt is enabled.
Page 410: Protection Configuration Registers
TC1796 System Units (Vol. 1 of 2) Program Memory Unit 7.2.11.5 Protection Configuration Registers The configuration of read/write protection and OTP functionality is indicated by three Protection Configuration Registers: • FLASH_PROCON0 indicates the read/write protection configuration for user 0 (UCB0) •...
Page 411 TC1796 System Units (Vol. 1 of 2) Program Memory Unit FLASH_PROCON1 Flash Protection Configuration Register User 1 (1024 Reset Value: 0000 XXXX S12L S11L S10L S9L S8L S7L S6L S5L S4L S3L S2L S1L S0L Field Bits Type Description Sector Locked for Write Protection by User 1...
Page 412: Emulation Interface
TC1796 emulation device, called TC1796ED. Segment 8 and 10 reserves 512 Kbyte for the emulation memory interface. In the TC1796, a CPU read access from the emulation memory region causes a DSE trap, a PLMB and a DLMB bus error. If the emulation memory region read access is initiated by a SPB master (e.g.
Page 413: Data Memory Unit
TC1796 System Units (Vol. 1 of 2) Data Memory Unit Data Memory Unit The Data Memory Unit (DMU) shown in Figure 8-1 contains a total of 80 Kbyte of fast static RAM memory: • 64 Kbyte SRAM memory that can be used as –...
Page 414: Dlmb/Plmb Interfaces
. This power supply pin provides the power for normal DDSBRAM operation of SBRAM, and during power-off state of the TC1796. If does not DDSBRAM drop below a specified voltage level in power-down mode (specified in Data Sheet), the SBRAM will remain its memory content.
Page 415: Parity Protection For Dmu Memories
Data Memory Unit Parity Protection for DMU Memories In the TC1796, the SBRAM and SRAM memory blocks of the DMU are equipped with a parity error detection logic that makes it possible to detect parity errors. In case of a parity error a NMI is generated.
Page 416 Redirection of Data Read Accesses from Code Memory to Internal Data Memory In the TC1796, the complete 64 Kbyte SRAM of the DMU can be used as overlay memory. Sixteen overlay memory blocks within the SRAM with programmable base address and block sizes are supported, and can be individually enabled for overlay functionality.
Page 417 TC1796 System Units (Vol. 1 of 2) Data Memory Unit There are four overlay RAM control registers (DMU_IOCRn, n = 0-3) assigned to control the internal overlay functionality. Each register specifies the start address of an overlayed 2 Kbyte block within the lower 128 Mbytes of segment 10 and 11. This start address can be placed on any 2 Kbyte boundary within the external code memory, using bit field OVPTR.
Page 418 2 bytes or higher. The redirection is done by a modification of the target address as shown in Figure 8-3. If the data size of a DLMB transaction in TC1796 is greater than the selected overlay memory block size, the following behavior will be observed: •...
Page 419: Internal Overlay
TC1796 System Units (Vol. 1 of 2) Data Memory Unit 8.5.1 Internal Overlay For internal overlay, the size of the blocks can be 2 , with n = 1 to 9 (2 to 512 byte). Thus the maximum memory size needed for overlay memory (if all blocks are used with maximum size) is 8 Kbyte.
Page 420: Program Local Memory Bus Interface (Lmi)
TC1796 System Units (Vol. 1 of 2) Data Memory Unit Program Local Memory Bus Interface (LMI) The PLMB (LMI) interface is a unidirectional interface, allowing the DMI/DMU to do data reads and writes into the PLMB-based modules such as e.g. Flash or EBU space.
Page 421 TC1796 System Units (Vol. 1 of 2) Data Memory Unit subsequent fast accesses for data with high locality, and un-cached faster accesses for data with low locality. Write Transactions When a write transaction hits into the read buffer, the buffer content is invalidated. This feature also can be used to flush the buffer contents.
Page 422: Dmu Registers
(x = 0-15) SBRCTR Stand-by SRAM Control Register 00E0 Page 8-12 1) The PMU register short names are extended and referenced in the other parts of the TC1796 User’s Manual with the module name prefix “PMU_”. User’s Manual 8-10 V2.0, 2007-07...
Page 423 TC1796 System Units (Vol. 1 of 2) Data Memory Unit The Module Identification Register ID contains read-only information about the DMU module version. Module Identification Register Reset Value: 002D C0XX 16 15 MODNUM MODTYPE MODREV Field Bits Type Description MODREV...
Page 424 TC1796 System Units (Vol. 1 of 2) Data Memory Unit The Stand-by SRAM Control Register SBRCTR controls the locking and unlocking of the DMU stand-by memory (SBRAM). SBRCTR Stand-by SRAM Control Register Reset Value: 0000 0000 STBSLK STBULK Field Bits...
Page 425 TC1796 System Units (Vol. 1 of 2) Data Memory Unit Field Bits Type Description [31:8] Reserved Read as 0; should be written with 0. For each of the 16 overlay sections (indicated by index x), three registers control the overlay operation: •...
Page 426 IEMS = 0 Internal/Emulation Memory Select This bit indicates the location of the overlay memory. In the TC1796, this bit is always read as 0, indicating that the DMU SRAM is used as overlay memory. DMU SRAM is selected as overlay memory;...
Page 427 TSEG [31:28] rw Target Segment (reserved) This bit field is reserved for future use, to select a segment. In TC1796 implementation, any access to segments 8 , or A will be checked for a valid base address; return 0 if read; should be written with 0.
Page 428 TC1796 System Units (Vol. 1 of 2) Data Memory Unit The Overlay Mask Register x determines the size of the overlay memory block x. It also determines which address bits will participate in the address compare for a block base address and which bits are used from the original target address and which bits are taken from RABRx.OBASE.
Page 429 TC1796 System Units (Vol. 1 of 2) Data Memory Unit Field Bits Type Description OMASK [8:1] Overlay Address Mask This bit field determines two parameters: • Block size of the overlay memory block x • Address bits taken for address generation...
Page 430 TC1796 System Units (Vol. 1 of 2) Data Memory Unit Field Bits Type Description Fixed Values [31:28] Corresponding address bits are not used in the address comparison. Corresponding final address bits are taken from the original address. [27:9] Fixed Values Corresponding address bits are participating in the address comparison.
Page 431: Memory Maps
Memory Maps Memory Maps This chapter gives an overview of the TC1796 memory map, and describes the address locations and access possibilities for the units, memories, and reserved areas as “seen” from the three different on-chip buses’ points of view.
Page 432 TC1796 System Units (Vol. 1 of 2) Memory Maps The DLMB address map shows the system addresses from the point of view of the DLMB master (DMI). Table 9-1 defines the acronyms and other terms that are used in the address maps...
Page 433 TC1796 System Units (Vol. 1 of 2) Memory Maps Table 9-1 Definition of Acronyms and Terms (cont’d) Term Description Only 32-bit word bus accesses are permitted to that register/address range. A bus access generates no bus error, although the bus access points to an undefined address or address range.
Page 434: Contents Of The Segments
From the SPB point of view (PCP, DMA, and Cerberus), this memory segment is reserved in the TC1796. From the PLMB point of view (PMI), this memory segment is reserved in the TC1796. From the DLMB point of view (DMI), this memory segment allows cached accesses to all DMU memories (SRAM and SBRAM).
Page 435 TC1796 System Units (Vol. 1 of 2) Memory Maps From the PLMB point of view (PMI), this memory segment allows non-cached accesses to the external peripheral and emulator space, the PMI scratch-pad RAM and read access to the boot ROM and test ROM (BROM and TROM).
Page 436: Address Map Of The Fpi Bus System
8FE1 FFFF Kbyte 8FE2 0000 Reserved PLMBBE & PLMBBE 8FEF FFFF Kbyte DLMBBE & SPBBE 8FF0 0000 Reserved for TC1796 8FF7 FFFF Kbyte emulation device memory 8FF8 0000 Reserved 8FFF BFFF Kbyte 8FFF C000 8 Kbyte Boot ROM (BROM) access...
Page 437 AFE1 FFFF Kbyte AFE2 0000 Reserved PLMBBE & PLMBBE AFEF FFFF Kbyte DLMBBE & SPBBE AFF0 0000 Reserved for TC1796 AFF7 FFFF Kbyte emulation device memory AFF8 0000 Reserved AFFF BFFF Kbyte AFFF C000 8 Kbyte Boot ROM (BROM) access...
Page 438 TC1796 System Units (Vol. 1 of 2) Memory Maps Table 9-2 SPB/RPB Address Map of Segment 0 to 14 (cont’d) Seg- Address Size Description Access Type ment Range Read Write D000 0000 56 Kbyte DMI Local Data RAM SPBBE SPBBE...
Page 439 TC1796 System Units (Vol. 1 of 2) Memory Maps Table 9-2 SPB/RPB Address Map of Segment 0 to 14 (cont’d) Seg- Address Size Description Access Type ment Range Read Write E000 0000 External Peripheral Space EBU E7FF FFFF Mbyte access...
Page 440: Segment 15
TC1796 System Units (Vol. 1 of 2) Memory Maps 9.3.2 Segment 15 Table 9-3 shows the address map of segment 15 as seen from the SPB and RPB bus masters PCP, DMA, and OCDS. Please note that access in Table 9-3...
Page 441 TC1796 System Units (Vol. 1 of 2) Memory Maps Table 9-3 SPB/RPB Address Map of Segment 15 (cont’d) Unit Unit Unit Access Type Read Write Port 3 F000 0F00 256 byte access access F000 0FFF Port 4 F000 1000 256 byte access...
Page 442 TC1796 System Units (Vol. 1 of 2) Memory Maps Table 9-3 SPB/RPB Address Map of Segment 15 (cont’d) Unit Unit Unit Access Type Read Write Reserved F000 6000 – SPBBE SPBBE F003 FFFF Reserved F004 0000 – SPBBE SPBBE F004 3EFF...
Page 443 TC1796 System Units (Vol. 1 of 2) Memory Maps Table 9-3 SPB/RPB Address Map of Segment 15 (cont’d) Unit Unit Unit Access Type Read Write Dual-Port RAM F010 A000 8 Kbyte access access F010 BFFF Micro Link Interface 0 (MLI0)
Page 444 TC1796 System Units (Vol. 1 of 2) Memory Maps Table 9-3 SPB/RPB Address Map of Segment 15 (cont’d) Unit Unit Unit Access Type Read Write Program Memory Unit (PMU) F800 0500 256 byte access access F800 05FF Reserved F800 0600 –...
Page 445: Address Map Of The Program Local Memory Bus (Plmb)
Data Flash (DFLASH) PLMBBET access 8FE1 FFFF Kbyte 8FE2 0000 Reserved PLMBBET PLMBBET 8FEF FFFF Kbyte 8FF0 0000 Reserved for TC1796 8FF7 FFFF Kbyte emulation device memory 8FF8 0000 Reserved 8FFF BFFF Kbyte 8FFF C000 8 Kbyte Boot ROM (BROM)
Page 446 AFE0 0000 Data Flash (DFLASH) PLMBBET access AFE1 FFFF Kbyte AFE2 0000 Reserved PLMBBET PLMBBET AFEF FFFF Kbyte AFF0 0000 Reserved for TC1796 access access AFF7 FFFF Kbyte emulation device memory AFF8 0000 Reserved PLMBBET PLMBBET AFFF BFFF Kbyte AFFF C000...
Page 447 TC1796 System Units (Vol. 1 of 2) Memory Maps Table 9-4 PLMB Address Map (cont’d) Seg- Address Size Description Action ment Range Read Write D000 0000 56 Kbyte Reserved PLMBBET PLMBBET D000 DFFF (DMI Local Data RAM) D000 E000 8 Kbyte...
Page 448 TC1796 System Units (Vol. 1 of 2) Memory Maps Table 9-4 PLMB Address Map (cont’d) Seg- Address Size Description Action ment Range Read Write F000 0000 Reserved PLMBBET PLMBBET F7FF FFFF Mbyte F800 0000 1 Kbyte External Bus Interface access...
Page 449: Address Map Of The Data Local Memory Bus (Dlmb)
8FE1 FFFF Kbyte 8FE2 0000 Reserved PLMBBET & PLMBBE 8FEF FFFF Kbyte DLMBBET 8FF0 0000 Reserved for TC1796 8FF7 FFFF Kbyte emulation device memory 8FF8 0000 Reserved 8FFF BFFF Kbyte 8FFF C000 8 Kbyte Boot ROM (BROM) access 8FFF DFFF...
Page 450 AFE1 FFFF Kbyte AFE2 0000 Reserved PLMBBET & PLMBBE AFEF FFFF Kbyte DLMBBET AFF0 0000 Reserved for TC1796 AFF7 FFFF Kbyte emulation device memory AFF8 0000 Reserved AFFF BFFF Kbyte AFFF C000 8 Kbyte Boot ROM (BROM) access AFFF DFFF...
Page 451 TC1796 System Units (Vol. 1 of 2) Memory Maps Table 9-5 DLMB Address Map (cont’d) Seg- Addresses Size Description Action ment Read Write D000 0000 DMI Local Data RAM ignore ignore D000 DFFF Kbyte (LDRAM) D000 E000 8 Kbyte DMI Dual-Port RAM...
Page 452: Memory Module Access Restrictions
TC1796 System Units (Vol. 1 of 2) Memory Maps Memory Module Access Restrictions Table 9-6 describes which type of accesses are possible to the different memories in the TC1796. Table 9-6 Possible Memory Accesses Memory Byte Half-word Word Double-word SPRAM –...
Page 453: General Purpose I/O Ports And Peripheral I/O Lines
General Purpose I/O Ports and Peripheral I/O Lines General Purpose I/O Ports and Peripheral I/O Lines The TC1796 has 127 digital General Purpose Input/Output (GPIO) port lines which are connected to the on-chip peripheral units. They are divided into: •...
Page 454: Basic Port Operation
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.1 Basic Port Operation Figure 10-2 is a general block diagram of a TC1796 GPIO port line. Pn_PDRx Pad Driver Mode Registers Pn_IOCR Input/Output Control Register...
Page 455 TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines Each port line has a number of control and data bits, enabling very flexible usage of the line. Each port pin (except Port 10) can be configured for input or output operation. In input mode (default after reset), the output driver is switched off (high-impedance).
Page 456 (class A2) outputs at GPIO ports and all EBU output lines. All GPIO lines of the TC1796 that are used by the GPTA modules (GPTA0, GPTA1, LTCA2) have an emergency stop logic. This logic makes it possible to individually disconnect GPTA outputs from the driving GPTA module outputs and to put them onto a well defined logic state in an emergency case.
Page 457: Port Register Description
MCA05654 Figure 10-3 Port Registers Note: The complete address map of the GPIO ports is described in the Chapter 18 “Register Overview” of this TC1796 System Units (Vol. 1 of 2) User’s Manual. Table 10-1 Registers Address Space Module Base Address...
Page 458 TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines Table 10-1 Registers Address Space Module Base Address End Address Note F000 1500 F000 15FF – F000 1600 F000 16FF – Table 10-2 Registers Overview...
Page 459: Port Input/Output Control Registers
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.2.1 Port Input/Output Control Registers The port input/output control registers select the digital output and input driver functionality and characteristics of a GPIO port pin. Port direction (input or output), pull- up or pull-down devices for inputs, and push-pull or open-drain functionality for outputs can be selected by the corresponding bit fields PCx (x = 0-15).
Page 460 TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines Pn_IOCR4 Port n Input/Output Control Register 4 Reset Value: 2020 2020 28 27 24 23 20 19 16 15 12 11 Field Bits Type Description...
Page 461 TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines Pn_IOCR12 Port n Input/Output Control Register 12 Reset Value: 2020 2020 28 27 24 23 20 19 16 15 12 11 PC15 PC14 PC13 PC12...
Page 462: Pad Driver Mode Register
Pad Driver Mode Register Overview The pad structure of the TC1796 GPIO lines offers the possibility to select the output driver strength and the slew rate. These two parameters are controlled by the bit fields in the pad driver mode register Pn_PDR, independently from input/output and pull- up/pull-down control functionality as programmed in the Pn_IOCR register.
Page 463 (see Page 5-41). Note: Please refer to the TC1796 Data Sheet for detailed DC characteristics of class A1 and class A2 pads. In addition to the pad driver mode register control selections, a temperature compensation logic, which is a part of the system control unit (SCU), makes it possible to adjust the edges of the high-speed class A2 GPIO output lines depending on the die temperature.
Page 464 TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines Further details of the temperature compensation logic are described in Section 5.6 on Page 5-41 (SCU) of this User’s Manual. Pad Driver Mode Register Example: Port 0 Pad Driver Mode Register...
Page 465: Port Output Register
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines Further details of the temperature compensation logic are described in Section 5.6 Page 5-41 (SCU) of this User’s Manual. 10.2.3 Port Output Register The port output register determines the value of a GPIO pin when it is selected by Pn_IOCRx as output.
Page 466: Port Output Modification Register
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.2.4 Port Output Modification Register The port output modification register contains control bits that make it possible to individually set, clear, or toggle the logic state of a single port line by manipulating the output register.
Page 467 TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines Table 10-5 Function of the Bits PRx and PSx Function Bit Pn_OUT.Px is not changed. Bit Pn_OUT.Px is set. Bit Pn_OUT.Px is cleared. Bit Pn_OUT.Px is toggled.
Page 468: Emergency Stop Register
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.2.5 Emergency Stop Register All GPIO lines which are used by the GPTA modules (GPTA0, GPTA1, LTCA2) have an emergency stop logic implemented (see Figure 10-2).
Page 469: Port Input Register
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines Note: Only Port 3 and 4 are 16-bit wide ports used by the GPTA modules. The Pn_ESR registers of the other ports have a reduced number of bits (see Pn_ESR register descriptions in the corresponding port sections).
Page 470: Port 0 Configuration
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.3 Port 0 This section describes the Port 0 functionality in detail. 10.3.1 Port 0 Configuration Port 0 is a general-purpose 16-bit bi-directional port. It serves as GPIO lines without secondary functions.
Page 471: Port 0 Function Table
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.3.2 Port 0 Function Table Table 10-6 summarizes the I/O control selection functions of each Port 0 line. Table 10-6 Port 0 Functions Port I/O Pin Functionality Associated Reg./...
Page 472 TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines Table 10-6 Port 0 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Field Value P0.6 General-purpose input P0_IN.P6 P0_IOCR4.PC6...
Page 473 TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines Table 10-6 Port 0 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Field Value P0.12 I General-purpose input P0_IN.P12...
Page 474: Port 0 Registers
2) This register is located in the address range of the SCU. Note: The complete address map of Port 0 is described in Table 18-9 Page 18-22 this TC1796 System Units (Vol. 1 of 2) User’s Manual. User’s Manual 10-22 V2.0, 2007-07...
Page 475: Port 0 Pad Driver Mode Register And Pad Classes
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.3.3.1 Port 0 Pad Driver Mode Register and Pad Classes The Port 0 pad driver mode register contains two bit fields that determine the pad driver mode (output driver strength and slew rate) of Port 0 line groups.
Page 476: Port 0 Software Configuration Selection
(at the rising edge of HDRST). This feature makes it possible to use Port 0 lines for software configuration selection purposes. Depending on the TC1796 device used, several of the SWOPT bits (meaning several of the P0 lines) are reserved and may not be used by a user program for software configuration selection purposes.
Page 477: Reserved Swopt Bits Of Scu_Sclir Register
General Purpose I/O Ports and Peripheral I/O Lines 10.3.3.3 Reserved SWOPT Bits of SCU_SCLIR Register Depending on the TC1796 device version used in an application, several Port 0 lines (meaning several SWOPT bits) are reserved and cannot be used for user system purposes during a HDRST reset operation.
Page 478: Port 1
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.4 Port 1 This section describes the Port 1 functionality in detail. 10.4.1 Port 1 Configuration Port 1 is a 16-bit bi-directional general-purpose I/O port that can be alternatively used for the MLI0 I/O lines or for the external trigger inputs REQ[3:0] of the CPU.
Page 479: Port 1 Function Table
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.4.2 Port 1 Function Table Table 10-9 summarizes the I/O control selection functions of each Port 1 line. Table 10-9 Port 1 Functions Port I/O Pin Functionality Associated Reg./...
Page 480 TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines Table 10-9 Port 1 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Field Value P1.4 General-purpose input P1_IN.P4 P1_IOCR4.PC4...
Page 481 TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines Table 10-9 Port 1 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Field Value P1.9 General-purpose input P1_IN.P9 P1_IOCR8.PC9...
Page 482: Port 1 Registers
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines Table 10-9 Port 1 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Field Value P1.14 I General-purpose input P1_IN.P14...
Page 483: Port 1 Pad Driver Mode Register And Pad Classes
Table 18-10 Page 18-23 of this TC1796 System Units (Vol. 1 of 2) User’s Manual. 10.4.3.1 Port 1 Pad Driver Mode Register and Pad Classes The Port 1 pad driver mode register contains four bit fields that determine the pad driver mode (output driver strength and slew rate) of Port 1 lines and line groups.
Page 484: Port 2
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.5 Port 2 This section describes the Port 2 functionality in detail. 10.5.1 Port 2 Configuration Port 2 is a 14-bit bi-directional general-purpose I/O port that can be used either for the SSC0/SSC1 chip select output lines or for MSC0/MSC1 or GPTA0/GPTA1/LTCA2 I/O lines.
Page 485: Port 2 Function Table
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.5.2 Port 2 Function Table Table 10-11 summarizes the I/O control selection functions of each Port 2 line. Table 10-11 Port 2 Functions Port I/O Pin Functionality Associated Reg./...
Page 486 TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines Table 10-11 Port 2 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Field Value P2.6 General-purpose input P2_IN.P6 P2_IOCR4.PC6...
Page 487 TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines Table 10-11 Port 2 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Field Value P2.10 I General-purpose input P2_IN.P10...
Page 488 TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines Table 10-11 Port 2 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Field Value P2.14 I General-purpose input P2_IN.P14...
Page 489: Port 2 Registers
Note: The complete address map of Port 2 is described in Table 18-11 Page 18-24 of this TC1796 System Units (Vol. 1 of 2) User’s Manual. 10.5.3.1 Port 2 Output Register The basic P2_OUT register functionality is described on Page 10-13.
Page 490: Port 2 Input/Output Control Register 0
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.5.3.3 Port 2 Input/Output Control Register 0 Port lines P2.0 and P2.1 are not available. Therefore, the PC0 and PC1 bit fields in register P2_IOCR0 are not connected to any port lines.
Page 491: Port 2 Pad Driver Mode Register And Pad Classes
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.5.3.6 Port 2 Pad Driver Mode Register and Pad Classes The Port 2 pad driver mode register contains four bit fields that determine the pad driver mode (output driver strength and slew rate) of Port 2 line groups.
Page 492: Port 3
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.6 Port 3 This section describes the Port 3 functionality in detail. 10.6.1 Port 3 Configuration Port 3 is a 16-bit bi-directional general-purpose I/O port that can be used for the GPTA0/GPTA1/LTCA2 I/O lines.
Page 493: Port 3 Function Table
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.6.2 Port 3 Function Table Table 10-13 summarizes the I/O control selection functions of each Port 3 line. Table 10-13 Port 3 Functions Port I/O Pin Functionality Associated Reg./...
Page 494 TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines Table 10-13 Port 3 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Field Value P3.4 General-purpose input P3_IN.P4 P3_IOCR4.PC4...
Page 495 TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines Table 10-13 Port 3 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Field Value P3.8 General-purpose input P3_IN.P8 P3_IOCR8.PC8...
Page 496 TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines Table 10-13 Port 3 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Field Value P3.12 I General-purpose input P3_IN.P12...
Page 497: Port 3 Registers
1) This register is listed here in the Port 3 section because they differ from the general port register description given in Section 10.2. Note: The complete address map of Port 3 is described in Table 18-12 Page 18-25 of this TC1796 System Units (Vol. 1 of 2) User’s Manual. User’s Manual 10-45 V2.0, 2007-07 Ports, V2.0...
Page 498: Port 3 Pad Driver Mode Register And Pad Classes
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.6.3.1 Port 3 Pad Driver Mode Register and Pad Classes The Port 3 pad driver mode register contains two bit fields that determine the pad driver mode (output driver strength and slew rate) of Port 3 line groups.
Page 499: Port 4
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.7 Port 4 This section describes the Port 4 functionality in detail. 10.7.1 Port 4 Configuration Port 4 is a 16-bit bi-directional general-purpose I/O port that can be used for the GPTA0/GPTA1/LTCA2 I/O lines.
Page 500: Port 4 Function Table
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.7.2 Port 4 Function Table Table 10-15 summarizes the I/O control selection functions of each Port 4 line. Table 10-15 Port 4 Functions Port I/O Pin Functionality Associated Reg./...
Page 501 TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines Table 10-15 Port 4 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Field Value P4.4 General-purpose input P4_IN.P4 P4_IOCR4.PC4...
Page 502 TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines Table 10-15 Port 4 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Field Value P4.8 General-purpose input P4_IN.P8 P4_IOCR8.PC8...
Page 503: Port 4 Registers
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines Table 10-15 Port 4 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Field Value P4.12 I General-purpose input P4_IN.P12...
Page 504 1) This register is listed here in the Port 4 section because they differ from the general port register description given in Section 10.2. Note: The complete address map of Port 4 is described in Table 18-13 Page 18-26 of this TC1796 System Units (Vol. 1 of 2) User’s Manual. User’s Manual 10-52 V2.0, 2007-07 Ports, V2.0...
Page 505: Port 4 Pad Driver Mode Register And Pad Classes
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.7.3.1 Port 4 Pad Driver Mode Register and Pad Classes The Port 4 pad driver mode register contains two bit fields that determine the pad driver mode (output driver strength and slew rate) of Port 4 lines and line groups.
Page 506: Port 5
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.8 Port 5 This section describes the Port 5 functionality in detail. 10.8.1 Port 5 Configuration Port 5 is an 8-bit bi-directional general-purpose I/O port which can be used for the ASC0/ASC1, MSC0/MSC1, or MLI0 interface I/O lines.
Page 507: Port 5 Function Table
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.8.2 Port 5 Function Table Table 10-17 summarizes the I/O control selection functions of each Port 5 line. Table 10-17 Port 5 Functions Port I/O Pin Functionality Associated Reg./...
Page 508 TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines Table 10-17 Port 5 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Field Value P5.5 General-purpose input P5_IN.P5 P5_IOCR4.PC5 0XXX...
Page 509: Port 5 Registers
Note: The complete address map of Port 5 is described in Table 18-14 Page 18-27 of this TC1796 System Units (Vol. 1 of 2) User’s Manual. 10.8.3.1 Port 5 Output Register The basic P5_OUT register functionality is described on Page 10-13.
Page 510: Port 5 Pad Driver Mode Register And Pad Classes
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.8.3.4 Port 5 Pad Driver Mode Register and Pad Classes The Port 5 pad driver mode register contains four bit fields that determine the pad driver mode (output driver strength and slew rate) of Port 5 line groups.
Page 511: Port 6 Configuration
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.9 Port 6 This section describes the Port 6 functionality in detail. 10.9.1 Port 6 Configuration Port 6 is a 12-bit bi-directional general-purpose I/O port which can be used for the SSC1, ASC0/ASC1, or for the MultiCAN controller I/O lines.
Page 512: Port 6 Function Table
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.9.2 Port 6 Function Table Table 10-19 summarizes the I/O control selection functions of each Port 6 line. Table 10-19 Port 6 Functions Port I/O Pin Functionality Associated Reg./...
Page 513 TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines Table 10-19 Port 6 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Field Value P6.8 General-purpose input P6_IN.P8 P6_IOCR8.PC8...
Page 514 TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines Table 10-19 Port 6 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Field Value P6.12 I General-purpose input P6_IN.P12...
Page 515: Port 6 Registers
Note: The complete address map of Port 6 is described in Table 18-15 Page 18-28 of this TC1796 System Units (Vol. 1 of 2) User’s Manual. 10.9.3.1 Port 6 Output Register The basic P6_OUT register functionality is described on Page 10-13.
Page 516: Port 6 Pad Driver Mode Register And Pad Classes
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.9.3.4 Port 6 Pad Driver Mode Register and Pad Classes The Port 6 pad driver mode register contains three bit fields that determine the pad driver mode (output driver strength and slew rate) of Port 6 line groups.
Page 517: Port 7
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.10 Port 7 This section describes the Port 7 functionality in detail. 10.10.1 Port 7 Configuration Port 7 is an 8-bit bi-directional general-purpose I/O port that can be used for the external trigger input lines REQ[7:4] or for the ADC0/ADC1 external multiplexer control output lines.
Page 518: Port 7 Function Table
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.10.2 Port 7 Function Table Table 10-21 summarizes the I/O control selection functions of each Port 7 line. Table 10-21 Port 7 Functions Port I/O Pin Functionality Associated Reg./...
Page 519 TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines Table 10-21 Port 7 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Field Value P7.5 General-purpose input P7_IN.P5 P7_IOCR4.PC5...
Page 520: Port 7 Registers
Note: The complete address map of Port 7 is described in Table 18-16 Page 18-29 of this TC1796 System Units (Vol. 1 of 2) User’s Manual. 10.10.3.1 Port 7 Output Register The basic P7_OUT register functionality is described on Page 10-13.
Page 521: Port 7 Pad Driver Mode Register And Pad Classes
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.10.3.4 Port 7 Pad Driver Mode Register and Pad Classes The Port 7 pad driver mode register contains one bit field that determines the pad driver mode (output driver strength and slew rate) of the Port 7 lines.
Page 522: Port 8
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.11 Port 8 This section describes the Port 8 functionality in detail. 10.11.1 Port 8 Configuration Port 8 is an 8-bit bi-directional general-purpose I/O port which can be used for the MLI1 interface lines or for the GPTA0/GPTA1 I/O lines.
Page 523: Port 8 Function Table
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.11.2 Port 8 Function Table Table 10-23 summarizes the I/O control selection functions of each Port 8 line. Table 10-23 Port 8 Functions Port I/O Pin Functionality Associated Reg./...
Page 524 TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines Table 10-23 Port 8 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Field Value P8.4 General-purpose input P8_IN.P4 P8_IOCR4.PC4...
Page 525: Port 8 Register
Note: The complete address map of Port 8 is described in Table 18-17 Page 18-30 of this TC1796 System Units (Vol. 1 of 2) User’s Manual. 10.11.3.1 Port 8 Output Register The basic P8_OUT register functionality is described on Page 10-13.
Page 526: Port 8 Pad Driver Mode Register And Pad Classes
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.11.3.5 Port 8 Pad Driver Mode Register and Pad Classes The Port 8 pad driver mode register contains two bit fields that determine the pad driver mode (output driver strength and slew rate) of Port 8 lines and line groups.
Page 527: Port 9
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.12 Port 9 This section describes the Port 9 functionality in detail. 10.12.1 Port 9 Configuration Port 9 is a 9-bit bi-directional general-purpose I/O port which can be used for the MSC0/MSC1 interface output lines or for the GPTA0/GPTA1 I/O lines.
Page 528: Port 9 Function Table
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.12.2 Port 9 Function Table Table 10-25 summarizes the I/O control selection functions of each Port 9 line. Table 10-25 Port 9 Functions Port I/O Pin Functionality Associated Reg./...
Page 529 TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines Table 10-25 Port 9 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Field Value P9.4 General-purpose input P9_IN.P4 P9_IOCR4.PC4...
Page 530: Port 9 Register
Note: The complete address map of Port 9 is described in Table 18-18 Page 18-31 of this TC1796 System Units (Vol. 1 of 2) User’s Manual. 10.12.3.1 Port 9 Output Register The basic P9_OUT register functionality is described on Page 10-13.
Page 531: Port 9 Input/Output Control Register 8
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.12.3.3 Port 9 Input/Output Control Register 8 P9_IOCR8 Port 9 Input/Output Control Register 8 Reset Value: 0000 0020 Field Bits Type Description [7:4] Port Control for P9.8 This bit field determines the P9.8 functionality.
Page 532: Port 9 Pad Driver Mode Register And Pad Classes
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.12.3.6 Port 9 Pad Driver Mode Register and Pad Classes The Port 9 pad driver mode register contains three bit fields that determine the pad driver mode (output driver strength and slew rate) of Port 9 lines.
Page 533: Port 10 (Hardware Select Inputs)
HWCFG in the reset status register RTS_SR. The four input lines of Port 10 have weak pull-up devices connected (always active). Inside the TC1796, the HWCFG[3:0] lines are used for boot configuration selection. Input P10.1 (HWCFG1) operates as emergency stop input for the GPTA modules. The emergency stop control logic is described in detail in the “System Control Unit”...
Page 534: Port 10 Registers
Table 18-19 Page 18-32 of this TC1796 System Units (Vol. 1 of 2) User’s Manual. Note: Bit field HWCFG in register RST_SR contains the latched logic levels of the Port 10 inputs that were detected at the last low-to-high transition of HDRST.
Page 535: Dedicated Peripheral I/O Lines
10.14.1 Dedicated I/O Lines for SSC0 and SSC1 In the TC1796 the Synchronous Serial interface SSC0 is directly connected to dedicated pins. Bits SSC0_CON.EN (signal “SSC Enabled”) enables/disables these dedicated pins. After a reset, SSC0_CON.EN is 0 and the dedicated SSC0 I/O pins are tri-stated.
Page 536 TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines Table 10-28 SSC0 Dedicated I/O Line Selection and Setup (cont’d) Dedicated SSC0 Input/ SSC0 Input/Output Enable Pad Driver Port Line Output Mode Selection Control Control...
Page 537: Lvds Outputs Of Msc0 And Msc1
TC1796 System Units (Vol. 1 of 2) General Purpose I/O Ports and Peripheral I/O Lines 10.14.2 LVDS Outputs of MSC0 and MSC1 The clock and data output lines of MSC0 and MSC1 are connected to dedicated differential output drivers, each of which has positive and negative signal polarity. These types of 3.3V LVDS pads are assigned as class C pads.
Page 538: Peripheral Control Processor (Pcp)
11.1 Peripheral Control Processor Overview The PCP in the TC1796 performs tasks that would normally be performed by the combination of a DMA controller and its supporting CPU interrupt service routines in a traditional computer system. It could easily be considered as the host processor’s first line of defence as an interrupt-handling engine.
Page 539: Pcp Architecture
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.2 PCP Architecture The PCP is made up of several modular blocks as follows. Please refer to Figure 11-1. • PCP Processor Core • Code Memory (CMEM) with parity protection •...
Page 540: Pcp Processor
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.2.1 PCP Processor The PCP Processor is the main engine of the PCP. It contains an instruction pipeline, a set of GPRs, an arithmetic/logic unit, as well as control and status registers and logic. Its instruction set is optimized especially for the tasks it has to perform.
Page 541: Pcp Code Memory
Page 11-125 for the implemented type and size of the code memory in the TC1796. The PCP CMEM is viewed from the FPI Bus as a 32-bit wide memory, that must be accessed with 32-bit (word) accesses, and is addressed with byte addresses. Thus, care has to be taken when calculating PCP instruction FPI addresses.
Page 542: Pcp Interrupt Control Unit And Service Request Nodes
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) access. If an FPI Bus master performs an atomic read-modify-write access to a PCP memory block, any concurrent PCP access to that block is stalled for the duration of the atomic operation.
Page 543: Pcp Programming Model
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.3 PCP Programming Model The PCP programming model can be viewed as a set of autonomous programs, or tasks, called channel programs, that share the processing resources of the PCP. channel programs may be short and simple, or very complex;...
Page 544: Register R0
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) R7 is the only one of the eight registers that may not be used as a full GPR. The most significant 16 bits of R7 may not be written, and will always read back as 0. However, no error will occur when writing to the most significant 16 bits.
Page 545: Register R6
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.3.1.4 Register R6 Register R6 may also be used as a general-use register. Again however, there are some instructions that use fields within R6. If the COPY or EXIT instructions are used, then the field R6.CNT1 can optionally be used implicitly as a counter.
Page 546: Register R7
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.3.1.5 Register R7 Register R7 is an exception with respect to the other registers in that not all bits within the register can be written, and the implicit use of the remaining bits virtually excludes the use of R7 as a GPR.
Page 547 TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) PCP Register R7 Reset Value: 0000 0000 DPTR – CEN IEN CNZ Field Bits Type Description Zero Negative Carry Overflow Outer Loop Counter 1 Zero Flag Interrupt Enable Channel is not interruptible...
Page 548: Contexts And Context Models
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.3.2 Contexts and Context Models After initialization, the instruction sequence of a PCP channel program is permanently stored (i.e. usually at least as long as the application is running) in the CMEM, and data parameters are held in the PRAM.
Page 549 TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) To distinguish the actual register contents from the copies stored in the PRAM context regions, the term CRx is used throughout the rest of this document to refer to the register values in the context regions.
Page 550 TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) Stored Context in PRAM PCP Register Set Restore Full Context 8 Words Save Small Context Restore 4 Words Save Minimum Context Restore 2 Words Save MCA05667 Figure 11-2 PCP Context Models User’s Manual...
Page 551: Context Save Area
PRAM in the TC1796. As an example, a PRAM of 2 Kbytes, solely used for the CSA, can store up to 255 Minimum Contexts, allowing the highest SRPN used for a PCP service request to be 255 (remember, an SRPN of 0 and an associated context region is never used;...
Page 552 TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) If portions of the PRAM are used for other variables and global data, the space available for the CSA and the range of valid SRPNs is reduced by the memory space required for this data.
Page 553 TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) Full Context Small Context Minimum Context PRAM PRAM PRAM Memory Memory Memory Context SRPN = n1 n1×8 Context SRPN = n2 n2×4 Context SRPN = n3 Context n3×2 SRPN = 2...
Page 554: Context Restore Operation For Cr6 And Cr7
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) the Full Context, and only some would require more context to be saved. In this case, a smaller Context Model can be used, and the channels which would require more register to be saved/restored would do this via explicit load and store instructions.
Page 555 TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) Channel Resume Mode Figure 11-4 illustrates the operation of a context restore for a “new” channel program when Channel Resume Mode has been selected (see Page 11-26). The PC is loaded from CR7[31:16], and the lower half of R7 is loaded from CR7[15:0].
Page 556 TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) Channel Restart Mode Figure 11-5 illustrates the operation of a context restore for a “new” channel program when Channel Restart Mode has been selected (see Page 11-25). The PC is loaded with the channel entry table address, and the lower half of R7 is loaded from CR7[15:0].
Page 557 TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) Suspended Channel Restart Figure 11-6 illustrates the operation of a context restore for a “suspended” channel program. The PC is loaded from CR7[31:16] (regardless of the Channel Start Mode), and the lower half of R7 is loaded from CR7[15:0].
Page 558: Context Save Operation For Cr6 And Cr7
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.3.2.4 Context Save Operation for CR6 and CR7 The operation of R6 and R7 context save varies according to whether the save operation is the result of a channel exit condition, or whether the channel is being suspended in favor of a higher-priority channel program.
Page 559 TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) Channel Restart Mode Figure 11-8 illustrates the operation of a context save for a channel exit when Channel Restart Mode has been selected.This is the same as for Channel Resume mode except that the PC value is discarded, and the appropriate Channel Entry Table address is written to CR7[31:16].
Page 560 TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) Channel Suspend Figure 11-9 illustrates the operation of a context save for a channel that is being suspended. This is the same as for Channel Resume mode except that an interrupt request is created to allow the channel to be restarted at a later time.
Page 561: Initialization Of The Contexts
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.3.2.5 Initialization of the Contexts The programmer is responsible for configuring each channel program’s context before commencing operation. Because this must be done by writing to the PCP across the FPI Bus, it is important to understand exactly where each channel program’s context is from...
Page 562: Channel Programs
PCP channels. The individual channel programs for the individual PCP service requests can usually be viewed as independent and separate programs. There is no background program defined and running for the PCP in TC1796 as there would be with traditional processors.
Page 563: Channel Resume Mode
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) It is recommended that all EXIT instructions for all channels should use the EP = 0 setting when the PCP is operated in Channel Restart Mode (see Page 11-89).
Page 564 TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) Channel Restart Mode Channel Resume Mode Code Memory Code Memory CMEM CMEM Channel #2 Main Code Channel #n1 Main Code Channel #2 Main Code Channel #3 Main Code Channel #n1...
Page 565: Pcp Operation
11.4.1 PCP Initialization The PCP is placed in a quiescent state when the TC1796 is first powered-on or reset. Before a channel program can be enabled, the PCP as a whole must be initialized by some other FPI Bus master, typically the CPU. Initialization steps include: •...
Page 566: Channel Exit And Context Save Operation
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) After the channel program starts, the value of R6 may be changed without altering the value of the effective CPPN, because updates to the value of R6.CPPN have no effect until the next invocation of the channel program.
Page 567: Error Condition Channel Exit
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) • If ST = 1 is specified bit R7.CEN (Channel Enable) is cleared (i.e. the channel is disabled). • If EP = 0 is specified or PCP_CS.RCB = 1 (Channel Restart Mode has been selected), the PCP program counter to be saved to context location CR7.PC is set to...
Page 568: Debug Exit
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) • The PC of the instruction that was executing when the error occurred is stored in PCP_ES.EPC. • The number of the channel program that was executing when the error occurred is stored in PCP_ES.EPN.
Page 569: Pcp Interrupt Operation
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) Note: The DEBUG instruction must be only used in DEBUG mode; otherwise an “Illegal Operation” (IOP) error will be generated. 11.5 PCP Interrupt Operation The PICU and the PSRNs (PCP_SRC[11:0]) are similar to the CPU’s ICU and all other SRNs in the system.
Page 570: Pcp Interrupt Control Unit
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) service requests by performing an FPI Bus write operation to an external service request node (SRN). Alternately, the PCP can raise a service request using one of its own internal SRN’s.
Page 571: Issuing Pcp Service Requests
(x = 4 to 8) with a TOS value representing a non-available interrupt bus or 11 in the TC1796) will disable Service Request Node x. The actual service request flag and the service request priority number of the PCP_SRCx registers are updated by the PCP when it generates an implicit service request.
Page 572: Service Request On Exit Instruction
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.5.4.1 Service Request on EXIT Instruction An implicit PCP service request is issued when the INT field of the EXIT instruction is set to 1 and the specified condition code, cc_B, of this instruction is true. Such a service request can be issued to any of the available interrupt buses, depending on the programmed value in the TOS field of register R6.
Page 573: Service Request On Error
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.5.4.3 Service Request on Error While a service request triggered through an EXIT instruction is optional and can be issued either to the CPU or to the PCP itself, a service request due to an error condition will always be automatically issued and will always be directed to the CPU.
Page 574 TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) lower than those of the PCP queue. In this way, it is guaranteed that one entry in the PCP queue gets serviced, freeing one slot in the queue. The PCP programmer needs to carefully consider this special operation. It ensures that...
Page 575: Pcp Error Handling
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.6 PCP Error Handling The PCP contains a number of fail-safe mechanisms to ensure that error conditions are handled gracefully and predictably. In addition to providing an extra level of system robustness suitable for high integrity and safety-critical systems, these mechanisms can often ease the task of finding programming errors during the development process.
Page 576: Channel Watchdog
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) Note: Enabling PRAM partitioning (PCP_CS.PPE = 1) with a CSA size of zero (PCP_CS.PPS = 0) is an invalid setting and will cause a PCP error event whenever any interrupt request is received by the PCP.
Page 577: Instruction Set Overview
11.7 Instruction Set Overview The following sections present an overview of the instruction set and the available addressing modes of the PCP in the TC1796. 11.7.1 DMA Primitives Table 11-3 DMA Transfer Instructions...
Page 578: Load And Store
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.7.2 Load and Store Note: If a conditional instruction’s condition code is false, the operation will be treated as a “No Operation”. Register values will not be changed and the flags will not be updated.
Page 579: Arithmetic And Logical Instructions
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.7.3 Arithmetic and Logical Instructions Arithmetic instructions that are fully register-based execute conditionally depending on the specified Condition Code A (see Page 11-73). All other arithmetic instructions such as PRAM (.PI), indirect (.I), and FPI (.F and .IF) execute unconditionally.
Page 580 TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) Table 11-6 Logical Instructions Logical Register AND register (conditionally) AND.F Content of FPI Bus address location AND register (byte, half-word or word) AND.PI Content of PRAM address location AND register MCLR.PI Clear specified bits within a PRAM location...
Page 581: Bit Manipulation
Set carry flag depending on value of specified register bit 11.7.5 Flow Control Table 11-8 describes flow control instructions of the PCP in the TC1796. Table 11-8 Flow Control Instructions Jump Jump conditionally to PC + short immediate offset address JC.A...
Page 582: Addressing Modes
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.7.6 Addressing Modes The PCP needs to address locations in memory in different ways, as determined by the type of memory being accessed and the type of action being performed on that location.
Page 583: Pram Addressing
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.7.6.2 PRAM Addressing The PRAM is always addressed indirectly by the PCP. The normal address used is the value of the R7.DPTR field (8 bits) concatenated with an immediate 6-bit offset value encoded in the instruction, yielding a 14-bit word address.
Page 584 TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) • Effective JUMP Address[15:0] = NextPC + Sign-Extend(#offset6); +/- 32 instructions The function NextPC indicates the instruction that would be fetched next by the program counter. Instructions using this addressing are JL, JC and JC.I.
Page 585: Accessing Pcp Resources From The Fpi Bus
11.8 Accessing PCP Resources from the FPI Bus Any FPI Bus master (on the TC1796’s System Peripheral Bus) can access the three distinct PCP address ranges from the FPI Bus side. Normally, the CPU initializes the control registers via FPI Bus access. Thereafter, the PCP should not access its control registers itself through PCP instructions.
Page 586: Access To The Cmem
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) Note: Since channel 0 is not defined (no service request with SRPN = 0), the first area is not an actual CSA. It is recommended that this area should not be used by PCP channel programs.
Page 587: Debugging The Pcp
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.9 Debugging the PCP For debugging the PCP, a special instruction, DEBUG, is provided. This instruction can only be used when the PCP is in Debug Mode. It can be placed at important locations inside the code to track and trace program execution.
Page 588 TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) included in the context will not be saved, and indeed these register values may be changed by the operation of another active channel. In this case, the required registers should be explicitly saved to PRAM by store instructions prior to execution of the DEBUG instruction.
Page 589: Pcp Registers
Figure 11-12 PCP Registers The complete address map of the PCP is described in Table 18-25 Page 18-77 this TC1796 System Units (Vol. 1 of 2) User’s Manual. Table 11-10 Registers Address Space - PCP Registers Module Base Address End Address...
Page 590 TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) Table 11-11 Registers Overview - PCP Registers Register Register Long Name Offset Description Short Name Address PCP_CLC PCP Clock Control Register 0000 Page 11-55 PCP_ID PCP Module Identification Register...
Page 591: Module Identification Register, Pcp_Id
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.10.1 Module Identification Register, PCP_ID The PCP Module Identification Register ID contains read-only information about the PCP module version. PCP_ID PCP Module Identification Register (008 Reset Value: 0020 C0XX...
Page 592: Pcp Clock Control Register, Pcp_Clc
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.10.2 PCP Clock Control Register, PCP_CLC PCP_CLC PCP Clock Control Register Reset Value: 0000 0000 Field Bits Type Description PCGDIS Clock Gating Disable Bit Allows clock gating to be disabled.
Page 593: Pcp Control And Status Register, Pcp_Cs
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.10.3 PCP Control and Status Register, PCP_CS This register can be Endinit-protected via bit EIE. PCP_CS PCP Control/Status Register Reset Value: 0000 0000 EIE RCB RS RST EN Field...
Page 594 TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) Field Bits Type Description Channel Start Mode Control Channel resume operation mode selected; channel start PC is taken from restored context Channel restart operation mode selected; channel start PC is derived from the requested...
Page 595 TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) Field Bits Type Description [15:9] PRAM Partition Size Default, only allowed with PPE = 0 000CSA contains 3 context save regions CSA contains 1 + 2 × n context save regions Note: The actual size of the CSA (in words) is given by ×...
Page 596: Pcp Error/Debug Status Register, Pcp_Es
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.10.4 PCP Error/Debug Status Register, PCP_ES This is a read-only register, providing state information about error and debug conditions. PCP_ES PCP Error/Debug Status Register Reset Value: 0000 0000 PPC CWD...
Page 597 TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) Field Bits Type Description Instruction Address Error Set if the last error/debug event was an error generated by the PCP attempting to fetch an instruction from an address outside the implemented CMEM range as a result of a jump or branch instruction;...
Page 598: Pcp Interrupt Control Register, Pcp_Icr
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) contents of the register are updated whenever there is a debug or an error event detected (i.e. all status/error bits, other than the bit representing the last PCP error/debug event, are cleared). This register therefore only provides a record of the last error/debug event encountered.
Page 599 TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) Field Bits Type Description PARBCYC [25:24] rw Number of Arbitration Cycles Control This bit field controls the number of arbitration cycles used to determine the request with the highest priority.
Page 600: Pcp Interrupt Threshold Register, Pcp_Itr
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.10.6 PCP Interrupt Threshold Register, PCP_ITR PCP_ITR PCP Interrupt Threshold Control Register Reset Value: 0000 0000 Field Bits Type Description [7:0] PCP Interrupt Threshold Service Request Priority Number This field contains the interrupt priority that is to be...
Page 601: Pcp Interrupt Configuration Register, Pcp_Icon
PCP Interrupt Bus 2 TOS Mapping This field reflects the TOS associated with interrupt bus 2. Note: Interrupt bus 2 is not available in the TC1796. [7:6] PCP Interrupt Bus 3 TOS Mapping This field reflects the TOS associated with interrupt bus 3.
Page 602 TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) Field Bits Type Description IP1E PCP Interrupt Bus 1 Enable This bit reflects the status of interrupt bus 1 (PCP interrupt arbitration bus). Interrupt bus 1 is always enabled.
Page 603: Pcp Stall Status Register, Pcp_Ssr
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.10.8 PCP Stall Status Register, PCP_SSR PCP_SSR PCP Stall Status Register Reset Value: 0000 0000 SCHN STOS SSRN Field Bits Type Description SSRN [7:0] PCP Stalled Service Request Number...
Page 604: Pcp Service Request Control Registers, Pcp_Src[1:0]
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.10.9 PCP Service Request Control Registers, PCP_SRC[1:0] Service request nodes for interrupt bus 0 (CPU interrupt arbitration bus). PCP_SRCx (x = 0-1) PCP Service Request Control Register x -x*4...
Page 605: Pcp Service Request Control Registers, Pcp_Src[3:2]
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.10.10 PCP Service Request Control Registers, PCP_SRC[3:2] Service request nodes for interrupt bus 1 (PCP interrupt arbitration bus). PCP_SRC2 PCP Service Request Control Register 2 Reset Value: 0000 1400...
Page 606: Pcp Service Request Control Registers, Pcp_Src[8:4]
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.10.11 PCP Service Request Control Registers, PCP_SRC[8:4] Service request nodes programmable for interrupt bus 0 (CPU interrupt arbitration bus) or 1 (PCP interrupt arbitration bus). PCP_SRCx (x = 4-8)
Page 607: Pcp Service Request Control Registers, Pcp_Src[11:9]
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.10.12 PCP Service Request Control Registers, PCP_SRC[11:9] Service request nodes for interrupt bus 1 (PCP interrupt arbitration bus) with suspended interrupt capability. PCP_SRCx (x = 9-11) PCP Service Request Control Register x...
Page 608 TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) Field Bits Type Description PCP Node x Service Request Flag No service requested (default) Valid active service requested SRCN [23:16] PCP Node x Service Request Channel Number Channel Number Entry (default = 0). When the PCP...
Page 609: Pcp Instruction Set Details
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.11 PCP Instruction Set Details This section describes the instruction set architecture of the PCP in detail. 11.11.1 Instruction Codes and Fields All PCP instructions use a common set of fields to describe such things as the source register, and the state of flags.
Page 610: Conditional Codes
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.11.1.1 Conditional Codes Many PCP instructions have the option of being executed conditionally. The condition code of an instruction is the field that specifies the condition to be tested before the instruction is executed.
Page 611: Instruction Fields
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.11.1.2 Instruction Fields Table 11-13 lists the instruction field definitions of the PCP instruction set architecture. Note: The exact syntax for these fields may be different depending on which tool (e.g.
Page 612 TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) Table 11-13 Instruction Field Definitions (cont’d) Symbol Syntax Description Stop PCP DAC = 0 Allow the PCP to continue to execute channel programs in response to service requests. DAC = 1 Prevent the PCP from executing further channel programs (PCP_CS.EN = 0).
Page 613 TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) Table 11-13 Instruction Field Definitions (cont’d) Symbol Syntax Description SRC+- Source Address Pointer Control SRC (00 No Change (SRC) SRC+ (01 Post Increment by Size (SRC+) SRC- (10 Post Decrement by Size (SRC-)
Page 614: Counter Operation For Copy Instruction
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.11.2 Counter Operation for COPY Instruction COPY Instruction CNT0 := RC0 DATA Transfer CNT0 := CNT0 - 1 CNT0 = 0 ? CNC = ? CNT1 := CNT1 - 1...
Page 615: Counter Operation For Bcopy Instruction
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.11.3 Counter Operation for BCOPY Instruction BCOPY Instruction DATA Transfer (Block size determined by CNT0 field) CNC = ? CNT1 := CNT1 - 1 CNT1 := CNT1 - 1...
Page 616: Divide And Multiply Instructions
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.11.4 Divide and Multiply Instructions The PCP has multiply and divide capabilities (unsigned values only). All multiply and divide instructions operate on 8 bits of data (taken from the dividend for divide, from the multiplicand for multiply).
Page 617: Add, 32-Bit Addition
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) a 40-bit unsigned multiply and then shifts this result right by 8 bits (discards the least significant 8 bits of the 40-bit result). The DSTEP instruction also has some conditions stipulated regarding input values to the instruction.
Page 618: Bcopy, Dma Operation
R5 = R5 +/- n; n depending on DST+- and CNT0 For counter operation see Figure 11-14 Page 11-78 Table 11-13 Page 11-74. Flags CN1Z See also Page 11-127 for TC1796 specific details of the BCOPY instruction. User’s Manual 11-81 V2.0, 2007-07 PCP, V2.0...
Page 619: And, 32-Bit Logical And
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.11.7 AND, 32-Bit Logical AND This section describes the AND instructions of the PCP. Syntax AND Rb, Ra, cc_A Description If the condition CONDCA is true, then perform a bit-wise logical AND of the contents of register Ra and the contents of register Rb;...
Page 620: Chkb, Check Bit
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.11.8 CHKB, Check Bit This section describes the CHKB instruction of the PCP. CHKB Syntax CHKB Ra, #imm5, S/C Description If bit imm5 of register Ra is equal to the specified test value S/C then set the carry flag R7.C, else clear the carry flag.
Page 621: Comp, 32-Bit Compare
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.11.10 COMP, 32-Bit Compare This section describes the COMP instructions of the PCP. COMP Syntax COMP Rb, Ra, cc_A Description If the condition CONDCA is true, then subtract the contents of register Ra from the contents of register Rb;...
Page 622: Copy, Dma Instruction
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.11.11 COPY, DMA Instruction This section describes the COMP instruction of the PCP. COPY Syntax COPY DST+-, SRC+-, CNC, RC0, SIZE Description Moves the contents of FPI Bus source location to FPI Bus destination location.
Page 623: Debug, Debug Instruction
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.11.12 DEBUG, Debug Instruction This section describes the DEBUG instruction of the PCP. DEBUG Syntax DEBUG EDA, DAC, RTA, SDB, cc_B Description Conditionally cause a debug event if condition CONDCB is true.
Page 624: Dinit, Divide Initialization Instruction
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.11.13 DINIT, Divide Initialization Instruction This section describes the DINIT instruction of the PCP. DINIT Syntax DINIT <R0>, Rb, Ra Description Initialize Divide logic ready for divide sequence (Rb / Ra) and Clear R0.
Page 625: Dstep, Divide Instruction
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.11.14 DSTEP, Divide Instruction This section describes the DSTEP instruction of the PCP. DSTEP Syntax DSTEP <R0>, Rb, Ra Description Perform 1 step (eight bits) of an unsigned 32- by 32-bit divide (Rb / Ra).
Page 626: Exit, Exit Instruction
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.11.16 EXIT, Exit Instruction This section describes the EXIT instruction of the PCP. EXIT Syntax EXIT EC, ST, INT, EP, cc_B Description Unconditionally exit channel program execution. Optionally decrement counter CNT1 (EC = 1), disable further channel invocation (ST = 1), generate an interrupt request (INT = 1) if condition CONDCB is true.
Page 627: Jc, Jump Conditionally
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.11.17 JC, Jump Conditionally This section describes the conditional jump instructions of the PCP. Syntax JC offset6, cc_B Description If CONDCB is true, then add the sign-extended value specified by offset6 to the contents of the PC, and jump to that address.
Page 628: Jl, Jump Long Unconditional
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.11.18 JL, Jump Long Unconditional This section describes the long jump instruction JL of the PCP. Syntax JL offset10 Description Add the sign-extended value specified by offset10 to the contents of the PC, and jump to that address.
Page 629 TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) LD.P Syntax LD.P Rb, [Ra], cc_A Description If condition CONDCA is true, then load the contents of the PRAM address location, specified by the addition of contents of the PRAM Data Pointer, shifted left by six bits, and the zero-extended 6-bit value Ra[5:0] into register Rb.
Page 630: Ldl, Load 16-Bit Value
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.11.20 LDL, Load 16-bit Value This section describes the LDL instructions of the PCP. LDL.IL Syntax LDL.IL Ra, #imm16 Description Load the immediate value imm16 into the lower bits of register Ra (bits [15:0]).
Page 631: Mov, Move Register To Register
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.11.22 MOV, Move Register to Register Syntax MOV Rb, Ra, cc_A Description If condition CONDCA is true, then move the contents of register Ra into register Rb. If CONDCA is false, no operation is performed.
Page 632: Multiply Instructions
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.11.23 Multiply Instructions This section describes the multiply instructions of the PCP. MSTEP32 Syntax MSTEP32 <R0>, Rb, Ra Description Perform an unsigned multiply step, using eight bits of data taken from Rb, keeping the least significant 32 bits of a potential 64-bit result.
Page 633: Neg, Negate
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.11.24 NEG, Negate This section describes the NEG instruction of the PCP. Syntax NEG Rb, Ra, cc_A Description If condition CONDCA is true, then move the 2’s complement of the contents of register Ra into register Rb. If CONDCA is false, no operation is performed.
Page 634: Or, Logical Or
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.11.27 OR, Logical OR This section describes the OR instructions of the PCP. Syntax OR Rb, Ra, cc_A Description If the condition CONDCA is true, then perform a bit-wise logical OR of the contents of register Ra and the contents of register Rb;...
Page 635: Pri, Prioritize
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.11.28 PRI, Prioritize This section describes the PRI instruction of the PCP. PRId Syntax PRI Rb, Ra, cc_A Description If condition CONDCA is true, then find the bit position of the most significant 1 in register Ra and put the number into register Rb.
Page 636: Pram Bit Operations
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.11.29 PRAM Bit Operations This section describes the MCLR and MSET instructions of the PCP. MCLR Syntax MCLR.PI Ra, [#offset6] Description Perform an ‘AND’ of the contents of the specified register with...
Page 637: Rl, Rotate Left
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.11.30 RL, Rotate Left This section describes the RL instruction of the PCP. Syntax RL Ra, #imm5 Description Rotate the contents of register Ra to the left by the number of bit positions specified through the 5-bit value imm5.
Page 638: Set, Set Bit
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.11.32 SET, Set Bit This section describes the SET bit instruction of the PCP. Syntax SET Ra, #imm5 Description Set bit imm5 of register Ra to 1. Operation R[a][imm5] = 1...
Page 639: Shr, Shift Right
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.11.34 SHR, Shift Right This section describes the SHR instruction of the PCP. Syntax SHR Ra, #imm5 Description Shift the contents of register Ra to the right by the number of bit positions specified through the 5-bit value imm5.
Page 640: St, Store
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.11.35 ST, Store This section describes the ST instructions of the PCP. ST.F Syntax ST.F Rb, [Ra], Size Description Store the contents of register Rb to the address location specified by the contents of register Ra.
Page 641: Sub, 32-Bit Subtract
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.11.36 SUB, 32-Bit Subtract This section describes the SUB instructions of the PCP. Syntax SUB Rb, Ra, cc_A Description If the condition CONDCA is true, then subtract the contents of register Ra from the contents of register Rb;...
Page 642: Xch, Exchange
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.11.37 XCH, Exchange This section describes the XCH instructions of the PCP. XCH.F Syntax XCH.F Rb, [Ra], Size Description Exchange contents of R[b] and FPI[R[a]] When Size is byte or half-word, the value is stored with the internal LSB (bit 0) properly aligned to the correct FPI byte or half-word lane.
Page 643: Xor, 32-Bit Logical Exclusive Or
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.11.38 XOR, 32-Bit Logical Exclusive OR This section describes the XOR instructions of the PCP. Syntax XOR Rb, Ra, cc_A Description If the condition CONDCA is true, then perform a bit-wise logical Exclusive-OR of the contents of register Ra and the contents of register Rb;...
Page 644: Flag Updates Of Instructions
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.11.39 Flag Updates of Instructions Most instructions update the state flags in R7. In Table 11-14, each instruction is shown with the flags that it updates. Table 11-14 Flag Updates...
Page 645: Instruction Timing
Note: The clock cycles listed in Table 11-15 are PCP module clock cycles. In the TC1796, the PCP is connected to the System Peripheral Bus (which is a FPI Bus) and clocked with as module clock ( = 75 MHz, resulting in a minimum SYSmax clock cycle time of 13.3 ns).
Page 646 TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) Table 11-15 Instruction Timing (cont’d) Instruction Number of Clock Comments Notes Cycles FPI Access ADD.F 8 min. 5 int. + 3 min. for FPI read SUB.F 8 min. 5 int. + 3 min. for FPI read COMP.F...
Page 647 TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) Table 11-15 Instruction Timing (cont’d) Instruction Number of Clock Comments Notes Cycles – – – – LD.P – – ST.P – – – – – – – – Immediate Access ADD.I...
Page 648 TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) Table 11-15 Instruction Timing (cont’d) Instruction Number of Clock Comments Notes Cycles MINIT – MSTEP.L – MSTEP.U – Jump – – y = 4, n = 2 – JC.A y = 4, n = 2 –...
Page 649: Programming Of The Pcp
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.12 Programming of the PCP In this section, several techniques are outlined to help design channel programs. There are also examples on configuring a channel program’s context. 11.12.1 Initial PC of a channel program A channel program can begin operation at the Channel Entry Table location corresponding to the priority of the interrupt.
Page 650: Channel Resume
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.12.1.2 Channel Resume When PCP_CS.RCB = 0, the program counter of the PCP is vectored to the address that is restored from the channel program’s context. This means that before exiting, a channel program must itself arrange for where it will resume execution by configuring the value of its PC in its saved context so that it restarts at the desired location.
Page 651: Channel Management For Small And Minimum Contexts
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) ERROR,cc_NZ ;jump to error routine if not ;correct ADD.I R5,#0x1 ;increment state number EXIT EC=1,ST=0,INT=0,EP=1,cc_UC ;begin exit STATE1: COMP.I R5,#0x1 ;compare to interrupt number it ;should be ERROR,cc_NZ ;jump to error routine if not ;correct...
Page 652: Dispatch Of Low Priority Tasks
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) two choices here. A boot-time interrupt channel program can be invoked once to perform initialization, or there can be a program that routinely loads these values as a matter of course, and is invoked at boot time or as upon receipt of the very first interrupt.
Page 653: Case-Like Code Switches (Computed Go-To)
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.12.6 Case-like Code Switches (Computed Go-To) The JC.I instruction can be used to implement a multi-way branch for branch-on-bit or branch-on-state conditional branches. This instruction allows a conditional relative jump based on an index held in a register.
Page 654: Bcopy Instruction (Burst Copy)
(see the FPI Bus description for details). If either address is incorrectly aligned, the PCP will generate an Illegal Operation Error Exit. See also Page 11-127 for TC1796 specific details of the BCOPY instruction. User’s Manual 11-117 V2.0, 2007-07...
Page 655: Pcp Programming Notes And Tips
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.13 PCP Programming Notes and Tips This section discusses constraints on the use of the PCP and points out some non- obvious issues. 11.13.1 Notes on PCP Configuration •...
Page 656: General Purpose Register Use
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.13.2 General Purpose Register Use • The most significant 16 bits of R7 may not be written, and will always read back as 0. However, no error will occur if a write to the most significant 16 bits occurs.
Page 657: Use Of Channel Interruption
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) necessary, critical instruction sequences should be protected by use of the R7.IEN bit (see Page 11-120). 11.13.3 Use of Channel Interruption • When a channel program consists of only a few instructions, it is best to configure the channel to be non-interruptible.
Page 658 TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) service request for a channel in any group from 1 to 3, a group 2 channel program can only be interrupted by a new service request for a channel in group 3).
Page 659: Implementing Divide Algorithms
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) 11.13.4 Implementing Divide Algorithms As discussed in Section 11.11.4, a divide algorithm must always start with a DINIT instruction followed by a number of DSTEP instructions (up to four depending on the data width that is required).
Page 660: Implementing Multiply Algorithms
TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) Divide Examples Example of a 32/32 bit divide (R5 / R3): DINIT R5, R3 ;Initialize ready for the divide HANDLE_DIVIDE_BY_ZERO, cc_V ;V flag was set so ;jump to divide ;by zero error handler...
Page 661 TC1796 System Units (Vol. 1 of 2) Peripheral Control Processor (PCP) MSTEP32 R1, R4 ;Perform one MSTEP32 instruction ;(8 bit multiply) After this sequence, R0 holds the result, R1 is left unchanged (right rotated by RR instruction then left rotated by MSTEP32 instruction), and R4 is unchanged. The result is only valid if there is no overflow (i.e.
Page 662: Implementation Of The Pcp In The Tc1796
The addresses of the PCP registers and memories in the TC1796 are given in the following subsections. 11.14.1 PCP Memories In the TC1796, the location of the registers and the memories sizes of the PRAM and the CMEM are given in Table 11-16.
Page 663: Pcp Reset Operation
By a system hardware signal (hard reset) • By programming of a PCP register bit (soft reset) PCP Hard Reset A PCP hard reset is always triggered if at least one of these TC1796 reset sources becomes active: • Watchdog Timer Reset •...
Page 664: Bcopy Instruction
11.14.4 BCOPY Instruction In the TC1796, the BCOPY instruction can be used to perform burst transfers (2, 4, or 8 words) with DMI memories (Local data RAM and Dual-port RAM) and the PCP memories. Other internal and external memories can be accessed using a burst size of 2 words only (CNT0 = 10 User’s Manual...
Page 665: Direct Memory Access Controller
Direct Memory Access Controller Direct Memory Access Controller This chapter describes the Direct Memory Access (DMA) Controller and the Memory Checker Module (MCHK) of the TC1796. It contains the following sections: • Functional description of the DMA controller kernel (see...
Page 666: Dma Controller Kernel Description
DMA Sub-Blocks to the two FPI Bus interfaces and an MLI bus interface. In the TC1796, the FPI Bus interfaces are connected to the System Peripheral Bus and the Remote Peripheral Bus. The third specific bus interface provides a connection to Micro Link Interface modules (two MLI modules in the TC1796) and other DMA-related devices (Memory Checker module in the TC1796).
Page 667: Features
TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller 12.1.1 Features • 16 independent DMA channels – 8 DMA channels in each DMA Sub-Block – Up to 8 selectable request inputs per DMA channel – 2-level programmable priority of DMA channels within a DMA Sub-Block –...
Page 668: Definition Of Terms
TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller 12.1.2 Definition of Terms DMA Move A DMA move is an operation that always consists of two parts: 1. A read move that loads data from a data source into the DMA controller 2.
Page 669: Dma Principles
TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller 12.1.3 DMA Principles The DMA controller supports DMA moves from one address location to another one. DMA moves can be requested either by hardware or by software. DMA hardware...
Page 670: Dma Channel Functionality
TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller 12.1.4 DMA Channel Functionality Each of the 2 × 8 DMA channels has one associated register set containing seven 32-bit registers. These registers are numbered by two indexes to indicate the related DMA channel: Index “m”...
Page 671 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller the source or destination address register. In this case, no buffering of the address is required. When writing a new address to the (address of) the source or destination address register and a DMA transaction is running, no transfer to an address register can take place and SHADRmn holds the new address value that was written.
Page 672 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller Write new source address to (address of) SADRmn No transaction running ? (CHSRmn.TCOUNT = 0 & TRSR.CHmn = 0) Store new source address intermediately in SHADRmn New transaction started ? &...
Page 673 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller CHSRmn.TCOUNT tc1-1 tc2-1 tc2-2 CHCRmn.TREL sa1+ sa1+ SADRmn sa1+1 sa2+1 sa2+2 tc1-1 SHADRmn with 0000 0000 ADRCR0n.SHCT = 01 tc1 = transfer count 1 1) 3) = writing to CHCRmn and SADRmn...
Page 674: Dma Channel Request Control
TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller 12.1.4.2 DMA Channel Request Control Figure 12-6 shows the control logic for DMA requests that is implemented for each DMA channel. CHCRmn Suspend Request CHMODE TRSR Suspend Control HTREQ TRSR &...
Page 675: Dma Channel Operation Modes
TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller If a software or a hardware DMA request is detected for channel mn while TRSR.CHmn is set, a request lost event occurs. This error event indicates that the DMA is already processing a transfer and that another transfer has been requested before the end of the previous one.
Page 676 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller The software-controlled mode that initiates a single DMA transfer to be executed is selected for DMA channel mn by the following write operations: • CHCRmn.RROAT = 0 • STREQ.SCHmn = 1, repeated for each DMA transfer When CHCRmn.RROAT = 0, TRSR.CHmn becomes cleared after each DMA transfer of...
Page 677 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller Hardware-controlled Modes In hardware-controlled modes a hardware request signal starts a DMA transaction or a single DMA transfer. There are two hardware-controlled modes available: • Single Mode: Hardware requests are disabled by hardware after a DMA transaction •...
Page 678 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller CHCRmn.RROAT = 1 TRSR.CHmn TRSR.HTREmn CHmn_REQ DMA Transfer mn TR0 TR1 CHSRmn.TCOUNT tc-1 tc-1 tc = initial transfer count (triggered at the end of a transaction with IRDV = 0) CHCRmn.RROAT = 0...
Page 679: Error Conditions
TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller Combined Software/Hardware-controlled Mode Figure 12-9 shows how software- and hardware-controlled modes can be combined. In the example, the first DMA transfer is triggered by software when setting STREQ.SCHmn. Hardware requests are still disabled. After hardware requests have been enabled by setting HTREQ.ECHmn, subsequent DMA transfers are triggered now...
Page 680: Channel Reset Operation
TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller 12.1.4.5 Channel Reset Operation A DMA transaction of DMA channel mn can be stopped (channel is reset) by setting bit CHRSTR.CHmn. When a read or write FPI Bus access of DMA channel mn is executed at the time when CHRSTR.CHmn is set, this FPI Bus access is finished normally.
Page 681: Transfer Count And Move Count
TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller 12.1.4.6 Transfer Count and Move Count The move count determines the number of moves (consisting of one read and one write each) to be done in each transfer. The move count allows the user to indicate to the DMA the number of moves to be done after one request.
Page 682 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller Source Memory Destination Memory Moves ..ADRCRmn Parameters: ADRCRmn Parameters: SMF = 011 DMF = 010 INCS = 1 INCD = 0 MCA05690 Figure 12-11 Programmable Address Modification - Example 1...
Page 683: Circular Buffer
TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller Source Memory Destination Memory Moves ADRCRmn Parameters: ADRCRmn Parameters: SMF = 000 DMF = 001 INCS = 1 INCD = 1 MCA05691 Figure 12-12 Programmable Address Modification - Example 2 12.1.4.7 Circular Buffer...
Page 684: Transaction Control Engine
TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller 12.1.5 Transaction Control Engine The Transaction Control Unit in each DMA Sub-Block, as shown in the DMA Controller block diagram in Figure 12-1, contains a Channel Arbiter and a Move Engine.
Page 685: Bus Switch
TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller 12.1.6 Bus Switch The Bus Switch of the DMA controller provides the connection from the two DMA Sub- Blocks to the two FPI Bus interfaces (connected to System Peripheral Bus and Remote...
Page 686 CHCRmn.DMAPRIO determines the priority that is used when a move operation related to this channel is targeting the FPI Bus 0 (SPB). In the TC1796, the DMA controller has two priorities on FPI Bus 0 (DMA0 and DMA1), where it competes against the other bus masters in the system to access the bus.
Page 687: On-Chip Debug Capabilities
DMA controller. 12.1.7.2 Soft-suspend Mode The TC1796 on-chip debug control unit is able to generate a Soft-suspend Mode request (SUSREQ) for the DMA controller. When this soft suspend request becomes active, the state of a DMA channel becomes frozen, DMA requests are no longer forwarded, and the state of the DMA channel can be analyzed by reading the register contents.
Page 688: Break Signal Generation
TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller after Suspend Mode has been left again. Suspend Mode of DMA channel mn is left and its normal operation continues if either the SUSREQ signal becomes inactive, or if the enable bit SUSENmn is cleared by software.
Page 689: Trace Signal Generation
Figure 12-16 DMA Break Event Generation 12.1.7.4 Trace Signal Generation The TC1796 provides sixteen OCDS Level 2 debug output lines OCDSL2[15:0]. These 16 output lines can be selected to output trace data of the DMA controller. Two trace data types are possible: •...
Page 690 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller TR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0 Figure 12-17 16-bit DMA Channel Transaction Request Trace TR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0...
Page 691: Interrupts
TCOUNT value. This means that a TCOUNT match interrupt can be generated after one of the last 16 DMA transfers of a DMA transaction. Note that with IRDV = 0000 , the 1) In the TC1796, only SR[7:0] are connected to interrupt nodes. User’s Manual 12-27 V2.0, 2007-07...
Page 692 Decremented CHmn CICHmn INTSR Clear CHCRmn IPMmn PATSEL Enabled if PATSEL ¹ 00 Pattern Detection Interrupt mn MCA05696_mod Figure 12-19 Channel Interrupts 1) In the TC1796, only SR[7:0] are connected to interrupt nodes. User’s Manual 12-28 V2.0, 2007-07 DMA, V2.0...
Page 693: Transaction Lost Interrupt
= 0-1, n = 0-7 CLRE ERRSR CHRSTR Clear CTL17 TRL17 ETRL17 CH17 CLear Transaction Lost Interrupt 17 MCA05697_mod Figure 12-20 Transaction Lost Interrupt 1) In the TC1796, only SR[7:0] are connected to interrupt nodes. User’s Manual 12-29 V2.0, 2007-07 DMA, V2.0...
Page 694: Move Engine Interrupts
³1 CLRE ERRSR m = 0-1 Clear CMEmDER MEmDER EMEmDER Move Engine m Destination Error Interrupt MCA05698_mod Figure 12-21 Move Engine Interrupts 1) In the TC1796, only SR[7:0] are connected to interrupt nodes. User’s Manual 12-30 V2.0, 2007-07 DMA, V2.0...
Page 695 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller When a Move Engine m source or destination error occurs, additional status bits and bit fields are provided in the error status register ERRSR to indicate the following two status conditions: •...
Page 696: Wrap Buffer Interrupts
= 0-1, n = 0-7 WRPSR CHICRmn WRPDmn WRPDE Clear Wrap Destination Buffer Interrupt mn MCA05699_mod Figure 12-22 DMA Wrap Buffer Interrupts 1) In the TC1796, only SR[7:0] are connected to interrupt nodes. User’s Manual 12-32 V2.0, 2007-07 DMA, V2.0...
Page 697: Interrupt Request Compressor
SIDMA15 CHICRmn WRPP ≥1 Interrupt to SR1 Output Wrap Buffer SR15 Interrupts (16) to SR14 MCA05700 Figure 12-23 DMA Interrupt Request Compressor 1) In the TC1796, only SR[7:0] are connected to interrupt nodes. User’s Manual 12-33 V2.0, 2007-07 DMA, V2.0...
Page 698: Pattern Detection
TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller 12.1.9 Pattern Detection Each Move Engine in a DMA Sub-Block provides a register MEmR that contains the data that was read during the last read move. Parts of this read move data can be compared after the read move to data that is stored in the Move Engine pattern register MEmPR of DMA Sub-Block m.
Page 699: Pattern Compare Logic
TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller 12.1.9.1 Pattern Compare Logic Read move data and compare match patterns are compared on a bit-wise level. The logic as shown in Figure 12-24 is implemented in each COMP block of...
Page 700: Pattern Detection For 8-Bit Data Width
TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller 12.1.9.2 Pattern Detection for 8-bit Data Width When 8-bit channel data width is selected (CHCRmn.CHDW = 00 ), the pattern detection logic is configured as shown in Figure 12-25. Three compare match configurations are possible.
Page 701: Pattern Detection For 16-Bit Data Width
TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller 12.1.9.3 Pattern Detection for 16-bit Data Width When 16-bit channel data width is selected (CHCRmn.CHDW = 01 ) the pattern detection logic can be configured as shown in Figure 12-26.
Page 702: Pattern Detection For 32-Bit Data Width
TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller ADRCRmn CHCRmn MEmPR PATm3 PATm2 PATm1 PATm0 INCS PATSEL Mask COMP Pattern Detected ≥1 Mask COMP & Mask COMP MEmR RDm3 RDm2 RDm1 RDm0 CHSRmn 1) This signal is clocked into LXO after each read move.
Page 703 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller 12.1.9.4 Pattern Detection for 32-bit Data Width When 32-bit channel data width is selected (CHCRmn.CHDW = 10 ), the pattern detection logic is configured as shown in Figure 12-27. Three compare match configurations are possible.
Page 704: Access Protection
TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller 12.1.9.5 Access Protection The DMA controller provides an access protection logic that makes it possible to disable read and write accesses of the Move Engines to specific parts of the memory map. Each address of a read move and a write move is always checked to determine if it is within an address range that is enabled for read/write access.
Page 705 Note: The definition of the fixed address ranges x and the assignment of each sub-range to one of the fixed address ranges is product-specific. The definitions of the address ranges for the DMA controller as implemented in the TC1796 are defined Page 12-98.
Page 706: Dma Module Kernel Registers
The complete and detailed address map of the DMA module is described in Table 18-23 Page 18-53 of the TC1796 User’s Manual System Units part (Volume 1). Note: For documentation automation purposes, the DMA channel numbering index “x” is used in the DMA module kernel register descriptions. This index is represented by “n”...
Page 707 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller Table 12-6 Registers Overview - DMA Kernel Registers Register Short Register Long Name Offset Description Name Address DMA_ID DMA Module Identification Register Page 12-45 DMA_CHRSTR DMA Channel Reset Request Register 010...
Page 708 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller Table 12-6 Registers Overview - DMA Kernel Registers (cont’d) Register Short Register Long Name Offset Description Name Address (m × 8 + x) × DMA_CHICRmx DMA Channel mx Interrupt Control...
Page 709: System Registers
TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller 12.2.1 System Registers The Module Identification Register ID contains read-only information about the DMA module version. DMA_ID DMA Module Identification Register (008 Reset Value: 001A C0XX 16 15 MODNUM...
Page 710 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller The OCDS Register describes the break capability of the DMA module. OCDSR is only reset with the OCDS Reset. DMA_OCDSR DMA OCDS Register (064 Reset Value: 0000 0000 BCHS1...
Page 711 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller Field Bits Type Description BRL0 Break On Request Lost in Sub-Block 0 This bit field determines whether a BREAK signal is generated for DMA Sub-Block 0 when at least one of its eight transaction lost interrupts becomes active.
Page 712 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller The Suspend Mode Register contains bits for each DMA channel that make it possible to enable/disable its Soft-suspend Mode capability and that indicate its suspend status. DMA_SUSPMR DMA Suspend Mode Register...
Page 713 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller Field Bits Type Description SUSEN1x Suspend Enable for DMA Channel 1x (x = 0-7) This bit enables the soft suspend capability individually for each DMA channel 1x. DMA channel 1x is disabled for Soft-suspend Mode.
Page 714 DMA interrupt output line SRx will be activated. Reading this bit returns a 0. [31:16] Reserved Read as 0; should be written with 0. Note: In the TC1796, only interrupt output lines SR[7:0] are available. Therefore, only bits SIDMA[7:0] are effective. User’s Manual 12-50 V2.0, 2007-07...
Page 715: General Control/Status Registers
TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller 12.2.2 General Control/Status Registers The bits in the Channel Reset Request Register are used to reset DMA channel mx. DMA_CHRSTR DMA Channel Reset Request Register (010 Reset Value: 0000 0000...
Page 716 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller The bits in the Transaction Request State Register indicates which DMA channel is processing a request, and which DMA channel has hardware transaction requests enabled. DMA_TRSR DMA Transaction Request State Register...
Page 717 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller Field Bits Type Description HTRE0x 16+x Hardware Transaction Request Enable State of DMA (x = 0-7) Channel 0x Hardware transaction request for DMA Channel 0x is disabled. An input DMA request will not trigger the channel 0x.
Page 718 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller The bits in the Software Transaction Request Register are used to generate a DMA transaction request by software. DMA_STREQ DMA Software Transaction Request Register (018 Reset Value: 0000 0000...
Page 719 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller The bits in the Hardware Transaction Request Register enable or disable DMA hardware requests. DMA_HTREQ DMA Hardware Transaction Request Register (01C Reset Value: 0000 0000 Field Bits Type Description...
Page 720 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller The Enable Error Register describes how the DMA controller reacts to errors. It enables the interrupts for the loss of a transaction request or Move Engine errors. DMA_EER DMA Enable Error Register...
Page 721 SR1 selected for Move Engine 0 interrupt … … 1110 SR14 selected for Move Engine 0 interrupt 1111 SR15 selected for Move Engine 0 interrupt Note: In the TC1796 only SR[7:0] are connected to interrupt nodes. User’s Manual 12-57 V2.0, 2007-07 DMA, V2.0...
Page 722 … 1110 SR14 selected for Move Engine 1 interrupt 1111 SR15 selected for Move Engine 1 interrupt Note: In the TC1796 only SR[7:0] are connected to interrupt nodes. TRLINP [31:28] rw Transaction Lost Interrupt Node Pointer TRLINP determines the number n (n = 0-15) of the service request output SRn that becomes active on a transaction lost interrupt.
Page 723 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller The Error Status Register indicates if the DMA controller couldn’t answer to a request because the previous request was not terminated (see Section 12.1.4.4). It indicates also the FPI Bus accesses that have been terminated with errors.
Page 724 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller Field Bits Type Description ME0SER Move Engine 0 Source Error This bit is set whenever a Move Engine 0 error occurred during a source (read) move of a DMA transfer, or a request could not been serviced due to the access protection.
Page 725 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller Field Bits Type Description FPI1ER RPB Error This bit is set whenever a move that has been started by the DMA/MLI master interface on FPI Bus interface 1 leads to an error.
Page 726 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller The Clear Error Register contains bits that make it possible to clear the Transaction Request Lost flags or the Move Engine error flags. DMA_CLRE DMA Clear Error Register (028...
Page 727 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller Field Bits Type Description CFPI0ER Clear SPB Error No action Clear error flag ERRSR.FPI0ER. CFPI1ER Clear RPB Error No action Clear error flag ERRSR.FPI1ER. CLRMLI0 Clear MLI0 Error No action Clear error flag ERRSR.MLI0.
Page 728 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller The Interrupt Status Register indicates if CHSRmx.TCOUNT matches with CHCRmx.IRDV, or if CHSRmx.TCOUNT has been decremented (depending on CHICRmx.INTCT[0]),or if a pattern has been detected. These conditions can also...
Page 729 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller Field Bits Type Description IPM0x 16+x Pattern Detection from Channel 0x (x = 0-7) This bit indicates that a pattern has been detected for channel 0x while the pattern detection has been enabled.
Page 730 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller The Wrap Status Register gives information about the channels that did a wrap-around on their source or destination buffer(s). This condition can also lead to an interrupt if it is enabled.
Page 731 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller Field Bits Type Description WRPD1x 24+x Wrap Destination Buffer for Channel 1x (x = 0-7) These bits indicate which channels have done a wrap-around of their destination buffer(s). No wrap-around occurred for channel 1x.
Page 732 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller Field Bits Type Description CICH1x Clear Interrupt for DMA Channel 1x (x = 0-7) These bits make it possible to clear the channel interrupt flags INTSR.ICH1x and INTSR.IPM1x of DMA channel 1x by software.
Page 733: Move Engine Registers
TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller 12.2.3 Move Engine Registers The Move Engine Status Register is a read-only register that holds status information about the transaction handled by the Move Engines. DMA_MESR DMA Move Engine Status Register...
Page 734 [7:5] Read Buffer Trace for FPI Bus Interface 0 This bit field contains trace information from the buffer in the FPI Bus Interface 0. In the TC1796 it indicates the source of a bus access to the Remote Peripheral Bus.
Page 735 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller The Move Engine m (m = 0,1) Read Register indicates the value that has just been read by Move Engine m. The value in this register is compared to the bits in register MEmPR according to the bit fields CHCR0x.PATSEL.
Page 736 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller The Move Engine m (m = 0,1) Pattern Register contains the patterns (mask and/or compare bits) to be processed by the pattern detection logic in Move Engine m. DMA_ME0PR...
Page 737 If AENn = 0 for a read/write move to address range n, the read/write move is not executed and a source/destination Move Engine interrupt is generated Note: See Table 12-11 Page 12-98 for the TC1796 specific address range definition. User’s Manual 12-73 V2.0, 2007-07 DMA, V2.0...
Page 738 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller The DMA Move Engine m (m = 0,1) Access Range Register determines number and size of the sub-ranges for address range extension n (n = 0-3). See also Figure 12-28 for bit field definitions.
Page 739 3. SIZE3 [31:29] Address Size 3 SIZE3 determines the sub-range size within address range extension 3. Note: See Section 12.3.2 Page 12-98 for the TC1796 specific address range and address range extension definitions. User’s Manual 12-75 V2.0, 2007-07 DMA, V2.0...
Page 740: Channel Control/Status Registers
TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller 12.2.4 Channel Control/Status Registers The Channel Control Register for DMA channel mx contains its configuration and its control bits and bit fields. DMA_CHCR0x (x = 0-7) DMA Channel 0x Control Register...
Page 741 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller Field Bits Type Description PRSEL [15:13] Peripheral Request Select This bit field controls the hardware request input multiplexer of DMA channel mx (m=0,1; see Figure 12-6 Page 12-10). Input CHmx_REQI0 selected...
Page 742 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller Field Bits Type Description CHMODE Channel Operation Mode CHMODE determines the clear condition for control bit TRSR.HTREmx of DMA channel mx. Single Mode operation is selected for DMA channel mx. After a transaction, DMA channel mx is disabled for further hardware requests (TRSR.HTREmx is cleared by hardware).
Page 743 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller Field Bits Type Description DMAPRIO DMA Priority This bit determines the bus request priority that is used when a move operation related to channel mx is requesting FPI Bus 0. The value of DMAPRIO is also used for the DMA-internal arbitration between the Move Engines of the DMA.
Page 744 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller The Channel Status Register contains the current transfer count and a pattern detection compare result. DMA_CHSR0x (x = 0-7) DMA Channel 0x Status Register (x*20 Reset Value: 0000 0000...
Page 745 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller The Channel Interrupt Control Register control the interrupts generation. DMA_CHICR0x (x = 0-7) DMA Channel 0x Interrupt Control Register (x*20 Reset Value: 0000 0000 DMA_CHICR1x (x = 0-7) DMA Channel 1x Interrupt Control Register...
Page 746 … … 1111 SR15 selected for channel mx wrap buffer interrupt Note: In the TC1796, only SR[7:0] are connected to interrupt nodes. INTP [11:8] Interrupt Pointer INTP determines the number n (n = 0-15) of the service request output SRn that becomes active on a channel interrupt.
Page 747 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller The Address Control Register controls how source and destination addresses are updated after a DMA move. Furthermore, it determines whether or not a source or destination address register update is shadowed.
Page 748 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller Field Bits Type Description INCS Increment of Source Address This bit determines whether the address offset as selected by SMF will be added to or subtracted from the source address after each DMA move. The source address is not modified if CBLS = 0000 Address offset will be subtracted.
Page 749 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller Field Bits Type Description CBLS [11:8] Circular Buffer Length Source This bit field determines which part of the 32-bit source address register remains unchanged and is not updated after a DMA move operation (see also Page 12-19).
Page 750 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller Field Bits Type Description SHCT [17:16] rw Shadow Control This bit field determines whether an address is transferred into the shadow address register when writing to source or destination address register.
Page 751 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller Table 12-8 shows the offset values that are added or subtracted to/from a source or destination address register after a DMA move. Bit field SMF and bit INCS determine the offset value for the source address.
Page 752: Channel Address Registers
TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller 12.2.5 Channel Address Registers The Source Address Register contains the 32-bit source address. If a DMA channel mx is active, SADRmx is updated continuously (if programmed) and shows the actual source address that is used for read moves within DMA transfers.
Page 753 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller The Destination Address Register contains the 32-bit destination address. If a DMA channel is active, DADRmx is updated continuously (if programmed) and shows the actual destination address that is used for write moves within DMA transfers.
Page 754 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller The Shadow Address Register holds the shadowed source or destination address before it is written into the source or destination address register. SHADRmx can be read only. DMA_SHADR0x (x = 0-7)
Page 755: Dma Module Implementation
System Units (Vol. 1 of 2) Direct Memory Access Controller 12.3 DMA Module Implementation This section describes the TC1796 DMA module interfaces with the clock control, interrupt control, and address decoding. Figure 12-30 shows the TC1796-specific implementation details and interconnections of the DMA module.
Page 756: Dma Request Wiring Matrix
TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller 12.3.1 DMA Request Wiring Matrix The DMA request input lines of each DMA channel within DMA Sub-Block 0 and 1 are connected to request output lines from the peripheral modules according...
Page 757 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller Table 12-9 DMA Request Assignment for DMA Sub-Block 0 (cont’d) DMA Request Line DMA Requesting Unit Selected by Channel CH02_OUT DMA channel 02 CHCR03.PRSEL = 000 SCU_REQ3 Ext. Request Unit CHCR03.PRSEL = 001...
Page 758 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller Table 12-9 DMA Request Assignment for DMA Sub-Block 0 (cont’d) DMA Request Line DMA Requesting Unit Selected by Channel CH05_OUT DMA channel 05 CHCR06.PRSEL = 000 SCU_REQ2 Ext. Request Unit CHCR06.PRSEL = 001...
Page 759 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller Table 12-10 DMA Request Assignment for DMA Sub-Block 1 DMA Request Source DMA Request Unit Selected by Channel CH07_OUT DMA channel 07 CHCR10.PRSEL = 000 SCU_REQ0 Ext. Request Unit CHCR10.PRSEL = 001...
Page 760 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller Table 12-10 DMA Request Assignment for DMA Sub-Block 1 (cont’d) DMA Request Source DMA Request Unit Selected by Channel CH12_OUT DMA channel 12 CHCR13.PRSEL = 000 SCU_REQ3 Ext. Request Unit CHCR13.PRSEL = 001...
Page 761 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller Table 12-10 DMA Request Assignment for DMA Sub-Block 1 (cont’d) DMA Request Source DMA Request Unit Selected by Channel CH15_OUT DMA channel 15 CHCR16.PRSEL = 000 SCU_REQ2 Ext. Request Unit CHCR16.PRSEL = 001...
Page 762: Access Protection Assignment
Page 12-40 requires the assignment of 32 fixed address range. Table 12-11 shows this address range assignment as implemented in the TC1796. Table 12-11 DMA Access Protection Address Ranges Access Protection Range Related Module(s) No. n Enable Bit in Selected Address Range...
Page 763 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller Table 12-11 DMA Access Protection Address Ranges (cont’d) Access Protection Range Related Module(s) No. n Enable Bit in Selected Address Range MEmAENR AEN20 F010 C100 - F010 C1FF MLI1,...
Page 764 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller In the TC1796, two internal memory areas are assigned for access protection using programmable address sub-ranges: • 8-Kbyte Dual-Ported RAM (DPRAM), assigned as address range 18. The sub-ranges are controlled by bit fields MEmARR.SIZE0 and MEmARR.SLICE0.
Page 765 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller Table 12-12 DPRAM Address Protection Sub-Range Definitions (cont’d) SIZE0 Sub-Ranges SLICE0 Selected Address Range 2 sub-ranges of XXXX0 F010 A000 - F010 AFFF 4 Kbyte XXXX1 F010 B000 - F010 BFFF...
Page 766 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller Table 12-13 SRAM Address Protection Sub-Range Definitions (cont’d) SIZE1 Sub-Ranges SLICE1 Selected Address Range 2 sub-ranges of XXXX0 E800 0000 - E800 7FFF 32 Kbyte XXXX1 E800 8000 - E800 FFFF...
Page 767: Implementation-Specific Dma Registers
TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller 12.3.3 Implementation-specific DMA Registers The DMA controller as implemented in the TC1796 contains the following additional registers: • DMA clock control register • Service request control registers for DMA controller interrupts (DMA_SRCx) •...
Page 768 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller • Eight interrupt requests SR[7:0] = INT_O[7:0] from the DMA controller; upper eight interrupt requests of the DMA controller INT_O[15:8] are not connected. • Four interrupt requests SR[3:0] = INT_O[3:0] from the MLI0 module; upper four interrupt requests of the MLI0 module INT_O[7:4] are not connected.
Page 769: Clock Control Register
TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller 12.3.3.1 Clock Control Register The Clock Control Register controls the module clock signal. This clock is also used for the MLI modules as a common clock that can be individually divided for the MLI modules.
Page 770: Dma Service Request Control Registers
Direct Memory Access Controller 12.3.3.2 DMA Service Request Control Registers In the TC1796, only the lower eight DMA controller interrupts SR[7:0] are connected to service request control registers. The upper eight DMA controller interrupt outputs SR[15:8] are not used and not connected.
Page 771: Mli Service Request Control Registers
TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller 12.3.3.3 MLI Service Request Control Registers The Service Request Control Registers of the MLI modules are located inside the DMA address area, because the MLI modules do not have own FPI Bus interfaces. They share one FPI Bus interface with the DMA controller.
Page 772: System Interrupt Service Request Control Register
TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller 12.3.3.4 System Interrupt Service Request Control Register System interrupts of other on-chip modules are controlled by five system service request control registers which are located in the DMA address space. The five system service...
Page 773: Dma Controller Address Map
TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller Field Bits Type Description [9:8], 11, Reserved [31:16] Read as 0; should be written with 0. Note: The bit coding of the system interrupt service request control registers is identical to that of the DMA service request control registers shown two pages before.
Page 774: Memory Checker Module
TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller 12.4 Memory Checker Module 12.4.1 Functional Description The Memory Checker Module (MCHK) makes it possible to check the data consistency of memories. Any SPB bus master may access the memory checker. Preferable the DMA controller does it as described hereafter.
Page 775: Registers
The complete and detailed address map of the of the Memory Checker module is described in Table 18-31 Page 18-103 of the TC1796 User’s Manual System Units part (Volume 1). Table 12-15 Registers Address Space - Memory Checker Module Base Address...
Page 776: Memory Checker Registers
TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller 12.4.2.1 Memory Checker Registers The MCHK Module Identification Register ID contains read-only information about the MCHK module version. MCHK_ID Memory Checker Module Identification Register (008 Reset Value: 001B C0XX...
Page 777 TC1796 System Units (Vol. 1 of 2) Direct Memory Access Controller The Memory Checker Input Register is used during write moves of a memory checker related DMA transaction as data destination with its fixed register address. If the DMA moves to register MCHK_IR are 8-bit or 16-bit wide, the unused register bits of the 32-bit MCHKIN value are taken as 0s for the current result calculation.
Page 778 MLI or DMA controller via the Bus Switch of the DMA controller (see Figure 12-14) does not request the two FPI buses of the TC1796, SPB and RPB, because it is near the MLI modules address ranges. MCHK_WR Memory Checker Write Register...
Page 779: Lmb External Bus Unit
LMB External Bus Unit LMB External Bus Unit The External Bus Unit (EBU) of the TC1796 controls the transactions between external memories or peripheral units, and the internal memories and peripheral units. The basic interfaces of the EBU are shown in Figure 13-1.
Page 780: Block Diagram
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.1 Block Diagram Figure 13-2 shows the building blocks of the EBU. Data Data Path Control Asynchronous Access State Machine Control Lines Burst Access Program PLMB State Machine Local...
Page 781: Ebu Interface Signals
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.2 EBU Interface Signals The external EBU interface signals are listed in Table 13-1 below. Table 13-1 EBU Interface Signals Signal/Pin Type Function D[31:0] Data bus lines 0-31 A[23:0]...
Page 782: Address Bus, A[23:0]
System Units (Vol. 1 of 2) LMB External Bus Unit Note: The TC1796 does not directly support for 8-bit data bus width. When 8-bit wide devices are used they must be arranged in pairs to implement either a 16-bit or a 32-bit wide memory region.
Page 783: Address Valid, Adv
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit The third read/write control line, MR/W, can be used to connect external devices directly to an asynchronous Motorola-style bus interface. MR/W goes to a low level during a write cycle, and will stay at high during a read cycle.
Page 784: Wait Input, Wait
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.2.8 Wait Input, WAIT This is an input signal to the EBU that is used to dynamically insert wait states into read or write data cycles controlled by the device on the external bus.
Page 785: External Bus Arbitration
(i.e. is capable of driving the external bus). An external master is not able to access units that are located inside the TC1796. 13.3.1 External Bus Modes The EBU can operate in two bus modes on the external bus: •...
Page 786 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Table 13-4 EBU External Bus Arbitration Signals Signal Direction Function HOLD HOLD is asserted (low) by an external bus master when the external bus master requests to obtain ownership of the external bus from the EBU.
Page 787 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Table 13-5 External Bus Arbitration Programmable Parameters Parameter Function Description EBU_CON.ARBMODE Arbitration mode selection Page 13-83 EBU_CON.ARBSYNC Arbitration input signal sampling control EBU_CON.EXTLOCK External bus ownership locking control EBU_CON.TIMEOUTC External bus time-out control User’s Manual...
Page 788: Arbitration Modes
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.3.3 Arbitration Modes The arbitration mode of the EBU can be selected through configuration pins during reset (see Boot Selection Table on Page 4-12) or by programming the EBU_CON.ARBMODE...
Page 789 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Table 13-6 Function of Arbitration Pins in Arbiter Mode Type Pin Function in Arbiter Mode HOLD In Owner Mode (EBU is the owner of the external bus), a low level at HOLD indicates a request for bus ownership from the external master.
Page 790 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 1. The external master wants to perform an external bus access by asserting a low signal on the HOLD input. 2. When the EBU is able to release bus ownership, it enters Hold Mode by tri-stating its bus interface lines and drives HLDA = 0 to indicate that it has released the bus.
Page 791 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Start EBU in Owner Mode (i.e. owner of the The EBU holds ownership of the external bus) external bus: While EXTLOCK = 1 Perform Appropriate PLMB access External Bus Access...
Page 792: Participant Mode" Arbitration Mode
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.3.3.4 “Participant Mode” Arbitration Mode The EBU tries to gain bus ownership only in case of pending transfers (e.g. when operating from internal memory and performing stores to external memory). While the EBU is not the owner of the external bus (default state), any PLMB access to the external bus will be issued with a retry by the EBU.
Page 793 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit BREQ (EBU Output) ≥1 Cycle HLDA (EBU Output) ≥1 Cycle HOLD (EBU Input) ≥1 Cycle External Bus Ext. Master on Bus EBU on Bus Ext. Master on Bus MCT05717 Figure 13-6 Arbitration Sequence with the EBU in Participant Mode In Participant Mode, the arbitration sequence starts with the EBU in Hold Mode.
Page 794 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Start EBU is in Hold Mode The EBU remains in Hold Mode until an PLMB access to the external bus is received. This access is rejected with a retry and...
Page 795: Arbitration Input Signal Sampling
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.3.4 Arbitration Input Signal Sampling The sampling of the arbitration inputs can be programmed for two modes: • Synchronous Arbitration • Asynchronous Arbitration When synchronous arbitration signal sampling is selected (ARBSYNC = 0), the arbitration input signals are sampled and evaluated in the same clock cycle.
Page 796: Reaction To An Plmb Access To The External Bus
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.3.6 Reaction to an PLMB Access to the External Bus The reaction of the to a external bus request from an PLMB master is controlled as shown in Figure 13-8.
Page 797: Pending Access Time-Out
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit As shown in Figure 13-8, this event also triggers the EBU to arbitrate with the external master in order to attempt to gain ownership of the external bus so that the request can be serviced when it is re-submitted by the master.
Page 798: Start-Up/Boot Process
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.4 Start-Up/Boot Process The EBU can start up in one of three modes after a reset or boot operation. Table 13-8 EBU Start-Up Modes Start-Up Modes Arbitration Mode Disabled...
Page 799: Boot Process
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Note: In TC1796, only Arbiter arbitration mode is supported in emulation mode. Furthermore, the CSEMU signal is connected to the CSCOMB chip select output by default after reset. 13.4.3 External Boot Mode The External Boot Mode of the EBU allows the EBU to boot (i.e.
Page 800 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Command Delay Address Phase Phase Command Phase (96 LMB_CLK (224 LMB_CLK (224 LMB_CLK cycles) cycles) cycles) LMBCLK Write Data AP95 CD223 CP223 to BUSCON Register A[23:0] 000004 BC[3:0] D[31:0]...
Page 801: Boot Configuration Value
TINV Field Bits Description AALIGN Address Alignment Loaded into EBU_BUSCON0.AALIGN. Reserved Reserved for future use. For TC1796, this bit must be set to 0. WAITRDC [4:2] Number of Wait States for Read Accesses Loaded into EBU_BUSAP0.WAITRDC. ADDRC [6:5] Number of Cycles in the Address Phase Loaded into EBU_BUSAP0.ADDRC.
Page 802 RES32 (bits [31:16]) of the configuration word are potentially available for use as configuration information. Note: In the TC1796, the EBU does not actually use bits 31 to 16 of the configuration word when CONF32BIT is 1. However, to allow future expansion this bit should be programmed to 0.
Page 803: Master Mode Operation
• Burst Mode Flash devices Each TC1796 internal PLMB master can access external devices via the EBU. The EBU provides four user-programmable external memory regions. Each of these regions is provided with a set of registers that determine the parameters of the external bus transaction and one chip select signal.
Page 804: External Memory Regions
13.5.1 External Memory Regions The EBU of the TC1796 supports four (plus one for emulation purposes) memory regions, which have its own associated chip select outputs CS[3:0] (and CSEMU). Each of these regions has a set of control registers to specify the type of memory/peripheral device and the access parameters.
Page 805 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Table 13-11 Programmable Parameters of Regions Register Parameter Function (Bit/Bit field) EBU_ADDRSELx ALTSEG Alternate segment of region to be compared to EBU_EMUAS PLMB address bits [31:28]. BASE Region base address to be compared with PLMB address in conjunction with the MASK parameter.
Page 806: Chip Select Control
• CSCOMB, which is a combination of CSEMU, CSGLB, and CSOVL. • Details about the chip select control logic as implemented in the TC1796 are shown Figure 13-10. The four chip select lines CSx are all available at dedicated chip select outputs. The internal CSGLB signal is controlled by bit field EBU_CON.GLOBALCS.
Page 807 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit EBU_CON SCU_CON Bit Field GLOBALCS & CSGLB Control & CSEMU CSCOMB & CSOVL EBU_EMUOVL Bit Field OVERLAY 1) Bit CSEEN is set after reset. Bits CSOEN and CSGEN are cleared after reset...
Page 808: Address Comparison
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.5.3 Address Comparison Standard Address Comparison Mode When an Addressing Override Mode is not active, each of the five EBU regions can be programmed for independent base addresses and lengths by bits and bit fields in registers EBU_ADDRSELx and EBU_EMU_AS.
Page 809 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 28 27 WRITE EBU_BUSCONx Write ? AGEN Register ≥1 & Burst Mode? 28 27 26 12 11 LMB Address Equal ? Expansion & Region Equal ? Selected ≥1 &...
Page 810 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 3. The most significant four bits of the PLMB address (“main” segment address) are compared to the most significant four bits of the BASE bit field. The result of the comparison (1 if equal, otherwise 0) is fed to the OR gate.
Page 811 128 Mbyte A[26:0] 1) These region size selections do not affect the external address bus of the TC1796 because A24, A25,and A26 are not output at pins (only A[23:0] are available at TC1796 pins). The EBU uses the five region select outputs from the above scheme, in conjunction with its own address decode logic, to react to PLMB accesses as follows: 1.
Page 812 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit When defining mirrored segments, the user is responsible for ensuring that there is no collision. There is no checking mechanism in hardware that ensures that each segment defined (either in BASE[31:28] or ALTSEG[11:8] or both) is exclusive. Therefore, the user must ensure that each mapping from region 0 to 3 and the emulator region does not interfere with any other;...
Page 813: Access Parameter Selection
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.5.4 Access Parameter Selection Selection of the appropriate access parameters is shown in Figure 13-12: Error No Match Region 0 Access Addr. Compare Parameter Check Region 1 Addr. Compare...
Page 814: Little-/Big-Endian Access Modes
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit The next cycle (Cycle n + 3) sees these parameters being passed to the appropriate external access cycle state machine (used to select/initialize the appropriate external access cycle, and also to select the external bus pins to be used for the access cycle).
Page 815: Plmb Bus Width Translation
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.5.6 PLMB Bus Width Translation If the internal access width is wider than the external bus width specified for the selected external region (programmed via the EBU_BUSCONx.PORTW bit field), the internal access is split in the EBU into several external accesses.
Page 816: Address Alignment During Bus Accesses
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit • During an access to a 16-bit wide external region, either Buffer 1 or Buffer 2 is enabled (according to bit 2 of the PLMB address being accessed) and either Buffer 4 or Buffer 5 is enabled (according to bit 1 of the PLMB address being accessed).
Page 817: Plmb Data Buffering
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.6 PLMB Data Buffering The EBU contains three data buffers that are used to adapt accesses from the internal 64-bit wide PLMB to the 16-bit or 32-bit wide external bus.
Page 818: Code Prefetch Buffer
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit modified bits in an external peripheral), the user’s software must ensure data coherency through the use of the DLOAD bit(s). When the EBU receives an external bus read access that represents a code fetch (i.e.
Page 819: Standard Access Phases
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Note: The Data Write Buffer can only store the data associated with a single write access. If the EBU receives a PLMB request for a write to the external bus and the Data Write Buffer is not available (i.e.
Page 820 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit • Asserts the MR/W signal according to the type of access to be performed (low in the case of a write access, not used in burst read cycles). This level is retained until the start of the next Address Phase.
Page 821: Command Delay Phase (Cd)
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.7.2 Command Delay Phase (CD) The Command Delay phase is optional. This means that it can also be programmed for a length of zero LMBCLK clock cycles. The CD phase allows for the insertion of a delay between Address Phase and Command Phase(s).
Page 822 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Cycle Type Number of Command Phase Cycles = WAITRDC × CMULT Read Cycle = WAITWRC × CMULT Write Cycle The equivalent control capability is available for bit fields EBU_EMUBAP.WAITRDC and EBU_BUSAPx.WAITWRC, which are multiplied by EBU_EMUBC.CMULT.
Page 823: Data Hold Phase (Dh)
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.7.4 Data Hold Phase (DH) The Data Hold phase is optional. This means that it can also be programmed for a length of zero LMBCLK clock cycles. Furthermore, it is only available for asynchronous write accesses.
Page 824: Burst Phase (Bp)
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.7.5 Burst Phase (BP) The Burst Phase is mandatory during burst read accesses. At the end of the Burst Phase the EBU reads data from the data bus. During a burst read access, Burst Phases are repeated as many times as required in order to read the required amount of data from the Burst Flash device.
Page 825: Recovery Phase (Rp)
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.7.6 Recovery Phase (RP) The Recovery Phase is optional. This means that it can also be programmed for a length of zero LMBCLK clock cycles. This phase allows the insertion of a delay following an external bus access that delays the start of the Address Phase for the next external bus access.
Page 826 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Table 13-15 Parameters for Recovery Phase Case Parameter(s) used to calculate “Highest Wins” Recovery Phase Region Current Next Access Access Same CSn Read Read RDRECOVC Write Write WRRECOVC Read...
Page 827: Multiplication Factor For Access Phase Length
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.7.7 Multiplication Factor for Access Phase Length As discussed in the previous sections, the length of each access phase is programmable as a multiple of the LMBCLK clock period. Since the LMB clock runs significantly faster than most external devices, some devices may need the EBU to be programmed to use a large number of LMBCLK clock cycles in a particular phase (or phases).
Page 828: Asynchronous Read/Write Accesses
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.8 Asynchronous Read/Write Accesses Asynchronous read/write access of the EBU support the following features: • LMBCLK clock-synchronous signal generation • Support for 16-bit and 32-bit bus width Performing an PLMB access with a data width greater than that of the external device automatically triggers a sequence of the appropriate number of external accesses to match the PLMB access width.
Page 829: Demultiplexed Device Configurations
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.8.2 Demultiplexed Device Configurations The EBU supports two different configurations of demultiplexed memory/peripheral devices: 16-bit demultiplexed mode and 32-bit demultiplexed mode. The 16-bit demultiplexed mode is selected by: •...
Page 830 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Figure 13-17 shows a typical connection for Intel-style and Motorola-style peripherals. The MR/W signal indicates the data direction for the current transfer, and can be used to control the data direction through the buffer for the D[31:0] bus (as well as controlling whether an access to a Motorola-Style device is read or write).
Page 831: Standard Asynchronous Access Phases
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.8.3 Standard Asynchronous Access Phases Accesses to asynchronous devices are composed of a subset of the standard access phases which are detailed in Section 13.7. The standard access phases for asynchronous devices are: •...
Page 832 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Table 13-17 Asynchronous Access Programmable Parameters (cont’d) Register Parameter Function (Bit/Bit field) EBU_BUSAPx RDRECOVC Number of minimum recovery cycles after a read EBU_EMUBAP access; can be multiplied by CMULT.
Page 833: Accesses To Demultiplexed Devices
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.8.5 Accesses to Demultiplexed Devices LMBCLK next AP (1 to n) (0 to n) (1 to n) (0 to n) A[23:0] Address Next A. RD/WR MR/W Sample D[31:0] Data in 1) All phases programmed to one LMBCLK period length.
Page 834 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit LMBCLK next AP (1 to n) (0 to n) (1 to n) (0 to n) (0 to n) A[23:0] Address Next. A. RD/WR MR/W D[31:0] Data out 1) All phases programmed to one LMBCLK period length.
Page 835: Dynamic Command Delay And Wait State Insertion
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.8.6 Dynamic Command Delay and Wait State Insertion In general, there are two critical phases during asynchronous device accesses. These phases are: • Command Delay Phase (see Page 13-43).
Page 836 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Note: Due to the two-cycle delay in Asynchronous Mode between the sampling of the WAIT input and its evaluation by the EBU, the Command Phase must always be programmed to be at least two LMBCLK cycles (via EBU_BUSAPx.WAITRDC or EBU_EMUBAP.WAITWRC) in this mode.
Page 837 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Read Access with Synchronous WAIT LMBCLK CPi1 CPi2 CPe3 A[23:0] Address D[31:0] Data in WAIT (active low) In the example above, the Command Delay phase is internally Note: programmed to zero LMBCLK cycles (no Command Delay phase).
Page 838 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit • Finally at LMBCLK edge 5, as a result of the WAIT input sampled as high at LMBCLK edge 3, the EBU terminates the Command Phase, reads the input data from D[31:0],and starts the Recovery Phase.
Page 839: Interfacing To Intel-Style Devices
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.8.6.2 Interfacing to INTEL-style Devices Figure 13-22 shows an example of accessing an INTEL-style demultiplexed device for read and write accesses. It shows the insertion of delay cycles (shown shaded) to adjust the access cycle to the device’s timing requirements.
Page 840 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Read Access LMBCLK CDi1 CDi2 CPi1 CPi2 CPi3 A[23:0] Address Next. A. D[31:0] Data in Sample Write Access LMBCLK CDi1 CDi2 CPi1 CPi2 A[23:0] Address Next. A. RD/WR D[31:0]...
Page 841: Interfacing To Motorola-Style Devices
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.8.6.3 Interfacing to Motorola-style Devices Figure 13-23 gives an example of accessing a Motorola-style demultiplexed device for read and write accesses. The chip select signal CSx is used to generate the AS input for the Motorola-style device.
Page 842 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Read Access LMBCLK CPi1 CPi2 CPe3 CPe4 CPe5 A[23:0] Address Next. A. (used as AS) M/RW D[31:0] Data in Sample WAIT (used as DTACK) Write Access LMBCLK CPi1 CPi2...
Page 843: Burst Mode Read Accesses
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.9 Burst Mode Read Accesses Synchronous burst read accesses of the EBU support the following features: • Fully synchronous timing with flexible programmable timing parameters (address cycles, read wait cycles, data cycles) •...
Page 844: Burst Flash Memory Configurations
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.9.2 Burst Flash Memory Configurations The EBU supports two different configurations of Burst Flash memory devices: 16-bit mode and 32-bit mode. Both modes are demultiplexed modes with separate address and data lines.
Page 845 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Figure 13-26 shows an example of two basic configurations for external Burst Flash memory connections. 32-Bit Data Bus D[15:0] DQ[15:0] DQ[15:0] D[31:16] A[19:0] A[19:0] A[21:2] 1M x 16 1M x 16...
Page 846: Burst Mode Access Phases
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Note: The EBU will issue an LMB Error Acknowledge if an attempt is made to write to an address that is programmed as Burst Flash unless a lower priority write-enabled region exists at the same address.
Page 847 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Table 13-19 Burst Flash Access Programmable Parameters Register Parameter Function (Bit/Bit field) EBU_BUSAPx ADDRC Number of cycles in address phase; can be EBU_EMUBAP multiplied by CMULT. CMDDELAY Number of programmed command delay cycles;...
Page 848 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Table 13-19 Burst Flash Access Programmable Parameters (cont’d) Register Parameter Function (Bit/Bit field) EBU_BFCON WAITFUNC0 Function of WAIT input during Type 0 reads: Wait for data or terminate burst...
Page 849: Support For Two Burst Flash Device Types
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.9.5 Support for two Burst Flash Device Types Support is provided for the use of two different Burst Flash configurations. This means, two sets of burst access parameters (e.g. for different Burst Flash devices) can be...
Page 850: Bfclki Input And Burst Flash Clock Feedback
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit LMBCLK BFCLKO EXTCLOCK = 00 BFCLKO EXTCLOCK = 01 BFCLKO EXTCLOCK = 10 BFCLKO EXTCLOCK = 11 MCT05738_mod Figure 13-27 Possible BFCLKO Configurations 13.9.7 BFCLKI Input and Burst Flash Clock Feedback The EBU Burst Mode control logic can be configured to use a clock feedback signal at BFCLKI to maximize the operating frequency for a given Flash device.
Page 851: Burst Length Control
0 or type 1 Burst Flash device parameters. Note: If EBSEn = 0, it must be regarded that the ADV/BAA active/inactive time in respect to BFCLKO can be negative. More details are defined in the AC timings of the TC1796 Data Sheet. User’s Manual 13-73 V2.0, 2007-07...
Page 852: Burst Flash Access Cycle
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.9.10 Burst Flash Access Cycle Figure 13-28 shows an example of a burst read access (burst length of four) with a Burst Flash device. LMBCLK BFCLKO AP2 AP3 CDi1 CDi2 CDi3...
Page 853: External Cycle Control Via The Wait Input
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Figure 13-29 shows a burst read access (burst length of four) with a BFCLKO frequency of 1/3 of LMBCLK frequency (EXTCLOCK = 01 LMBCLK BFCLKO A[23:0] Addr Next data...
Page 854: Wait For Page Load Mode
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Table 13-20 WAIT Mode Selection EBU_BUSCON. EBU_BFCON. Selected WAIT Mode WAIT WAITFUNC – WAIT function disabled Asynchronous Wait for Page Load Asynchronous Terminate and Start New Burst Synchronous Wait for Page Load...
Page 855: Terminate And Start New Burst Mode
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit only effect on operation is that the number of overrun cycles will increase as the decrementing of the sample counter will be lagged by the re-synchronization stages. 13.9.11.2 Terminate and Start New Burst Mode...
Page 856: Termination Of A Burst Mode Read Access
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.9.12 Termination of a Burst Mode Read Access A burst read operation is terminated by de-asserting the CSx signal, followed by the appropriate length Recovery Phase. Figure 13-30 shows termination of a burst access following the read of two locations (i.e.
Page 857: Ebu Registers
The complete and detailed address map of the PMU module with its registers is shown Table 18-34 Page 18-112 of this TC1796 System Units (Vol. 1 of 2) User’s Manual. Table 13-21 Registers Address Space -Flash Registers Module Base Address...
Page 858 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Table 13-22 Registers OverviewPMU Overlay Control Registers Register Register Long Name Offset Description Short Name Address EBU_ADDRSEL0 EBU Address Select Register 0 Page 13-90 EBU_ADDRSEL1 EBU Address Select Register 1...
Page 859: Identification Register, Id
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.10.1 Identification Register, ID The Module Identification Register ID contains read-only information about the EBU module version. EBU_ID EBU Module Identification Register (008 Reset Value: 0014 C0XX 16 15...
Page 860: Clock Control Register, Clc
DISS EBU Disable Status Bit EBU is enabled (default after reset) EBU is disabled In the TC1796, DISS is always read as 0, meaning that the EBU is always enabled. [31:2] Reserved Read as 0; should be written with 0.
Page 861: Configuration Register, Con
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.10.3 Configuration Register, CON EBU_CON EBU Configuration Register (010 Reset Value (Internal boot): 0000 0028 Reset Value (External boot): 0801 0068 0801 008A Reset Value (Emulation mode): 1001 0068...
Page 862 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Field Bits Type Description TIMEOUTC [15:8] Bus Time-out Control This bit field determines the number of inactive cycles leading to a bus time-out after the EBU gains ownership. Time-out is disabled.
Page 863 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Field Bits Type Description BFSSS Burst Flash Single Stage Synchronization This bit reduces the number of synchronization stages used in the pad logic of EBU pads. Two stages of synchronization used.
Page 864: Burst Flash Control Register, Bfcon
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.10.4 Burst Flash Control Register, BFCON EBU_BFCON EBU Burst Flash Control Register (020 Reset Value: 0010 01D0 FETBLEN1 DTALTNCY FETBLEN0 CLOCK Field Bits Type Description FETBLEN0 [3:0] Fetch Burst Length for Burst Flash Type 0...
Page 865 Frequency of External Clock at Pin BFCLKO This bit field sets the frequency of pin BFCLKO for accesses to both types of Burst Flash devices. Equal to LMBCLK frequency. In the TC1796, this selection is not allowed for LMBCLK ( frequencies above 75 MHz.
Page 866 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Field Bits Type Description FDBKEN Burst Flash Clock Feedback Enable BFCLK feedback not used. In this case, bit field DTALTNCY must be set to 0000 Incoming data and control signals (from the Burst Flash device) are re-synchronized to the BFCLKI input.
Page 867 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Field Bits Type Description DBA1 Disable Burst Address Wrapping The EBU automatically re-aligns any non- aligned burst access to a Type 1 device so that data can be fetched from the device in a single burst transaction.
Page 868: Address Select Register, Addrselx
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.10.5 Address Select Register, ADDRSELx EBU_ADDRSELx (x = 0-3) EBU Address Select Register x (080 +x*8 ADDRSEL[3:1] - Reset Value: 0000 0000 ADDRSEL0 - Reset Value (internal boot): 0000 0000...
Page 869 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Field Bits Type Description BASE [31:12] rw Memory Region Base Address Base address to be compared to PLMB address in conjunction with the mask control. [3:2] Reserved Read as 0; should be written with 0.
Page 870: Bus Configuration Register, Busconx
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.10.6 Bus Configuration Register, BUSCONx EBU_BUSCONx (x = 0-3) EBU Bus Configuration Register (0C0 +x*8 Reset Value (internal boot): 8092 8000 Reset Value (external boot): 8092 807F ENDI AGEN...
Page 871 The EBU aligns the address according to the setting of the PORTW bit field. (see Section 13.5.7). CTYPE [11:10] rw Cycle Type This bit field is 00 after reset. In the TC1796, CTYPE must always be written with 00 User’s Manual 13-93 V2.0, 2007-07 EBU, V2.0...
Page 872 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Field Bits Type Description CMULT [15:13] rw Cycle Multiplier Control This bit field specifies a multiplier for the cycles specified via MULTMAP. WAITRDC, WAITWRC, DTARDWR and DTACS always use this multiplier.
Page 873 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Field Bits Type Description BCGEN [21:20] rw Byte Control Signal Control This bit field selects the timing mode of the byte control signals. Byte control signals follow chip select timing.
Page 874 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Field Bits Type Description WRITE Memory Region Write Protection Writes to the memory region are enabled. Writes to the memory region are disabled (default after reset). 12, 7 Reserved Read as 0;...
Page 875: Bus Access Parameter Register, Busapx
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.10.7 Bus Access Parameter Register, BUSAPx EBU_BUSAPx (x = 0-3) EBU Bus Access Parameter Register (100 +x*8 Reset Value: FFFF FFFF ADDRC CMDDELAY WAITRDC WAITWRC BURSTC DATAC RDRECOVC WRRECOVC...
Page 876 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Field Bits Type Description DTARDWR [7:4] Recovery Cycles between Read and Write Accesses This bit field determines the basic number of clock cycles of the Recovery Phase between a read and write access, and vice versa.
Page 877 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Field Bits Type Description DATAC [15:14] rw Data Hold Cycles for Write Accesses This bit field determines the basic number of Data Hold phase clock cycles during write accesses. The total number of Data Hold phase cycles further depends on bit fields EBU_BUSCONx.CMULT and...
Page 878 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Field Bits Type Description WAITRDC [24:22] rw Read Command Phase Cycles This bit field determines the basic number of Command Phase clock cycles during read accesses. The total number of Command Phase clock cycles for read accesses is defined by WAITRDC multiplied by EBU_BUSCONx.CMULT (see also...
Page 879: Emulator Address Select Register, Emuas
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Note: When in external boot mode (see Page 13-21), the reset value of BUSAP0 is overwritten automatically (subsequent to the release of reset) as a result of the external Boot Configuration Value fetch.
Page 880: Emulator Bus Configuration Register, Emubc
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Field Bits Type Description [3:2] Reserved Read as 0; should be written with 0. 13.10.9 Emulator Bus Configuration Register, EMUBC EBU_EMUBC EBU Emulator Bus Configuration Register (168 Reset Value: 0190 2077...
Page 881 The EBU aligns the address according to the setting of the PORTW bit field. (see Section 13.5.7) CTYPE [11:10] rw Cycle Type This bit field is 00 after reset. In the TC1796, CTYPE must always be written with 00 User’s Manual 13-103 V2.0, 2007-07 EBU, V2.0...
Page 882 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Field Bits Type Description CMULT [15:13] rw Cycle Multiplier Control This bit field specifies a multiplier for the cycles specified via MULTMAP. WAITRDC, WAITWRC, DTARDWR and DTACS always use this multiplier.
Page 883 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Field Bits Type Description BCGEN [21:20] rw Byte Control Signal Control This bit field selects the timing mode of the byte control signals. Byte control signals follow chip select timing.
Page 884: Emulator Bus Access Parameter Register, Emubap
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Field Bits Type Description 7, 12 Reserved Read as 0; should be written with 0. 13.10.10 Emulator Bus Access Parameter Register, EMUBAP EBU_EMUBAP EBU Emulator Bus Access Parameter Register...
Page 885 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Field Bits Type Description DTARDWR [7:4] Recovery Cycles between Read and Write Accesses This bit field determines the basic number of clock cycles of the Recovery Phase between a read and write access, and vice versa.
Page 886 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Field Bits Type Description DATAC [15:14] rw Data Hold Cycles for Write Accesses This bit field determines the basic number of Data Hold phase clock cycles during write accesses. The total number of Data Hold phase cycles further depends on bit fields EBU_EMUBC.CMULT and...
Page 887 TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit Field Bits Type Description WAITRDC [24:22] rw Read Command Phase Cycles This bit field determines the basic number of Command Phase clock cycles during read accesses. The total number of Command Phase clock cycles for read accesses is defined by WAITRDC multiplied by EBU_EMUBC.CMULT (see also...
Page 888: Emulator Overlay Register, Emuovl
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.10.11 Emulator Overlay Register, EMUOVL EBU_EMUOVL EBU Emulator Overlay Register (178 Reset Value: 0000 0000 OVERLAY Field Bits Type Description OVERLAY [3:0] Overlay Chip Select Signal The bits of this bit field are used to enable the CS[3:0] chip select lines for the CSOVL overlay chip select generation.
Page 889: Test/Control Configuration Register, Usercon
TC1796 System Units (Vol. 1 of 2) LMB External Bus Unit 13.10.12 Test/Control Configuration Register, USERCON EBU_USERCON EBU Test/Control Configuration Register (190 Reset Value: 0000 0000 Field Bits Type Description Disable Internal Pipelining The EBU can accept a new LMB transaction before the previous LMB transaction has been completed.
Page 890: Interrupt System
“interrupt requests” in this document because they can be serviced by either of the service providers. Each peripheral unit in the TC1796 can generate service requests. Additionally, the Bus Control Units, the Debug Unit, the PCP, and even the CPU itself can generate service requests to either of the two service providers.
Page 891 SBCU 2 SRNs 1 SRN RBCU 1 SRN 8 SRNs Flash 1 SRN 1 SRN Cerberus Ext. Int. 2 SRNs 1 SRN Software MCB05742 Figure 14-1 Block Diagram of the TC1796 Interrupt System User’s Manual 14-2 V2.0, 2007-07 Interrupt, V2.0...
Page 892: Service Request Nodes
14.2 Service Request Nodes In total, there are 181 Service Request Nodes available in the TC1796. Each SRN contains a Service Request Control Register and interface logic that connects it to the triggering unit and to the two interrupt arbitration buses. Some peripheral units of the TC1796 have multiple SRNs.
Page 893: General Service Request Control Register Layout
TC1796 System Units (Vol. 1 of 2) Interrupt System 14.2.1.1 General Service Request Control Register Layout mod_SRC Service Request Control Register Reset Value: 0000 0000 SRR SRE SRPN Field Bits Type Description SRPN [7:0] Service Request Priority Number Service request is never serviced Service request is on lowest priority …...
Page 894: Request Set And Clear Bits (Setr, Clrr)
TC1796 System Units (Vol. 1 of 2) Interrupt System Field Bits Type Description SETR Request Set Bit SETR is required to set SRR. No action Set SRR; bit value is not stored; read always returns 0; no action if CLRR is set also.
Page 895: Service Request Flag (Srr)
14.2.1.5 Type-Of-Service Control (TOS) There are two service providers for service requests in the TC1796, the CPU and the PCP. The TOS bit is used to select whether a service request generates an interrupt to the CPU (TOS = 0) or to the PCP (TOS = 1).
Page 896: Service Request Priority Number (Srpn)
This means that the TC1796 Interrupt Vector Table is ordered by priority number. This is unlike traditional interrupt architectures in which their interrupt vector tables are ordered by the source of the interrupt. The TC1796 Interrupt Vector Table allows a single peripheral can have multiple priorities for different purposes.
Page 897: Interrupt Control Units
The TC1796 contains two interrupt control units, one for the CPU (called ICU), and one for the PCP (called PICU). Each one controls its associated interrupt arbitration bus and...
Page 898 TC1796 System Units (Vol. 1 of 2) Interrupt System Field Bits Type Description Global Interrupt Enable Bit The interrupt enable bit globally enables the CPU service request system. Whether or not a service request is delivered to the CPU depends on the individual Service Request Enable Bits (SRE) in the SRNs, and the current state of the CPU.
Page 899: Operation Of The Interrupt Control Unit (Icu)
TC1796 System Units (Vol. 1 of 2) Interrupt System 14.3.1.2 Operation of the Interrupt Control Unit (ICU) Service-request arbitration is performed in the ICU in parallel with normal CPU operation. When a triggering event occurs in one or more interrupt sources, the associated SRNs, if enabled, send service requests to the CPU through the ICU.
Page 900: Pcp Interrupt Control Unit (Picu)
TC1796 System Units (Vol. 1 of 2) Interrupt System If a new service request is received by the ICU before the CPU has acknowledged the pending interrupt request, the ICU deactivates the pending request and starts a new arbitration process. This reduces the latency of service requests posted before the current request is acknowledged.
Page 901: Arbitration Process
In a real-time system where responsiveness is critical, arbitration must be as fast as possible. However, to maintain flexibility, the TC1796 system is designed to have a large range of service priorities. If not all priorities are needed in a system, arbitration can be speeded up by not examining all the bits used to identify all 255 unique priorities.
Page 902: Controlling The Duration Of Arbitration Cycles
During each arbitration cycle, the rate of information flow between the SRNs and the ICU can become limited by propagation delays within the TC1796 when it is executing at high system clock frequencies. At high frequencies, arbitration cycles may require two system clocks to execute properly.
Page 903: Exiting An Interrupt Service Routine
TC1796 System Units (Vol. 1 of 2) Interrupt System As explained, receipt of further interrupts is disabled (ICR.IE = 0) when an Interrupt Service Routine is entered. At the same time, the current CPU priority ICR.CCPN is set by hardware to the priority of the interrupting source (ICR.PIPN).
Page 904: Interrupt Vector Table
TC1796 System Units (Vol. 1 of 2) Interrupt System 14.7 Interrupt Vector Table Interrupt Service Routines (ISRs) are associated with interrupts at a particular priority by way of the Interrupt Vector Table. The Interrupt Vector Table is an array of ISR entry points.
Page 905 ISR residing elsewhere in memory. Due to the way the vector table is organized according to the interrupt priorities, the TC1796 offers an additional option by allowing spanning several Interrupt Vector Table entries so long as those entries are otherwise unused.
Page 906 TC1796 System Units (Vol. 1 of 2) Interrupt System Interrupt Vector Table Priority Number 8 Words PN = 255 8 Words PN = 5 Service PN = 4 Routine (may not be used may span if spanned by ISR several...
Page 907: Usage Of The Tc1796 Interrupt System
System Units (Vol. 1 of 2) Interrupt System 14.8 Usage of the TC1796 Interrupt System The following sections provide some examples of using the TC1796 interrupt system to solve both typical and special application requirements. 14.8.1 Spanning Interrupt Service Routines Across Vector Entries Each Interrupt Vector Table entry consists of eight words of memory.
Page 908: Configuring Ordinary Interrupt Service Routines
The TC1796 interrupt architecture can be used to create such interrupt priority groups. It is effected by managing the current CPU priority level ICR.CCPN in a way described in this section.
Page 909: Splitting Interrupt Service Across Different Priority Levels
Interrupt priority groups demonstrate the power of the TC1796 priority-based interrupt- ordering system. Thus the flexibility of interrupt priority levels ranges from all interrupts in one group to each interrupt request building its own group, and to all possible combinations in between.
Page 910: Using Different Priorities For The Same Interrupt Source
In the TC1796, however, the extra check and branch in the ISR are not necessary, which reduces the interrupt latency.
Page 911: Interrupt Priority 1
SRNs and interrupt priority numbers that are not being used for hardware interrupts. The TC1796 contains four SRNs that support software-initiated interrupts. These SRNs are not connected to peripheral modules and can only cause interrupts when software sets its SRR bit.
Page 912: Service Request Node Table
TC1796 System Units (Vol. 1 of 2) Interrupt System 14.9 Service Request Node Table Table 14-2 shows all TC1796 Service Request Nodes. Table 14-2 Service Request Nodes in the TC1796 Module No. of Description SRC Register Nodes CPU Service Request Nodes [3:0]...
Page 913 TC1796 System Units (Vol. 1 of 2) Interrupt System Table 14-2 Service Request Nodes in the TC1796 (cont’d) Module No. of Description SRC Register Nodes ASC1 ASC1 Transmit Interrupt Service Request ASC1_TSRC Node ASC1 Receive Interrupt Service Request Node ASC1_RSRC...
Page 914: Non-Maskable Interrupt
Although called an interrupt, the Non-Maskable Interrupt (NMI) is actually serviced as a trap, since it is not interruptible and does not follow the standards for regular interrupts. In the TC1796, four different events can generate an NMI trap: •...
Page 915: Sram Parity Error Nmi
TC1796 System Units (Vol. 1 of 2) Interrupt System 14.10.4 SRAM Parity Error NMI If an SRAM parity error is detected in an SRAM memory block that is enabled for parity error detection (corresponding enable bit SCU_PETCR.PENx is set), the NMIPER flag in register NMISR is set together with related parity error flag SCU_PETSR.PFLx.
Page 916: Nmi Enable
TC1796 System Units (Vol. 1 of 2) Interrupt System 14.10.5 NMI Enable After reset, the NMI is disabled. It must be enabled by the user program when the NMI handler routine has been setup. The NMI is enabled by setting bit SCU_CON.NMIEN.
Page 917 TC1796 System Units (Vol. 1 of 2) Interrupt System Field Bits Type Description NMIPLL PLL NMI Flag This flag indicates whether or not a PLL NMI request has occurred. No PLL NMI has occurred. The PLL has lost the lock to the external crystal (becomes unlocked).
Page 918: System Timer
STM is enabled and immediately starts counting up. It is not possible to affect the content of the STM during normal operation of the TC1796. The timer registers can only be read but not written to.
Page 919 TC1796 System Units (Vol. 1 of 2) System Timer to count between the two load operations, there is a chance that the two values read are not be consistent (due to possible overflow from the low part of the timer to the high part between the two read operations).
Page 920 TC1796 System Units (Vol. 1 of 2) System Timer STM Module Compare Register 0 STM_CMP0 Compare Register1 STM_CMP1 STMIR1 Interrupt 56-Bit System Timer Control STMIR0 Enable / STM_CAP Disable Clock Control STM_TIM6 STM_TIM5 Address STM_TIM4 Decoder STM_TIM3 PORST STM_TIM2 STM_TIM1...
Page 921: Resolution And Ranges
TC1796 System Units (Vol. 1 of 2) System Timer 15.2.1 Resolution and Ranges Table 15-1 is an overview on the individual timer registers with their resolutions and timing ranges. As an example, the values for a 75 and 37.5 MHz STM input clock frequency are given.
Page 922: Compare Register Operation
TC1796 System Units (Vol. 1 of 2) System Timer 15.2.2 Compare Register Operation The content of the 56-bit STM can be compared to the content of two compare values stored in the STM_CMP0 and STM_CMP1 registers. Interrupts can be generated on a compare match of the STM with the STM_CMP0 or STM_CMP1 registers.
Page 923: Compare Match Interrupt Control
STMIR1 outputs are each connected to an interrupt service request control registers, STM_SRC0 and STM_SCR1. These registers control the general interrupt handling and processing as described in Chapter 14 of this TC1796 System Units (Vol. 1 of 2) User’s Manual. Compare Match from CMP0 Register Set ≥1...
Page 924: Kernel Registers
This section describes the kernel registers of the STM. The STM registers can be divided into four types, as shown in Figure 15-4. Note: In the TC1796, all kernel registers are readable in suspend mode. STM Registers Overview General Module Timer/Capture...
Page 925 TC1796 System Units (Vol. 1 of 2) System Timer Table 15-3 Registers Overview - STM Registers Register Register Long Name Offset Description Short Name Address STM_CLC STM Clock Control Register Page 15-9 STM_ID STM Module Identification Register Page 15-10 STM_TIM0...
Page 926: General Module Register
TC1796 System Units (Vol. 1 of 2) System Timer 15.3.1 General Module Register The STM Clock Control Register is used to switch the STM on or off and to control its input clock rate. After a power-on reset, the STM is always enabled and starts counting.
Page 927 TC1796 System Units (Vol. 1 of 2) System Timer Field Bits Type Description [10:8] Clock Divider in Run Mode No clock signal generated Clock signal selected (default after reset) Clock signal / 2 selected Clock signal / 3 selected Clock signal...
Page 928: Timer/Capture Registers
TC1796 System Units (Vol. 1 of 2) System Timer 15.3.2 Timer/Capture Registers Registers STM_TIM1 to STM_TIM6 provide 32-bit views at varying resolutions of the underlying STM counter. STM_TIM0 STM Timer Register 0 Reset Value: 0000 0000 STM[31:0] Field Bits Type Description...
Page 929 TC1796 System Units (Vol. 1 of 2) System Timer STM_TIM2 STM Timer Register 2 Reset Value: 0000 0000 STM[39:8] Field Bits Type Description STM[39:8] [31:0] System Timer Bits [39:8] This bit bield contains bits [39:8] of the 56-bit STM. STM_TIM3...
Page 930 TC1796 System Units (Vol. 1 of 2) System Timer STM_TIM5 STM Timer Register 5 Reset Value: 0000 0000 STM[51:20] Field Bits Type Description STM[51:20] [31:0] System Timer Bits [51:20] This bit bield contains bits [51:20] of the 56-bit STM. STM_TIM6...
Page 931 TC1796 System Units (Vol. 1 of 2) System Timer STM_CAP STM Timer Capture Register Reset Value: 0000 0000 24 23 STM_CAP[55:32] Field Bits Type Description STM[55:32] [23:0] Captured System Timer Bits [55:32] The capture register STM_CAP always captures the STM bits [55:32] when one of the registers STM_TIM0 to STM_TIM5 is read.
Page 932: Compare Registers
TC1796 System Units (Vol. 1 of 2) System Timer 15.3.3 Compare Registers The STM Compare Register holds up to 32-bits; its value is compared to the value of the STM. STM_CMPx (x = 0-1) STM Compare Register x +x*4 Reset Value: 0000 0000...
Page 933 TC1796 System Units (Vol. 1 of 2) System Timer The STM Compare Match Control Register controls the parameters of the compare logic. STM_CMCON STM Compare Match Control Register Reset Value: 0000 0000 MSTART1 MSIZE1 MSTART0 MSIZE0 Field Bits Type Description...
Page 934 TC1796 System Units (Vol. 1 of 2) System Timer Field Bits Type Description MSIZE1 [20:16] Compare Register Size for CMP1 This bit field determines the number of bits in register CMP1 (starting from bit 0) that are used for the compare operation with the STM.
Page 935: Interrupt Registers
TC1796 System Units (Vol. 1 of 2) System Timer 15.3.4 Interrupt Registers The two compare match interrupts of the STM are controlled by the STM Interrupt Control Register. STM_ICR STM Interrupt Control Register Reset Value: 0000 0000 Field Bits Type Description...
Page 936 TC1796 System Units (Vol. 1 of 2) System Timer Field Bits Type Description CMP0OS Compare Register CMP0 Interrupt Output Selection This bit determines the interrupt output that is activated on a compare match event of compare register CMP0. Interrupt output STMIR0 selected...
Page 937 TC1796 System Units (Vol. 1 of 2) System Timer The bits in the STM Interrupt Set/Reset Register make it possible to set or clear the compare match interrupt request status flags of register ICR. STM_ISRR STM Interrupt Set/Reset Register Reset Value: 0000 0000...
Page 938 TC1796 System Units (Vol. 1 of 2) System Timer In the TC1796, the compare match interrupt output signals of the STM, STMIR0 and STMIR1, are controlled by the STM Service Request Control Registers STM_SRC0 and STM_SRC1. STM_SRC0 STM Service Request Control Register 0...
Page 939: Watchdog Timer
The WDT provides a highly reliable and secure way to detect and recover from software or hardware failure. The WDT helps to abort an accidental malfunction of the TC1796 in a user-specified time period. When enabled, the WDT will cause the TC1796 system to be reset if the WDT is not serviced within a user-programmable time period.
Page 940: Features Of The Watchdog Timer
Double Reset Detection: If a Watchdog induced reset occurs twice, a severe system malfunction is assumed and the TC1796 is held in reset until a power-on or hardware reset occurs. This prevents the device from being periodically reset if, for instance, connection to the external memory has been lost such that even system initialization could not be performed.
Page 941: The Endinit Function
Because understanding of the ENDINIT bit and its function is an important prerequisite for the descriptions in the following sections, its function is explained first. There are a number of registers in the TC1796 that are usually programmed only once during the initialization sequence of the application. Modification of such registers during normal application run can have a severe impact on the overall operation of modules or the entire system.
Page 942 TC1796 System Units (Vol. 1 of 2) Watchdog Timer Table 16-1 TC1796 Registers Protected via the Endinit Feature Registers Description mod_CLC All clock control registers of the individual peripheral modules are Endinit-protected. mod_FDR All clock fractional divider registers of the individual peripheral modules are Endinit-protected.
Page 943: Watchdog Timer Operation
TC1796 System Units (Vol. 1 of 2) Watchdog Timer 16.4 Watchdog Timer Operation The following sections describe the registers, the operation, and different modes of the WDT, as well as the Password Access mechanism. Figure 16-2 gives an example for the operation of the WDT.
Page 944: Wdt Register Overview
TC1796 System Units (Vol. 1 of 2) Watchdog Timer 16.4.1 WDT Register Overview Two control registers, WDT_CON0 and WDT_CON1, and one status register, WDT_SR, serve for communication of the software with the WDT. This section provides a short overview and describes the access mechanisms of the WDT registers. Detailed layout...
Page 945: Operating Modes Of The Watchdog Timer
TC1796 System Units (Vol. 1 of 2) Watchdog Timer 16.4.2 Operating Modes of the Watchdog Timer The WDT can operate in one of four different operating modes: • Time-Out Mode • Normal Mode • Disable Mode • Prewarning Mode The following overview describes these modes and how the WDT changes from one mode to the other.
Page 946: Time-Out Mode
WDT is performed, or if the timer overflows before ENDINIT is set to 1, a WDT Non-Maskable Interrupt request (WDT_NMI) is requested, and Prewarning Mode is entered. A reset of the TC1796 is imminent and can no longer be stopped.
Page 947: Prewarning Mode
WDT_CON0. Instead of immediately generating a reset of the device, as other WDTs do, the TC1796 WDT provides the system with a chance to save important state information before the reset occurs. This is done through first activating an NMI trap request to the CPU, warning it about the coming reset (reset prewarning).
Page 948: Password Access To Wdt_Con0
TC1796 System Units (Vol. 1 of 2) Watchdog Timer 16.4.3 Password Access to WDT_CON0 A correct password must be written to register WDT_CON0 in order to unlock it for modifications. Software must either know the correct password in advance, or it can compute it at runtime.
Page 949: Modify Access To Wdt_Con0
TC1796 System Units (Vol. 1 of 2) Watchdog Timer 16.4.4 Modify Access to WDT_CON0 If WDT_CON0 is successfully unlocked as described on Page 16-10, the following write access to WDT_CON0 can modify it. However, this access must also meet certain requirements in order to be accepted and regarded as valid.
Page 950: Term Definitions For Wdt_Con0 Accesses
TC1796 System Units (Vol. 1 of 2) Watchdog Timer 16.4.5 Term Definitions for WDT_CON0 Accesses To simplify the descriptions in the following sections, a number of terms are defined to indicate the type of access to register WDT_CON0: Watchdog Access Sequence: Two accesses to register WDT_CON0 consisting of first a Password Access followed by a Modify Access.
Page 951: Detailed Descriptions Of The Wdt Modes
TC1796 System Units (Vol. 1 of 2) Watchdog Timer 16.4.6 Detailed Descriptions of the WDT Modes The following subsections provide detailed descriptions of each of the modes of the WDT. The entry conditions and actions, operation in this mode, as well as exit conditions and the succeeding mode are listed for each mode.
Page 952: Normal Mode Details
TC1796 System Units (Vol. 1 of 2) Watchdog Timer Table 16-4 WDT Time-Out Mode (cont’d) State / Description Action Exit 1. Writing ENDINIT to 1 with a Valid Modify Access (a Valid Password Access must have been executed first). 2. Timer WDTTIM overflows from FFFF to 0000 3.
Page 953: Disable Mode Details
TC1796 System Units (Vol. 1 of 2) Watchdog Timer 16.4.6.3 Disable Mode Details Disable Mode is provided for applications that truly do not require the WDT function. It can only be entered from Time-Out Mode if bit WDT_CON1.WDTDR is set to 1 before proper termination of Time-Out Mode.
Page 954: Prewarning Mode Details
TC1796 System Units (Vol. 1 of 2) Watchdog Timer 16.4.6.4 Prewarning Mode Details Prewarning Mode is always entered immediately after a Watchdog error condition was detected. This can be either an access error to register WDT_CON0 or an overflow of the counter in Normal or Time-Out Mode.
Page 955: Wdt Operation During Power-Saving Modes
Double Watchdog Errors and suspends all system operations after the second reset occurs. This feature prevents the TC1796 from executing random wrong code for longer than the Time-out Period, and prevents the TC1796 from being repeatedly reset by the WDT.
Page 956: Determining Wdt Periods
TC1796 System Units (Vol. 1 of 2) Watchdog Timer The purpose of the Double Watchdog Error feature is to avoid loops such as: Reset - software does not start correctly - prewarning - watchdog reset - software does not start correctly - …...
Page 957 TC1796 System Units (Vol. 1 of 2) Watchdog Timer Time-out Period After Reset After reset, the initial count value for the timer is fixed at FFFC when the WDT clock starts running. The WDT counts up at a rate determined by WDT_SR.WDTIS, which is 0 after any reset ( /16384).
Page 958: Normal Period
TC1796 System Units (Vol. 1 of 2) Watchdog Timer Note: In Prewarning Mode, the device does not need to wait for the end of the Time-out Period and the reset. After having saved required state in the NMI routine, software can execute a software reset to shorten the time. However, the state of...
Page 959: Wdt Period During Power-Saving Modes
TC1796 System Units (Vol. 1 of 2) Watchdog Timer 16.4.7.3 WDT Period During Power-Saving Modes Care needs to be taken when programming the WDT reload value before going to Idle or Sleep Mode. As described on Page 16-17, the state of bit 15 of the Watchdog counter is used to wake-up from these modes.
Page 960: Handling The Watchdog Timer
TC1796 System Units (Vol. 1 of 2) Watchdog Timer 16.5 Handling the Watchdog Timer This section describes methods of handling the WDT function. 16.5.1 System Initialization After any reset, the WDT is put in Time-Out Mode, and WDT_CON0.ENDINIT is 0, providing access to sensitive system registers.
Page 961: Re-Opening Access To Critical System Registers
TC1796 System Units (Vol. 1 of 2) Watchdog Timer Bit fields WDT_CON0.WDTREL and WDT_CON0.WDTPW can optionally be changed during the Valid Modify Access, but it is not required. WDT_CON0.ENDINIT can be set to 1 or 0; however, setting ENDINIT to 0 does not stop Time-Out Mode. Any values written to WDTREL, WDTPW, and ENDINIT are stored in WDT_CON0, and WDT_CON0 is automatically locked (WDTLCK = 1) after the Modify Access is finished.
Page 962: Handling The User-Definable Password Field
TC1796 System Units (Vol. 1 of 2) Watchdog Timer 16.5.4 Handling the User-Definable Password Field WDT_CON0.WDTPW is an 8-bit field that can be set by software to any arbitrary value during a Modify Access. Settings of this bit field have no effect on the operation of the...
Page 963 TC1796 System Units (Vol. 1 of 2) Watchdog Timer Password access: write xy to WDTPW Service Sequence Modify access: set WDTPW to 10 Next expected WDTPW = 10 Multiple Omission Execution Password access: of Service: of Service: write 10 to WDTPW...
Page 964 TC1796 System Units (Vol. 1 of 2) Watchdog Timer service sequence if all the expected paths and calculation routines have been executed properly. If one or more steps were omitted or a wrong path was executed due to a malfunction, the Watchdog failure mechanism will detect this and issue a reset of the device (after the prewarning phase).
Page 965: Determining The Required Values For A Wdt Access
TC1796 System Units (Vol. 1 of 2) Watchdog Timer 16.5.5 Determining the Required Values for a WDT Access As described on Page 16-10 Page 16-11, the values required for the password and Modify Accesses to register WDT_CON0 are designed such that they can be derived from the values read from registers WDT_CON0 and WDT_CON1.
Page 966: Watchdog Timer Registers
TC1796 System Units (Vol. 1 of 2) Watchdog Timer 16.6 Watchdog Timer Registers This section describes the WDT registers. The WDT is provided with three registers: WDT_CON0, WDT_CON1, and WDT_SR, as shown in Figure 16-6. They are located inside the SCU module’s address range.
Page 967: Watchdog Timer Control Register 0
TC1796 System Units (Vol. 1 of 2) Watchdog Timer 16.6.1 Watchdog Timer Control Register 0 Register WDT_CON0 manages the Password Access to the WDT. It also stores the timer reload value, a user-definable password field, a lock bit, and the End-of- Initialization control bit.
Page 968 TC1796 System Units (Vol. 1 of 2) Watchdog Timer Field Bits Type Description WDTLCK Lock Bit to Control Access to WDT_CON0 Register WDT_CON0 is unlocked. Register WDT_CON0 is locked (default after reset). The actual value of WDTLCK is controlled by hardware.
Page 969: Watchdog Timer Control Register 1
TC1796 System Units (Vol. 1 of 2) Watchdog Timer 16.6.2 Watchdog Timer Control Register 1 WDT_CON1 manages operation of the WDT. It includes the disable request and frequency selection bits. It is ENDINIT-protected. WDT_CON1 Watchdog Timer Control Register 1 Reset Value: 0000 0000...
Page 970: Watchdog Timer Status Register
TC1796 System Units (Vol. 1 of 2) Watchdog Timer Field Bits Type Description [1:0], Reserved [31:4] Read as 0; should be written with 0. 16.6.3 Watchdog Timer Status Register Register WDT_SR shows the current state of the WDT. Status include bits indicating reset prewarning, Time-out, enable/disable status, input clock status, and access error status.
Page 971 TC1796 System Units (Vol. 1 of 2) Watchdog Timer Field Bits Type Description WDTOE Watchdog Overflow Error Status Flag No Watchdog overflow error. A Watchdog overflow error has occurred. This bit is set by hardware when the WDT overflows from FFFF to 0000 .
Page 972 TC1796 System Units (Vol. 1 of 2) Watchdog Timer Field Bits Type Description WDTPR Watchdog Prewarning Mode Flag Normal mode (default after reset) The Watchdog is operating in Prewarning Mode This bit is set to 1 when a Watchdog error is detected.
Page 973: On-Chip Debug Support
On-Chip Debug Support On-Chip Debug Support This chapter gives an overview on the debug features of the TC1796 device. This chapter does not describe the TC1796 debug functionality and capabilities in detail. For detailed information about the On-Chip Debug Support (OCDS) functionality (e.g.
Page 974 TC1796 System Units (Vol. 1 of 2) On-Chip Debug Support TC1796. For detailed information about the TC1796ED functionality (e.g. required by high-end emulation manufacturers), please contact local Infineon representatives. Figure 17-1 is a block diagram of the TC1796 OCDS based system.
Page 975 TC1796 System Units (Vol. 1 of 2) On-Chip Debug Support • OCDS Level 1 module of PCP • OCDS Level 2 interface of PCP • OCDS Level 1 module in the BCU of the System Peripheral Bus (SBCU) • OCDS Level 1 module in the BCU of the Remote Peripheral Bus (RBCU) •...
Page 976: Ocds Level 1
1. The debugger software, supporting a standard JTAG protocol via a PC port 2. The debugger hardware interface adapter, connecting the TC1796 JTAG interface in the target system with the PC port (parallel, serial, or USB) This configuration makes it possible to realize a cheap debugging environment that permits comprehensive real-time debugging tasks to be performed.
Page 977: Basic Concept
– High priority requests can still be serviced when the core is in emulation mode, by interrupting the monitor program. 17.2.1.1 Basic Concept The TriCore CPU in the TC1796 provides OCDS with the following two basic parts: • Debug Event Trigger Generation •...
Page 978: Debug Event Generation
Activation of the External Break Input Pin BRKIN When activating the TC1796 device pin BRKIN = 0, the MCBS unit induces a break event as specified in a External Break Input Event Specifier Register EXEVT.
Page 979: Debug Actions
TC1796 System Units (Vol. 1 of 2) On-Chip Debug Support Execution of a MTCR/MFCR Instruction In order to protect the emulator resource, a debug event is raised whenever a MTCR or MFCR instruction is used to read or modify an user core SFR, but an event is not raised when the user reads or modifies one of the dedicated core debug registers: •...
Page 980: Tricore Ocds Registers
TC1796 System Units (Vol. 1 of 2) On-Chip Debug Support 17.2.1.4 TriCore OCDS Registers Figure 17-4 shows the TriCore OCDS registers in an overview. CPU OCDS Registers DBGSR EXEVT CREVT SWEVT TR0EVT TR1EVT CPU_SBSRC0 MCA05759 Figure 17-4 TriCore Core Debug Registers...
Page 981: Bcu Ocds Level 1
On-Chip Debug Support 17.2.3 BCU OCDS Level 1 The BCUs of the two FPI buses inside the TC1796 support OCDS Level 1, which offers very comfortable and powerful means for breakpoint generation. Each BCU (SBCU, RBCU) contains one comparator each for •...
Page 982: Ocds Level 2 Debugging Via Trace Port
TC1796 System Units (Vol. 1 of 2) On-Chip Debug Support 17.3 OCDS Level 2 Debugging via Trace Port The OCDS Level 2 debug support extends the OCDS Level 1 debug functionalities with an additional 16-bit wide trace port TR[15:0] with the trace clock TRCLK. The trace port extension makes it possible to output one out of four types of trace output signals: •...
Page 983: Concurrent Debugging
TC1796 System Units (Vol. 1 of 2) On-Chip Debug Support 17.3.3 Concurrent Debugging A limited concurrent debugging is possible for CPU and DMA. It is not possible to trace CPU and DMA at the same time. But when the trace port is assigned to the DMA Controller, the break-in and break-out features of the CPU can be used at the same time.
Page 984: Debug Interface (Cerberus)
TC1796 System Units (Vol. 1 of 2) On-Chip Debug Support 17.4 Debug Interface (Cerberus) The Cerberus module is the on-chip unit that controls all OCDS Level 1 and 2 main debug functions. Generally, the Cerberus should not be used by any application software, since this could disturb the emulation tool behavior.
Page 985: Communication Mode
17.4.4 Multi Core Break Switch In the TC1796 there are two main processor units, the CPU and the PCP2. For debugging purposes, the OCDS run control of one processor unit can break (interrupt) the other processor unit or vice versa. This run control tasks are handled by the MCBS unit which is a part of the Cerberus.
Page 986 TC1796 System Units (Vol. 1 of 2) On-Chip Debug Support TriCore BRKIN BRKOUT BRKIN Multi Core BRKIN Break PCP2 BRKOUT Switch BRKOUT (MCBS) BRKOUT Signals DMA, SBCU, RBCU, MLI0, MLI1 MCA05760_mod Figure 17-5 Break Switch Interfaces The MCBS unit supports the following features: •...
Page 987: Jtag Interface
JTAG port can be used during normal device operation as an ideal interface for debugging tasks. On the other hand, the TC1796 OCDS is designed to support complex multi- core/debugging environments. The challenge here is that several debugger applications may have to share a single resource, i.e.
Page 988: Cerberus And Jtag Registers
TC1796 System Units (Vol. 1 of 2) On-Chip Debug Support 17.6 Cerberus and JTAG Registers This section summarizes all Cerberus and JTAG registers for reference purposes. Details on these registers are contained in OCDS documents that are available for tool suppliers on request (please contact local Infineon representatives).
Page 989 TC1796 System Units (Vol. 1 of 2) On-Chip Debug Support Table 17-3 JTAG/Cerberus Register Overview (cont’d) Register Register Long Name Address Short Name CBS_OSTATE Cerberus OSCU Status Register F000 0480 CLIENT_ID Cerberus JTAG Client Identification Register (32-bit) IOCONF Configuration Register (12-bit)
Page 990: Register Overview
Register Overview Register Overview This chapter describes all registers of the TC1796 that are located is segment 15. It also describes the read/write access rights of the specific address ranges/registers. Throughout the tables in this chapter, the “Access Mode” “Read” and “Write”, and “Reset Values”...
Page 991: Address Map Of Segment 15
TC1796 System Units (Vol. 1 of 2) Register Overview 18.1 Address Map of Segment 15 Table 18-2 shows the block address map of Segment 15. Table 18-2 Block Address Map of Segment 15 Unit Address Access Mode Size Range Read...
Page 992 TC1796 System Units (Vol. 1 of 2) Register Overview Table 18-2 Block Address Map of Segment 15 (cont’d) Unit Address Access Mode Size Range Read Write Port 5 F000 1100 256 byte F000 11FF Page 18-27 Port 6 F000 1200...
Page 993 TC1796 System Units (Vol. 1 of 2) Register Overview Table 18-2 Block Address Map of Segment 15 (cont’d) Unit Address Access Mode Size Range Read Write PCP2 Registers F004 3F00 256 byte F004 3FFF Page 18-77 Reserved F004 4000 –...
Page 994 TC1796 System Units (Vol. 1 of 2) Register Overview Table 18-2 Block Address Map of Segment 15 (cont’d) Unit Address Access Mode Size Range Read Write Micro Link Interface 1 (MLI1) F010 C100 256 byte F010 C1FF Page 18-100 Memory Checker (MCHK)
Page 995 TC1796 System Units (Vol. 1 of 2) Register Overview Table 18-2 Block Address Map of Segment 15 (cont’d) Unit Address Access Mode Size Range Read Write Flash Register F800 1000 5 Kbyte F800 23FF Page 18-117 Reserved F800 2400 –...
Page 996: Registers Tables
TC1796 System Units (Vol. 1 of 2) Register Overview 18.2 Registers Tables Table 18-3 up to Table 18-42 show the address maps with all register of segment 15. Note: Addresses listed in columns “Address” are always word (32-bit) addresses. Table 18-3...
Page 997 TC1796 System Units (Vol. 1 of 2) Register Overview Table 18-3 Address Map of SCU and WDT (cont’d) Short Name Description Address Access Mode Reset Value Read Write SCU_SCLIR SCU Software F000 0038 U, SV BE 0000 XXXX Configuration Latched Inputs Register –...
Page 998 TC1796 System Units (Vol. 1 of 2) Register Overview Table 18-3 Address Map of SCU and WDT (cont’d) Short Name Description Address Access Mode Reset Value Read Write EICR1 External Input Channel F000 0084 U, SV U, SV 0000 0000...
Page 999 TC1796 System Units (Vol. 1 of 2) Register Overview Table 18-3 Address Map of SCU and WDT (cont’d) Short Name Description Address Access Mode Reset Value Read Write SCU_ SCU Parity Error Trap F000 00D4 U, SV BE 0000 0000...
Page 1000 TC1796 System Units (Vol. 1 of 2) Register Overview Table 18-4 Address Map of SBCU Short Name Description Address Access Mode Reset Value Read Write System Peripheral Bus Control Unit (SBCU) – Reserved F000 0100 – F000 0104 SBCU_ID SBCU Module...

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