Infineon Technologies XC2200 Manuals

Manuals and User Guides for Infineon Technologies XC2200. We have 1 Infineon Technologies XC2200 manual available for free PDF download: User Manual

Infineon Technologies XC2200 User Manual

Infineon Technologies XC2200 User Manual (677 pages)

16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

Brand: Infineon Technologies | Category: Controller | Size: 6 MB

Table of Contents

Summary of Chapters

5
- Table of Contents
  6
Table of Contents

7
1 Introduction

18
- Members of the 16-Bit Microcontroller Family
  20
- Summary of Basic Features
  22
- Abbreviations
  26
- Naming Conventions
  27
2 Architectural Overview

28
3 Memory Organization

62
- Address Mapping
  64
- Special Function Register Areas
  66
- Data Memory Areas
  70
- Program Memory Areas
  72
- Program/Data SRAM (PSRAM)
  73
- Non-Volatile Program Memory (Flash)
  74
- System Stack
  75
- IO Areas
  76
- External Memory Space
  77
- Crossing Memory Boundaries
  78
- Embedded Flash Memory
  79
- Definitions
  79
- Operating Modes
  81
- Operations
  83
- Details of Command Sequences
  86
- Data Integrity
  96
- Protection Handling Details
  99
- Protection Handling Examples
  104
- EEPROM Emulation
  108
- Interrupt Generation
  110
- Recommendations for Optimized Flash Usage
  110
- On-Chip Program Memory Control
  112
- Overview
  112
- Register Interface
  114
- Startup, Shutdown
  129
- Error Reporting Summary
  130
- Data Retention Memories
  131
- Stand-By RAM Accesses
  132
- Stand-By RAM Registers
  134
4 Central Processing Unit (CPU)

139
- Components of the CPU
  142
- Instruction Fetch and Program Flow Control
  143
- Branch Detection and Branch Prediction Rules
  145
- Correctly Predicted Instruction Flow
  145
- Incorrectly Predicted Instruction Flow
  147
- Instruction Processing Pipeline
  149
- Pipeline Conflicts Using General Purpose Registers
  151
- Pipeline Conflicts Using Indirect Addressing Modes
  153
- Pipeline Conflicts Due to Memory Bandwidth
  155
- Pipeline Conflicts Caused by CPU-SFR Updates
  158
- CPU Configuration Registers
  164
- Use of General Purpose Registers
  167
- GPR Addressing Modes
  169
- Context Switching
  171
- Code Addressing
  175
- Data Addressing
  177
- Short Addressing Modes
  177
- Long Addressing Modes
  179
- Indirect Addressing Modes
  182
- DSP Addressing Modes
  184
- The System Stack
  190
- Standard Data Processing
  194
- 16-Bit Adder/Subtracter, Barrel Shifter, and 16-Bit Logic Unit
  198
- Bit Manipulation Unit
  198
- Multiply and Divide Unit
  200
- DSP Data Processing (MAC Unit)
  202
- MAC Unit Control
  203
- Representation of Numbers and Rounding
  203
- The 16-Bit by 16-Bit Signed/Unsigned Multiplier and Scaler
  204
- Concatenation Unit
  204
- One-Bit Scaler
  204
- The 40-Bit Adder/Subtracter
  204
- The Data Limiter
  205
- The Accumulator Shifter
  205
- The 40-Bit Signed Accumulator Register
  206
- The MAC Unit Status Word MSW
  208
- The Repeat Counter MRW
  210
- Constant Registers
  212
5 Interrupt and Trap Functions

213
- Interrupt System Structure
  214
- Interrupt Arbitration and Control
  216
- Interrupt Vector Table
  223
- Operation of the Peripheral Event Controller Channels
  232
- The PECC Registers
  232
- The PEC Source and Destination Pointers
  236
- PEC Transfer Control
  238
- Channel Link Mode for Data Chaining
  240
- PEC Interrupt Control
  241
- Prioritization of Interrupt and PEC Service Requests
  243
- Context Switching and Saving Status
  245
- Interrupt Node Sharing
  248
- External Interrupts
  249
- OCDS Requests
  251
- Service Request Latency
  252
- Trap Functions
  254
6 System Control Unit (SCU)

261
- Clock Generation Unit
  262
- Overview
  262
- Trimmed Current Controlled Wake-Up Clock (OSC_WU)
  264
- High Precision Oscillator Circuit (OSC_HP)
  264
- Phase-Locked Loop (PLL) Module
  265
- Clock Control Unit
  275
- External Clock Output
  280
- CGU Registers
  283
- Wake-Up Timer (WUT)
  304
- Wake-Up Timer Operation
  304
- WUT Registers
  306
- Reset Operation
  309
- Reset Architecture
  309
- General Reset Operation
  311
- Debug Reset Assertion
  313
- Coupling of Reset Types
  313
- Reset Request Trigger Sources
  314
- Module Reset Behavior
  316
- Reset Controller Registers
  318
- External Service Request (ESR) Pins
  328
- General Operation
  328
- ESR Control Registers
  335
- ESR Data Register
  341
- Power Supply and Control
  342
- Supply Watchdog (SWD)
  344
- Monitoring the Voltage Level of a Core Domain
  350
- Controlling the Voltage Level of a Core Domain
  357
- Handling the Power System
  369
- Power State Controller (PSC)
  371
- Operating a Power Transfer
  374
- Power Control Registers
  375
- Global State Controller (GSC)
  411
- GSC Control Flow
  411
- GSC Registers
  415
- Software Boot Support
  421
- Start-Up Registers
  421
- External Request Unit (ERU)
  422
- Introduction
  422
- ERU Pin Connections
  424
- External Request Select Unit (Ersx)
  428
- Event Trigger Logic (Etlx)
  429
- Connecting Matrix
  431
- Output Gating Unit (Oguy)
  432
- ERU Output Connections
  436
- ERU Registers
  438
- SCU Interrupt Generation
  445
- Interrupt Support
  445
- SCU Interrupt Sources
  446
- Interrupt Control Registers
  447
- Temperature Compensation Unit
  466
- Temperature Compensation Registers
  468
- Watchdog Timer (WDT)
  470
- Introduction
  470
- Overview
  470
- Functional Description
  471
- WDT Kernel Registers
  475
- SCU Trap Generation
  479
- Trap Support
  479
- SCU Trap Sources
  480
- SCU Trap Control Registers
  481
- Memory Content Protection
  491
- Parity Error Handling
  491
- Register Control
  500
- Register Access Control
  500
- Register Protection Registers
  503
- Miscellaneous System Registers
  505
- System Registers
  505
- Identification Block
  506
- Marker Memory
  511
- SCU Register Addresses
  512
- Implementation
  520
- Clock Generation Unit
  520
- Esr
  521
7 Parallel Ports

523
- General Description
  524
- Basic Port Operation
  524
- Input Stage Control
  527
- Output Driver Control
  527
- Port Register Description
  528
- Pad Driver Control
  528
- Port Output Register
  531
- Port Output Modification Register
  532
- Port Input Register
  534
- Port Input/Output Control Registers
  535
  - Port 0
    535
  - Port 1
    535
  - Port 2
    535
  - Port 3
    535
  - Port 4
    535
  - Port 6
    535
  - Port 7
    535
  - Port 8
    535
  - Port 9
    535
- Port 15
  540
- Pin Description
  555
8 Dedicated Pins

582
9 The External Bus Controller EBC

585
- External Bus Signals
  587
- Timing Principles
  588
- Basic Bus Cycle Protocols
  588
- Bus Cycle Phases
  591
- Bus Cycle Examples: Fastest Access Cycles
  593
- Functional Description
  595
- Configuration Register Overview
  595
- The EBC Mode Register 0
  598
- The EBC Mode Register 1
  598
- The Timing Configuration Registers Tconcsx
  601
- The Function Configuration Registers Fconcsx
  604
- The Address Window Selection Registers Addrselx
  607
- Ready Controlled Bus Cycles
  610
- External Bus Arbitration
  612
- Shutdown Control
  616
- Lxbus Access Control and Signal Generation
  617
10 Startup Configuration and Bootstrap Loading

618
- Start-Up Mode Selection
  618
- Device Status after Start-Up
  619
- Registers Modified by the Start-Up Procedure
  619
- System Frequency
  621
- Watchdog Timer Handling
  621
- Start-Up Error State
  622
- Special Start-Up Features
  623
- Supplementary Start-Up Information From/To the User
  623
- Support for Power-Saving Modes
  625
- Preparing to Activate Parity
  625
- Internal Start
  628
- External Start
  628
- Specific Settings
  630
- Bootstrap Loading
  631
- General Functionality
  631
- Bootstrap Loaders Using UART Protocol
  633
- Synchronous Serial Channel Bootstrap Loader
  640
- CAN Bootstrap Loader
  643
- Summary of Bootstrap Loader Modes
  646
11 Debug System

647
- Debug Interface
  648
- Routing of Debug Signals
  649
- OCDS Module
  651
- Debug Events
  652
- Debug Actions
  654
- Cerberus
  655
- Functional Overview
  655
- Boundary-Scan
  657
12 Instruction Set Summary

658
13 Device Specification

664

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