Infineon Technologies XC2200 User Manual page 174

4.5.2.1 The Context Pointer (CP)
This non-bit-addressable register selects the current global register bank context. It can
be updated via any instruction capable of modifying SFRs.
CP
Context Pointer
15 14 13 12
1 1 1
r r r
Field Bits
cp [11:1]
Note: It is the user's responsibility to ensure that the physical GPR address specified via
CP register plus short GPR address is always an internal DPRAM location. If this
condition is not met, unexpected results may occur. Do not set CP below the
internal DPRAM start address. Do not set CP above FDE0
phase will overwrite SFRs (beginning at FE00
The XC2200 switches the complete memory-mapped GPR bank with a single
instruction. After switching, the service routine executes within its own separate context.
The instruction "SCXT CP, #New_Bank" pushes the value of the current context pointer
(CP) into the system stack and loads CP with the immediate value "New_Bank", which
selects a new register bank. The service routine may now use its "own registers". This
memory register bank is preserved when the service routine terminates, i.e. its contents
are available on the next call.
Before returning from the service routine (RETI), the previous CP is simply popped from
the system stack which returns the registers to the original bank.
Note: Due to the internal instruction pipeline, a write operation to the CP register stalls
the instruction flow until the register file context switch is really executed. The
instruction immediately following the instruction that updates CP register can use
the new value of the changed CP.
User's Manual
CPUSV2_X, V2.2
SFR (FE10
11 10 9
1
r
Type Description
rw Modifiable Portion of Register CP
Specifies the (word) base address of the current
global (memory-mapped) register bank.
When writing a value to register CP with bits CP[11:9]
= 000
System Units (Vol. 1 of 2)
Central Processing Unit (CPU)
/08 )
H H
8 7 6 5
cp
rw
, bits CP[11:10] are set to 11
B
).
H
4-36
XC2200 Derivatives
Reset Value: FC00
4 3 2 1
by hardware.
B
, otherwise the store
H
V2.1, 2008-08
H
0
0
r