Infineon Technologies XC2200 User Manual page 165

CPUCON2
CPU Control Register 2
15 14 13 12
FIFODEPTH
rw
Field Bits
FIFODEPTH [15:12] rw
FIFOFED [11:10] rw
BYPPF 9
BYPF 8
EIOIAEN 7
STEN 6
LFIC 5
User's Manual
CPUSV2_X, V2.2
SFR (FE1A
11 10 9 8
BYP BYP
FIFOFED
PF F
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Type Description
FIFO Depth Configuration
0000 No FIFO (entries)
0001 One FIFO entry
... ...
1000 Eight FIFO entries
1001 reserved
... ...
1111 reserved
FIFO Fed Configuration
00 FIFO disabled
01 FIFO filled with up to one instruction per cycle
10 FIFO filled with up to two instructions per cycle
11 FIFO filled with up to three instruction per cycle
rw Prefetch Bypass Control
0 Bypass path from prefetch to decode disabled
1 Bypass path from prefetch to decode available
rw Fetch Bypass Control
0 Bypass path from fetch to decode disabled
1 Bypass path from fetch to decode available
rw Early IO Injection Acknowledge Enable
0 Injection acknowledge by destructive read not
guaranteed
1 Injection acknowledge by destructive read
guaranteed
rw Stall Instruction Enable (for debug purposes)
0 Stall Instruction disabled
1 Stall Instruction enabled (see example below)
rw Linear Follower Instruction Cache
0 Linear Follower Instruction Cache disabled
1 Linear Follower Instruction Cache enabled
System Units (Vol. 1 of 2)
Central Processing Unit (CPU)
/0D )
H H
7 6 5
EIO STE
LFIC
IAEN N
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4-27
XC2200 Derivatives
Reset Value: 8FBB
4 3 2 1
OV RET
- DAID SL
RUN ST
rw rw - rw
V2.1, 2008-08
H
0
rw