Infineon Technologies XC2200 User Manual page 156

The CoXXX instructions are the only instructions able to read two memory operands per
cycle. A conflict between the two read and one pending write access can occur if all three
operands are located in the DPRAM area. This is especially important for performance
in the case of executing a filter routine. One of the operands should be located in the
DSRAM to guarantee a single-cycle execution of the CoXXX instructions.
Conflict_DPRAM_Bandwidth:
I ADD op1,R1
n
I ADD R6,R0
n+1
I CoMAC [IDX0],[R0]
n+2
I MOV R3,[R0]
n+3
I ...
n+4
Table 4-9 Pipeline Dependencies in Case of Memory Conflicts (DPRAM)
Stage T
n
DECODE I = ADD
n
op1, R1
ADDRESS I
n-1
MEMORY I
n-2
EXECUTE I
n-3
WR.BACK I
n-4
1) COMAC instruction stalls due to memory bandwidth conflict.
User's Manual
CPUSV2_X, V2.2
T T
n+1 n+2
I = ADD I =
n+1 n+2
R6, R0 CoMAC ...
I = ADD I = ADD
n n+1
op1, R1 R6, R0
I I = ADD
n-1 n
op1, R1
I I
n-2 n-1
I I
n-3 n-2
4-18
XC2200 Derivatives
System Units (Vol. 1 of 2)
Central Processing Unit (CPU)
1)
T T
n+3 n+4
I = MOV I
n+3 n+4
R3, [R0]
I = I = MOV
n+2 n+3
CoMAC ... R3, [R0]
I = ADD I =
n+1 n+2
R6, R0 CoMAC ...
I = ADD I = ADD
n n+1
op1, R1 R6, R0
I I = ADD
n-1 n
op1, R1
T
n+5
I
n+4
I = MOV
n+3
R3, [R0]
I =
n+2
CoMAC ...
–
I = ADD
n+1
R6, R0
V2.1, 2008-08