Infineon Technologies XC161 User Manual

16-bit single-chip microcontroller with c166sv2 core

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U s er ' s Ma n u a l , V 2 . 2, J a n . 20 0 4

XC161

1 6 - B i t S i n g l e - C h i p M i c r o c o n t r o l l er

w i t h C 1 6 6 S V 2 C o r e

V ol u m e 2 (o f 2) : P e ri p he ra l U ni t s

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Page 1 U s er ’ s Ma n u a l , V 2 . 2, J a n . 20 0 4 XC161 1 6 - B i t S i n g l e - C h i p M i c r o c o n t r o l l er...
Page 2 Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life.
Page 3 U s er ’ s Ma n u a l , V 2 . 2, J a n . 20 0 4 XC161 1 6 - B i t S i n g l e - C h i p M i c r o c o n t r o l l er...
Page 4 XC161 Volume 2 (of 2): Peripheral Units Revision History: V2.2, 2004-01 Previous Version: V2.2, 2003-09 (Pre-release) V2.1, 2003-06 V2.0, 2003-03 V1.1, 2002-02 (Draft Manual) V1.0, 2001-04 (Draft Manual) Page Subjects (major changes since version V2.1) 14-1ff Timer block description introduced...
Page 5 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Table of Contents Page This User’s Manual consists of two Volumes, “System Units” and “Peripheral Units”. For your convenience this table of contents (and also the keyword index) lists both volumes, so can immediately find the reference to the desired section in the corresponding document ([1] or [2]).
Page 6 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Table of Contents Page 3.10 Program Memory Control ....... . . 3-37 [1] 3.10.1...
Page 7 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Table of Contents Page Interrupt and Trap Functions ......5-1 [1] Interrupt System Structure .
Page 8 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Table of Contents Page Parallel Ports ......... . . 7-1 [1] Input Threshold Control .
Page 9: Table Of Contents
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Table of Contents Page 9.3.7.3 Combining the READY Function with Predefined Wait States . 9-22 [1] 9.3.8 Access Control to TwinCAN ......9-23 [1] 9.3.9...
Page 10 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Table of Contents Page 14.2.3 GPT2 Auxiliary Timer T5 Control ......14-39 [2] 14.2.4...
Page 11 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Table of Contents Page 17.8 Staggered and Non-Staggered Operation ....17-29 [2] 17.9 CAPCOM Interrupts .
Page 12 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Table of Contents Page 19.2.8 Port Configuration Requirements ......19-17 [2] 19.3...
Page 13 Global CAN Control/Status Registers ..... 21-80 [2] 21.3 XC161 Module Implementation Details ..... . 21-82 [2] 21.3.1 Interfaces of the TwinCAN Module .
Page 14 SDLM Module Register Table ......22-50 [2] 22.6 XC161 Module Implementation Details ..... . 22-51 [2] 22.6.1 Interfaces of the SDLM Module .
Page 15: The General Purpose Timer Units
XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units The General Purpose Timer Units The General Purpose Timer Unit blocks GPT1 and GPT2 have very flexible multifunctional timer structures which may be used for timing, event counting, pulse width measurement, pulse generation, frequency multiplication, and other purposes.
Page 16: Timer Block Gpt1
XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units 14.1 Timer Block GPT1 From a programmer’s point of view, the GPT1 block is composed of a set of SFRs as summarized below. Those portions of port and direction registers which are used for alternate functions by the GPT1 block are shaded.
Page 17 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units The interrupts of GPT1 are controlled through the Interrupt Control Registers TxIC. These registers are not part of the GPT1 block. The input and output lines of GPT1 are connected to pins of ports P3 and P5.
Page 18: Gpt1 Core Timer T3 Control
XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units 14.1.1 GPT1 Core Timer T3 Control The current contents of the core timer T3 are reflected by its count register T3. This register can also be written to by the CPU, for example, to set the initial start value.
Page 19 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Field Bits Description T3OE Overflow/Underflow Output Enable Alternate Output Function Disabled State of T3 toggle latch is output on pin T3OUT T3UDE Timer T3 External Up/Down Enable...
Page 20 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Timer T3 Run Control The core timer T3 can be started or stopped by software through bit T3R (Timer T3 Run Bit). This bit is relevant in all operating modes of T3. Setting bit T3R will start the timer, clearing bit T3R stops the timer.
Page 21 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Timer 3 Output Toggle Latch The overflow/underflow signal of timer T3 is connected to a block named ‘Toggle Latch’, shown in the timer mode diagrams. Figure 14-3 illustrates the details of this block.
Page 22: Gpt1 Core Timer T3 Operating Modes
XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units 14.1.2 GPT1 Core Timer T3 Operating Modes Timer 3 in Timer Mode Timer mode for the core timer T3 is selected by setting bitfield T3M in register T3CON to 000 .
Page 23 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Gated Timer Mode Gated timer mode for the core timer T3 is selected by setting bitfield T3M in register T3CON to 010 or 011 . Bit T3M.0 (T3CON.3) selects the active level of the gate input.
Page 24 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Counter Mode Counter Mode for the core timer T3 is selected by setting bitfield T3M in register T3CON to 001 . In counter mode, timer T3 is clocked by a transition at the external input pin T3IN.
Page 25 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Incremental Interface Mode Incremental interface mode for the core timer T3 is selected by setting bitfield T3M in register T3CON to 110 or 111 . In incremental interface mode, the two inputs associated with core timer T3 (T3IN, T3EUD) are used to interface to an incremental encoder.
Page 26 1 X X Reserved. Do not use this combination. The incremental encoder can be connected directly to the XC161 without external interface logic. In a standard system, however, comparators will be employed to convert the encoder’s differential outputs (such as A, A) to digital signals (such as A). This greatly increases noise immunity.
Page 27 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units As in incremental interface mode two input signals with a 90 ° phase shift are evaluated, their maximum input frequency can be half the maximum count frequency.
Page 28 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Forward Jitter Backward Jitter Forward T3IN T3EUD Contents of T3 Down Note: This example shows the timer behaviour assuming that T3 counts upon any transition on input T3IN, i.e. T3I = '001...
Page 29: Gpt1 Auxiliary Timers T2/T4 Control
XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units 14.1.3 GPT1 Auxiliary Timers T2/T4 Control Auxiliary timers T2 and T4 have exactly the same functionality. They can be configured for timer mode, gated timer mode, counter mode, or incremental interface mode with the same options for the timer frequencies and the count signal as the core timer T3.
Page 30 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Field Bits Description TxCHDIR Timer Tx Count Direction Change This bit is set each time the count direction of timer Tx changes. TxCHDIR must be cleared by SW.
Page 31 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Field Bits Description [2:0] Timer Tx Input Parameter Selection Depends on the operating mode, see respective sections for encoding: Table 14-7 for Timer Mode and Gated Timer Mode...
Page 32: Gpt1 Auxiliary Timers T2/T4 Operating Modes
XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units 14.1.4 GPT1 Auxiliary Timers T2/T4 Operating Modes The operation of the auxiliary timers in the basic operating modes is almost identical with the core timer’s operation, with very few exceptions. Additionally, some combined operating modes can be selected.
Page 33 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Timers T2 and T4 in Gated Timer Mode Gated timer mode for an auxiliary timer Tx is selected by setting bitfield TxM in register TxCON to 010 or 011 .
Page 34 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Timers T2 and T4 in Counter Mode Counter mode for an auxiliary timer Tx is selected by setting bitfield TxM in register TxCON to 001 . In counter mode, an auxiliary timer can be clocked either by a transition at its external input line TxIN, or by a transition of timer T3’s toggle latch T3OTL.
Page 35 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units For counter operation, pin TxIN must be configured as input (the respective direction control bit DPx.y must be 0). The maximum input frequency allowed in counter mode depends on the selected prescaler value.
Page 36 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Timer Concatenation Using the toggle bit T3OTL as a clock source for an auxiliary timer in counter mode concatenates the core timer T3 with the respective auxiliary timer. This concatenation forms either a 32-bit or a 33-bit timer/counter, depending on which transition of T3OTL is selected to clock the auxiliary timer.
Page 37 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Auxiliary Timer in Reload Mode Reload Mode for an auxiliary timer Tx is selected by setting bitfield TxM in the respective register TxCON to 100 . In reload mode, the core timer T3 is reloaded with the contents of an auxiliary timer register, triggered by one of two different signals.
Page 38 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units • If both a positive and a negative transition of T3OTL are selected to trigger a reload, the core timer will be reloaded with the contents of the auxiliary timer each time it overflows or underflows.
Page 39 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Auxiliary Timer T2 Edge T2IN Reload T2IRQ Select T2I.2 T3IRQ Operating Count Mode Core Timer T3 Toggle Latch T3OUT T3IN Control Up/Down BPS1 Edge T4IN Reload T4IRQ Select T4I.2...
Page 40 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Auxiliary Timer in Capture Mode Capture mode for an auxiliary timer Tx is selected by setting bitfield TxM in the respective register TxCON to 101 . In capture mode, the contents of the core timer T3 are latched into an auxiliary timer register in response to a signal transition at the respective auxiliary timer’s external input pin TxIN.
Page 41: Gpt1 Clock Signal Control
XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units 14.1.5 GPT1 Clock Signal Control All actions within the timer block GPT1 are triggered by transitions of its basic clock. This basic clock is derived from the system clock by a basic block prescaler, controlled by...
Page 42 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Table 14-7 GPT1 Overall Prescaler Factors for Internal Count Clock Individual Common Prescaler for Module Clock Prescaler for Tx BPS1 = 01 BPS1 = 00 BPS1 = 11...
Page 43: Gpt1 Timer Registers
XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units External Count Clock Input The external input signals of the GPT1 block are sampled with the GPT1 basic clock (see Figure 14-2). To ensure that a signal is recognized correctly, its current level (high or low) must be held active for at least one complete sampling period, before changing.
Page 44: Interrupt Control For Gpt1 Timers
XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units 14.1.7 Interrupt Control for GPT1 Timers When a timer overflows from FFFF to 0000 (when counting up), or when it underflows from 0000 to FFFF (when counting down), its interrupt request flag (T2IR, T3IR or T4IR) in register TxIC will be set.
Page 45: Timer Block Gpt2
XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units 14.2 Timer Block GPT2 From a programmer’s point of view, the GPT2 block is represented by a set of SFRs as summarized below. Those portions of port and direction registers which are used for alternate functions by the GPT2 block are shaded.
Page 46 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units space (see Section 14.2.7). When any of the timer registers is written to by the CPU in the state immediately preceding a timer increment, decrement, reload, or capture operation, the CPU write operation has priority in order to guarantee correct results.
Page 47: Gpt2 Core Timer T6 Control
XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units 14.2.1 GPT2 Core Timer T6 Control The current contents of the core timer T6 are reflected by its count register T6. This register can also be written to by the CPU, for example, to set the initial start value.
Page 48 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Field Bits Description Timer T6 Run Bit Timer T6 stops Timer T6 runs [5:3] Timer T6 Mode Control (Basic Operating Mode) 000 Timer Mode 001 Counter Mode...
Page 49 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Timer 6 Output Toggle Latch The overflow/underflow signal of timer T6 is connected to a block named ‘Toggle Latch’, shown in the timer mode diagrams. Figure 14-21 illustrates the details of this block.
Page 50: Gpt2 Core Timer T6 Operating Modes
XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units 14.2.2 GPT2 Core Timer T6 Operating Modes Timer 6 in Timer Mode Timer mode for the core timer T6 is selected by setting bitfield T6M in register T6CON to 000 .
Page 51 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Gated Timer Mode Gated timer mode for the core timer T6 is selected by setting bitfield T6M in register T6CON to 010 or 011 . Bit T6M.0 (T6CON.3) selects the active level of the gate input.
Page 52 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Counter Mode Counter mode for the core timer T6 is selected by setting bitfield T6M in register T6CON to 001 . In counter mode, timer T6 is clocked by a transition at the external input pin T6IN.
Page 53: Gpt2 Auxiliary Timer T5 Control
XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units 14.2.3 GPT2 Auxiliary Timer T5 Control Auxiliary timer T5 can be configured for timer mode, gated timer mode, or counter mode with the same options for the timer frequencies and the count signal as the core timer T6.
Page 54 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Field Bits Description T5CC Timer T5 Capture Correction T5 is just captured without any correction T5 is decremented by 1 before being captured Timer T3 Capture Trigger Enable...
Page 55: Gpt2 Auxiliary Timer T5 Operating Modes
XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units In gated timer mode, the timer will only run if the selected run bit is set and the gate is active (high or low, as programmed). Note: If remote control is selected T6R will start/stop timer T6 and the auxiliary timer T5 synchronously.
Page 56 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Timer T5 in Gated Timer Mode Gated timer mode for the auxiliary timer T5 is selected by setting bitfield T5M in register T5CON to 010 or 011 .
Page 57 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Edge T5IN Count Auxiliary T5IRQ Timer T5 Select Toggle Latch T5I.2 Clear T5RC Up/Down T5UD MCB05408 Figure 14-27 Block Diagram of Auxiliary Timer T5 in Counter Mode...
Page 58 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Timer Concatenation Using the toggle bit T6OTL as a clock source for the auxiliary timer in counter mode concatenates the core timer T6 with the auxiliary timer T5. This concatenation forms either a 32-bit or a 33-bit timer/counter, depending on which transition of T6OTL is selected to clock the auxiliary timer.
Page 59: Gpt2 Register Caprel Operating Modes
XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units 14.2.5 GPT2 Register CAPREL Operating Modes The Capture/Reload register CAPREL can be used to capture the contents of timer T5, or to reload timer T6. A special mode facilitates the use of register CAPREL for both functions at the same time.
Page 60 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Count Auxiliary T5IRQ Clock Timer T5 Clear Up/Down Edge CAPIN T5CLR Select Capture Capture Correction T5CC T3IN Signal T5SC Select CAPREL T3EUD Register CRIRQ Clear T6CLR MCA05410...
Page 61 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units incremental interface mode, in order to derive dynamic information (speed, acceleration) from the input signals. For capture mode operation, the selected pins CAPIN, T3IN, or T3EUD must be configured as input.
Page 62 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units GPT2 Capture/Reload Register CAPREL in Capture-And-Reload Mode Since the reload function and the capture function of register CAPREL can be enabled individually by bits T5SC and T6SR, the two functions can be enabled simultaneously by setting both bits.
Page 63 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units the contents of timer T5 are latched into register CAPREL and timer T5 is cleared (T5CLR = 1). Thus, register CAPREL always contains the correct time between two events, measured in timer T5 increments.
Page 64: Gpt2 Clock Signal Control
XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units 14.2.6 GPT2 Clock Signal Control All actions within the timer block GPT2 are triggered by transitions of its basic clock. This basic clock is derived from the system clock by a basic block prescaler, controlled by...
Page 65 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Table 14-15 GPT2 Overall Prescaler Factors for Internal Count Clock Individual Common Prescaler for Module Clock Prescaler for Tx BPS2 = 01 BPS2 = 00 BPS2 = 11...
Page 66 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units External Count Clock Input The external input signals of the GPT2 block are sampled with the GPT2 basic clock (see Figure 14-20). To ensure that a signal is recognized correctly, its current level (high or low) must be held active for at least one complete sampling period, before changing.
Page 67: Gpt2 Timer Registers
XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units 14.2.7 GPT2 Timer Registers GPT12E_Tx Timer x Count Register SFR (FE4x Reset Value: 0000 Txvalue Table 14-18 GPT1 Timer Register Locations Timer Register Physical Address 8-Bit Address...
Page 68: Interrupt Control For Gpt2 Timers And Caprel
XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units 14.2.8 Interrupt Control for GPT2 Timers and CAPREL When a timer overflows from FFFF to 0000 (when counting up), or when it underflows from 0000 to FFFF (when counting down), its interrupt request flag (T5IR or T6IR) in register TxIC will be set.
Page 69: Interfaces Of The Gpt Module
XC161 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units 14.3 Interfaces of the GPT Module Besides the described intra-module connections, the timer unit blocks GPT1 and GPT2 are connected to their environment in two basic ways (see...
Page 70: Real Time Clock
A number of programming options as well as interrupt request signals adjust the operation of the RTC to the application’s requirements. The RTC can continue its operation while the XC161 is in a power-saving mode, such that real time date and time information is provided.
Page 71: Defining The Rtc Time Base
15-3). The RTC is also supplied with the system clock of the XC161. This clock signal is used to control the RTC’s logic blocks and its bus interface. To synchronize properly to the count clock, the system clock must run at least four times faster than the count clock, ≥...
Page 72 When the system clock frequency becomes lower than 4 × proper synchronization is not possible and count events may be missed. When the XC161 enters e.g. sleep mode the system clock stops completely and the RTC would stop counting. In these cases the RTC can be switched to Asynchronous Mode (by setting bit RTCCM in register SYSCON0).
Page 73 Real Time Clock Increased RTC Accuracy through Software Correction The accuracy of the XC161’s RTC is determined by the oscillator frequency and by the respective prescaling factor (excluding or including T14 and the 8:1 prescaler). The accuracy limit generated by the prescaler is due to the quantization of a binary counter...
Page 74: Rtc Run Control
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Real Time Clock 15.2 RTC Run Control If the RTC shall operate bit RUN in register RTC_CON must be set (default after reset). Bit RUN can be cleared, for example, to exclude certain operation phases from time keeping.
Page 75 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Real Time Clock Field Bits Type Description RTC Input Source Prescaler Enable Prescaler disabled, T14 clocked with Prescaler enabled, T14 clocked with RTC Run Bit RTC stopped RTC runs User’s Manual 15-6 V2.2, 2004-01...
Page 76: Rtc Operating Modes
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Real Time Clock 15.3 RTC Operating Modes The RTC can be configured for several operating modes according to the purpose it is meant to serve. These operating modes are configured by selecting appropriate reload values and interrupt signals.
Page 77 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Real Time Clock Timer T14 and its reload register are accessed via dedicated locations. The four RTC counters CNT3 … CNT0 are accessed via the two 16-bit RTC timer registers, RTCH and RTCL.
Page 78 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Real Time Clock RTC_RELH RTC Reload High Register ESFR (F0CE Reset Value: 0000 REL3 REL2 RTC_RELL RTC Reload Low Register ESFR (F0CC Reset Value: 0000 REL1 REL0 Field Bits Type Description RELx...
Page 79: 48-Bit Timer Operation
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Real Time Clock 15.3.1 48-bit Timer Operation The concatenation of timers T14 and COUNT0 … COUNT3 can be regarded as a 48-bit timer which is clocked with the RTC input frequency, optionally divided by the prescaler.
Page 80: Cyclic Interrupt Generation
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Real Time Clock <timer_width> Each timer in the chain divides the clock by (2 - <reload_value>) : 1, as the timers count up. Table 15-3 shows the reload values which must be chosen for a specific scenario (i.e.
Page 81: Rtc Interrupt Generation
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Real Time Clock 15.4 RTC Interrupt Generation The overflow signals of each timer of the RTC timer chain can generate an interrupt request. The RTC’s interrupt subnode control register ISNC combines these requests to activate the common RTC interrupt request line RTC_IRQ.
Page 82 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Real Time Clock RTC_ISNC Interrupt Subnode Ctrl. Reg. ESFR (F10C Reset Value: 0000 Field Bits Type Description CNTxIR 9, 7, 5, Section CNTx Interrupt Request Flag (x = 3 … 0) No request pending...
Page 83: The Analog/Digital Converter
The Analog/Digital Converter The Analog/Digital Converter The XC161 provides an Analog/Digital Converter with 8-bit or 10-bit resolution and a sample & hold circuit on-chip. An input multiplexer selects between up to 12 analog input channels (alternate functions of Port 5) either via software (fixed channel modes) or automatically (auto scan modes).
Page 84 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter The external analog reference voltages are fixed. The separate supply AREF AGND for the ADC reduces the interference with other digital signals. The reference voltages must be stable during the reset calibration phase and during an entire conversion, to achieve a maximum of accuracy.
Page 85: Mode Selection
XC161 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter 16.1 Mode Selection The analog input channels AN15 … AN12, AN7 … AN0 are alternate functions of Port 5 which is an input-only port. The Port 5 lines may either be used as analog or digital inputs.
Page 86 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter Field Bits Type Function ADWR ADC Wait for Read Control ADBSY ADC Busy Flag ADC is idle A conversion is active ADST ADC Start Bit Stop a running conversion...
Page 87: Enhanced Mode
XC161 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter Field Bits Type Description Conversion Resolution Control 10-bit resolution (default after reset) 8-bit resolution ADCTC [11:6] ADC Conversion Time Control Defines the ADC basic conversion clock: / (<ADCTC> + 1)
Page 88 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter Field Bits Type Description ADCTS [13:12] rw Channel Injection Trigger Input Select Channel injection trigger input disabled Trigger input CAPCOM selected Reserved Reserved Note: Reset value of bitfield ADCTS is 01 compatibility purposes.
Page 89 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter ADC_CTR2 ADC Control Register 2 ESFR (F09C Reset Value: 0000 ADCTC ADSTC ADC_CTR2IN Injection Control Register 2 ESFR (F09E Reset Value: 0000 ADCTC ADSTC Field Bits Type Description [13:12] rw...
Page 90: Adc Operation
XC161 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter 16.2 ADC Operation Channel Selection, ADCH Bitfield ADCH controls the input channel multiplexer logic. In the Single Channel Modes, it specifies the analog input channel which is to be converted. In the Auto Scan Modes, it specifies the highest channel number to be converted in the auto scan round.
Page 91 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter • In Auto Scan Single Conversion mode, the ADC continues the auto scan round until the conversion of channel 0 is finished, then it stops. There is no difference to the operation if ADST was not cleared by software.
Page 92 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter Conversion Result The result of a conversion is stored in the result register ADC_DAT, or in register ADC_DAT2 for an injected conversion. The position of the result depends on the basic operating mode (compatibility or enhanced) and on the selected resolution (8-bit or 10-bit).
Page 93: Fixed Channel Conversion Modes
XC161 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter 16.2.1 Fixed Channel Conversion Modes These modes are selected by programming the mode selection bitfield ADM to 00 (single conversion) or to 01 (continuous conversion). After starting the converter through bit ADST the busy flag ADBSY will be set and the channel specified in bitfield ADCH will be converted.
Page 94: Auto Scan Conversion Modes
XC161 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter 16.2.2 Auto Scan Conversion Modes These modes are selected by programming the mode selection field ADM to 10 (single conversion) or to 11 (continuous conversion). Auto Scan modes automatically convert a sequence of analog channels, beginning with the channel specified in bitfield ADCH and ending with channel 0, without requiring software to change the channel number.
Page 95: Wait For Read Mode
XC161 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter 16.2.3 Wait for Read Mode If in default mode of the ADC a previous conversion result has not been read out of the result register by the time a new conversion is complete, the previous result is lost because it is overwritten by the new value, and the A/D overrun error interrupt request flag ADEIR will be set.
Page 96: Channel Injection Mode
XC161 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter 16.2.4 Channel Injection Mode Channel Injection Mode allows the conversion of a specific analog channel (also while the ADC is running in a continuous or auto scan mode) without changing the current operating mode.
Page 97 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter A channel injection can be triggered in two ways: • setting of the Channel Injection Request bit ADCRQ via software • a compare or a capture event of Capture/Compare register CC31 of the CAPCOM2 unit, which also sets bit ADCRQ.
Page 98 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter Arbitration of Conversions Conversion requests that are activated while the ADC is idle immediately trigger the respective conversion. If a conversion is requested while another conversion is currently in progress the operation of the A/D converter depends on the kind of the involved conversions (standard or injected).
Page 99: Automatic Calibration
The Analog/Digital Converter 16.3 Automatic Calibration The ADC of the XC161 features automatic self-calibration. This calibration corrects gain errors, which are mainly due to process variation, and offset errors, which are mainly due to temperature changes. Two types of calibration are supported: •...
Page 100: Conversion Timing Control
The time that the two different actions during conversion take (sampling, and converting) can be programmed within a certain range in the XC161 relative to the CPU clock. The absolute time that is consumed by the different conversion steps therefore is independent from the general speed of the controller.
Page 101 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter Standard Timing Control Standard timing control is performed by using two 2-bit fields in register ADC_CON. Bitfield ADCTC (conversion time control) selects the basic conversion clock ( ), used for the operation of the A/D converter.
Page 102 XC161 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter Total Conversion Time Examples The time for a complete conversion includes the sample time , the conversion itself (successive approximation and calibration), and the time required to transfer the digital value to the result register as shown in the example below (standard conversion timing).
Page 103: A/D Converter Interrupt Control
XC161 Derivatives Peripheral Units (Vol. 2 of 2) The Analog/Digital Converter 16.5 A/D Converter Interrupt Control At the end of each conversion, interrupt request flag ADCIR in interrupt control register ADC_CIC is set. This end-of-conversion interrupt request may cause an interrupt to vector ADCINT, or it may trigger a PEC data transfer which reads the conversion result from register ADC_DAT, e.g.
Page 104: Interfaces Of The Adc Module
The 2 interrupt request lines of the ADC are connected to the interrupt control block. External Connections The analog input signals for the ADC are connected with Port 5 of the XC161 (input only). Two dedicated pins ( ) provide the analog reference voltage for the...
Page 105: Capture/Compare Units
Capture/Compare Units Capture/Compare Units The XC161 provides two, almost identical, Capture/Compare (CAPCOM) units, which only differ in the way they are connected to the pins. Each CAPCOM unit provides 16 capture/compare channels, which interact with 2 timers. A CAPCOM channel can capture the contents of a timer on specific internal or external events, or it can compare a timer’s contents with given values, and modify output signals in case of a match.
Page 106 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units With this mechanism, each CAPCOM unit supports generation and control of timing sequences on up to 16 channels with a minimum of software intervention. From the programmer’s point of view, the term ‘CAPCOM unit’ refers to a set of registers...
Page 107 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units Reload Reg. T0REL/T7REL T0/T7 T0IRQ, T0IN/T7IN Input Timer T0/T7 T7IRQ Control T6OUF CCxIO CCxIRQ CCxIO CCxIRQ Mode Sixteen Control 16-bit (Capture Capture/ Compare Compare) Registers CCxIO CCxIRQ T1/T8 T1IRQ, Input...
Page 108: The Capcom Timers
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units 17.1 The CAPCOM Timers The primary use of the timers T0/T7 and T1/T8 is to provide two independent time bases for the capture/compare channels of each unit. The maximum resolution is 8 staggered mode, and 1 in non-staggered mode.
Page 109 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units CC1_T01CON Timer 0/1 Control Register SFR (FF50 Reset Value: 0000 CC2_T78CON Timer 7/8 Control Register SFR (FF20 Reset Value: 0000 Field Bits Type Description 14, 6 Timer/Counter Tx Run Control...
Page 110 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units Timer Mode In Timer Mode (TxM = 0), the input clock for a CAPCOM timer is derived from divided by a programmable prescaler. Each timer has its own individual prescaler, controlled through the individual bitfields TxI in the timer control registers T01CON and T78CON.
Page 111 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units Table 17-1 Timer Tx Input Clock Selection for Timer Mode, = 40 MHz Prescaler Input Resolution Period Frequency Non-Staggered Mode 5 MHz 200 ns 13.11 ms 2.5 MHz 400 ns 26.21 ms...
Page 112 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units Counter Mode In Counter Mode (TxM = 1), the input clock of a CAPCOM timer is either derived from an associated external input pin, T0IN/T7IN, or from the over-/underflows of GPT timer T6.
Page 113: Capcom Timer Interrupts
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units 17.2 CAPCOM Timer Interrupts Upon a timer overflow the corresponding timer interrupt request flag TxIR for the respective timer will be set. This flag can be used to generate an interrupt or trigger a PEC service request, when enabled by the respective interrupt enable bit TxIE.
Page 114: Capture/Compare Channels
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units 17.3 Capture/Compare Channels The 16-bit capture/compare registers CC0 through CC15 (CC16 through CC31) are used as data registers for capture or compare operations with respect to timers T0/T7 and T1/T8. The capture/compare registers are not bit-addressable.
Page 115 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units Capture/Compare Registers for the CAPCOM2 Unit (CC31 … CC16) CC2_M4 CAPCOM Mode Ctrl. Reg. 4 SFR (FF22 Reset Value: 0000 MOD19 MOD18 MOD17 MOD16 CC2_M5 CAPCOM Mode Ctrl. Reg. 5...
Page 116 Note: A capture or compare event on channel 31 may be used to trigger a channel injection on the XC161’s A/D converter if enabled. User’s Manual 17-12 V2.2, 2004-01...
Page 117: Capture Mode Operation
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units 17.4 Capture Mode Operation In Capture Mode, the current contents of a CAPCOM timer are latched (captured) into the respective capture/compare register in response to an external event. This is used, for example, to record the time at which an external event has occurred, or to measure the distance between two external events in timer increments.
Page 118: Compare Mode Operation
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units 17.5 Compare Mode Operation The compare modes allow triggering of events (interrupts and/or output signal transitions) or generation of pulse trains with minimum software overhead. In all compare modes, the 16-bit value stored in a capture/compare register CCy (in the following also referred to as ‘compare value’) is continuously compared with the contents of the...
Page 119: Compare Mode 0
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units 17.5.1 Compare Mode 0 This is an interrupt-only mode which can be used for software timing purposes. In this mode, the interrupt request line CCyIRQ is activated each time a match is detected between the contents of the compare register CCy and the allocated timer.
Page 120 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units T1IRQ, Timer T0/T7 Timer T1/T8 T8IRQ T0IRQ, T7IRQ ACCy Mode 1 only! Mode & to Port Output Ctrl. Logic Mode Comparator MODy CCyIRQ Control SEEy SEMy Compare Register CCy MCB05421 Figure 17-5 Compare Mode 0 and 1 Block Diagram Note: The signal remains unaffected in compare mode 0.
Page 121 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units Timer Contents FFFF FFFF FFFE FFFE FFFD FFFD FFFC FFFC FFFB FFFB FFFA FFFA FFF9 FFF9 Reload Value = FFF9 CCxIO Case 1 CC0 = FFFF CCxIO Case 2 CC0 = FFFA...
Page 122: Compare Mode 2
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units 17.5.3 Compare Mode 2 Compare mode 2 is an interrupt-only mode similar to compare mode 0. The main difference is that only one compare match, corresponding to one interrupt request, is possible within a given timer period.
Page 123 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units T1IRQ, Timer T0/T7 Timer T1/T8 T8IRQ T0IRQ, T7IRQ ACCy ACCy Mode 3 only! Mode & to Port Output Ctrl. Logic Mode Comparator MODy CCyIRQ Control SEEy SEMy Compare Register CCy...
Page 124 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units detected at FFFF . One can see, that this operation is ideal for PWM generation, as software can write a new compare value regardless of whether this value is higher or lower than the current timer contents.
Page 125 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units wrote to the register, a match would have been detected and the reprogramming would go into effect during the next timer period. The examples in Figure 17-9 show special cases for compare modes 2 and 3. Case 1 illustrates the effect when the compare value is equal to the reload value of the timer.
Page 126: Double-Register Compare Mode
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units Case 5 shows an option to get around this problem. Here, the compare register is reloaded with FFF8 , a value which is lower than the timer reload value. Thus, the timer will never reach this value, and no compare match will be detected.
Page 127 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units for mode 1 (with port influence), while the bank2 register must be programmed for mode 0 (interrupt-only). Double-register compare mode can be controlled (this means, enabled or disabled) for each register pair via the associated control bitfield DRxM in register CC1_DRM or CC2_DRM, respectively.
Page 128 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units Timer T0/T7 Timer T1/T8 ACCy ACCz DRyM Mode Comp. CCyIRQ Control MODy Mode & to Port SEEy SEMy Output Ctrl. Logic DRyM Mode Comparator CCzIRQ Control MODz SEEz SEMz Compare...
Page 129: Compare Output Signal Generation
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units 17.6 Compare Output Signal Generation This section discusses the interaction between the CAPCOM Unit and the Port Logic. The block diagram illustrated in Figure 17-11 details the logic of the block “Mode &...
Page 130 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units STAG >1 & Compare Match TxOV Port Latch Port Pin Output Driver Pm.n Value Control OUT Latch Direction ALTSEL0Pn MODy CAPCOM Logic Port Logic MCB05427 Figure 17-11 Port Output Block Diagram for Compare Modes Note: A compare output signal is visible at the pin only in compare modes 1 or 3.
Page 131: Single Event Operation
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units 17.7 Single Event Operation If an application requires that one and only one compare event needs to take place (within a certain time frame), single event operation helps to reduce software overhead and to eliminate the need for fast reaction upon events.
Page 132 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units CC1_SEE Single Event Enable Reg. SFR (FE2E Reset Value: 0000 CC2_SEE Single Event Enable Reg. SFR (FE2A Reset Value: 0000 Field Bits Type Description SEEy 15 … 0 Single Event Enable Control...
Page 133: Staggered And Non-Staggered Operation
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units 17.8 Staggered and Non-Staggered Operation The CAPCOM units can run in one of two basic operation modes: Staggered Mode and Non-Staggered Mode. The selection between these modes is performed via register IOC.
Page 134 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units in the same clock cycle. This mode offers a faster operation and increased resolution of the CAPCOM unit, 8 times higher than in staggered mode. Staggered Mode Figure 17-12 illustrates the staggered mode operation. In this example, all CCy registers are programmed for compare mode 3.
Page 135 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units Timer increments to FFFF Timer increments to Timer Timer overflow FFFE contents = FFFD Timer is reloaded with FFFC 1 CAPCOM Cycle 1 CAPCOM Cycle Clock Cycles Clock Cycles CC0 = FFFE...
Page 136 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units Non-Staggered Mode To gain maximum speed and resolution with the CAPCOM unit, it can be switched to non-staggered mode. In this mode, one CAPCOM operation cycle is equal to one module clock cycle.
Page 137 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units Timer increments to FFFF Timer increments to Timer Timer overflow FFFE contents = FFFD Timer is reloaded with FFFC 1 CAPCOM Cycle 1 CAPCOM Cycle Clock Cycle Clock Cycle CC0 = FFFE...
Page 138: Capcom Interrupts
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units 17.9 CAPCOM Interrupts Upon a capture or compare event, the interrupt request flag CCxIR for the respective capture/compare register CCx is automatically set. This flag can be used to generate an interrupt or trigger a PEC service request when enabled by the interrupt enable bit CCxIE.
Page 139 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units Table 17-4 CAPCOM Unit Interrupt Control Register Addresses CAPCOM1 Unit CAPCOM2 Unit Register Name Address Reg. Register Name Address Reg. Space Space CC1_CC0IC FF78 CC2_CC16IC F160 ESFR CC1_CC1IC FF7A CC2_CC17IC...
Page 140: External Input Signal Requirements
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units 17.10 External Input Signal Requirements The external input signals of a CAPCOM unit are sampled by the CAPCOM logic based on the module clock and the basic operation mode (staggered or non-staggered mode).
Page 141: Interfaces Of The Capcom Units
External Connections The capture/compare signals of both CAPCOM units are connected with input/output ports of the XC161. Depending on the selected direction, these ports may provide capture trigger signals from the external system or issue compare output signals to external circuitry.
Page 142 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units CC0IO P6.0/CC0IO System Control CC1IO CC1DIS P6.1/CC1IO Unit (SCU) CC2IO P6.2/CC2IO T6OUF CC3IO GPT12 P6.3/CC3IO Unit Port P6 CC4IO Control P6.4/CC4IO T0IRQ CC5IO P6.5/CC5IO T1IRQ CC6IO P6.6/CC6IO CC0IRQ CC7IO CC1IRQ P6.7/CC7IO...
Page 143 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Capture/Compare Units CC16IO P9.0/CC16IO System Control CC17IO CC2DIS P9.1/CC17IO Unit (SCU) CC18IO P9.2/CC18IO Port P9 T6OUF CC19IO GPT12 Control P9.3/CC19IO Unit CC20IO P9.4/CC20IO T7IRQ CC21IO P9.5/CC21IO T8IRQ CC16IRQ CC22IO P1L.7/CC22IO CC17IRQ CC23IO P1H.0/CC23IO...
Page 144: Asynchronous/Synchronous Serial Interface (Asc)
Asynchronous/Synchronous Serial Interface (ASC) Asynchronous/Synchronous Serial Interface (ASC) The XC161 contains two Asynchronous/Synchronous Serial Interfaces, ASC0 and ASC1. The following sections present the general features and operations of such an ASC module. The final section describes the actual implementation of the two ASC modules including their interconnections with other on-chip modules.
Page 145 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Bus Interface Module Product Interface Clock ASCxDIS Control Address Decoder Port Module Control (Kernel) TBIR Interrupt Control ABSTIR ABDETIR MCA05432 Figure 18-1 ASC Interface Diagram User’s Manual 18-2 V2.2, 2004-01...
Page 146: Operational Overview
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 18.1 Operational Overview Figure 18-2 shows a block diagram of the ASC with its operating modes (Asynchronous and Synchronous Mode). Asynchronous Mode Prescaler / Baudrate Fractional Timer Divider...
Page 147 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Testing is supported by a loop-back option. A 13-bit baudrate timer with a versatile input clock divider circuitry provides the serial clock signal. In a Special Asynchronous Mode, the ASC supports IrDA data transmission up to 115.2 kbit/s with fixed or programmable...
Page 148: Asynchronous Operation
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 18.2 Asynchronous Operation Asynchronous Mode supports full-duplex communication in which both transmitter and receiver use the same data frame format and the same baudrate. Data is transmitted on line TxD and received on line RxD.
Page 149: Asynchronous Data Frames
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 18.2.1 Asynchronous Data Frames 8-Bit Data Frames 8-bit data frames consist of either eight data bits D7 … D0 (M = 001 ), or seven data bits D6 … D0 plus an automatically generated parity bit (M = 011 ).
Page 150 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 9-Bit Data Frames 9-bit data frames consist of either nine data bits D8 … D0 (M = 100 ), eight data bits D7 … D0 plus an automatically generated parity bit (M = 111 ), or eight data bits D7 …...
Page 151 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) IrDA Frames The modulation schemes of IrDA are based on standard asynchronous data transmission frames. The asynchronous data format in IrDA Mode (M = 010 ) is defined...
Page 152: Asynchronous Transmission
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 18.2.2 Asynchronous Transmission Asynchronous transmission begins at the next overflow of the divide-by-16 baudrate timer (transition of the baudrate clock ), if bit R is set and data has been loaded into TBUF.
Page 153 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) TXFCON.TXFITL = 0011 Byte 7 Byte 6 Byte 7 Byte 7 Byte 6 Byte 5 Byte 5 Byte 6 Byte 6 Byte 6 Byte 6 Byte 4 Byte 4...
Page 154 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) If the TXFIFO is full and additional bytes are written into TBUF, the error interrupt will be generated with bit OE set. In this case, the data byte that was last written into the transmit FIFO is overwritten and the transmit FIFO filling level TXFFL is set to maximum.
Page 155: Asynchronous Reception
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 18.2.4 Asynchronous Reception Asynchronous reception is initiated by a falling edge (1-to-0 transition) on line RxD, provided that bits R and REN are set. The receive data input line RxD is sampled at 16 times the rate of the selected baudrate.
Page 156 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) The receive FIFO cannot be accessed directly. All data read operations from the RXFIFO are executed by reading the RBUF register. RXFCON.RXFITL = 0011 Byte 6 Byte 5...
Page 157 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) enabled but empty, an error interrupt EIR will be generated as well with bit OE set. In this case, the receive FIFO filling level RXFFL is set to 0000...
Page 158: Fifo Transparent Mode
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 18.2.6 FIFO Transparent Mode In Transparent Mode, a specific interrupt generation mechanism is used for receive and transmit buffer interrupts. In general, in Transparent Mode, receive interrupts are always generated if data bytes are available in the RXFIFO.
Page 159: Irda Mode
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Note: The Receive FIFO Interrupt Trigger Level bitfield RXFITL is a don’t care in Transparent Mode. Interrupt generation for the transmit FIFO depends on the TXFIFO filling level and the execution of write operations to the register TBUF.
Page 160: Rxd/Txd Data Path Selection In Asynchronous Modes
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Table 18-1 Formulas for IrDA Pulse Width Calculation PMW_IPMW Formulas 1 … 255 PMW >> 1 --------------------------------------- -------------------------------- - × IPW min 16 Baudrate -------------- - The contents of PW_VALUE further define the minimum IrDA pulse width (...
Page 161 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Autobaud Detection ABCON RXINV TXINV ABEM IrDA IrDA Coding Decode Asynch. Mode Logic RxDI MCA05442 Figure 18-11 RxD/TxD Data Path in Asynchronous Modes Note: In Echo Mode the transmit output signal is blocked by the Echo Mode output multiplexer.
Page 162: Synchronous Operation
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 18.3 Synchronous Operation Synchronous Mode supports half-duplex communication, basically for simple I/O expansion via shift registers. Data is transmitted and received via line RxD while line TxD outputs the shift clock.
Page 163: Synchronous Transmission
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 18.3.1 Synchronous Transmission Synchronous transmission begins within four state times after data has been loaded into TBUF, provided that bit R is set and bit REN is cleared (half-duplex, no reception).
Page 164 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Receive/Transmit Timing Shift Shift Shift Latch Shift Clock (TxD) Transmit Data Data Bit Data Bit Data Bit (RxD) n + 1 n + 2 Receive Data Valid Data...
Page 165: Baudrate Generation
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 18.4 Baudrate Generation The serial channel ASC has its own dedicated 13-bit baudrate generator with reload capability, allowing baudrate generation independent of other timers. The baudrate generator is clocked with a clock (...
Page 166 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) The output clock of the baudrate timer with the reload register is the sample clock in the Asynchronous Modes of the ASC. For baudrate calculations, this baudrate clock derived from the sample clock by a division by 16.
Page 167 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Table 18-3 Asynchronous Baudrate Formulas Using the Fixed Input Clock Dividers Formula 0 … 8191 Baudrate ----------------------------------- - × --------------------------------------- 1 – × 32 Baudrate Baudrate ----------------------------------- - ×...
Page 168 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Table 18-5 Async. Baudrate Formulas Using the Fractional Input Clock Divider Formula – 1 … 8191 1 … 511 × ----------- - ----------------------------------- - Baudrate × Baudrate ----------------------------------- - ×...
Page 169: Baudrate In Synchronous Mode
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 18.4.2 Baudrate in Synchronous Mode For synchronous operation, the baudrate generator provides a clock with four times the rate of the established baudrate (see Figure 18-15). 13-bit Reload Register...
Page 170: Autobaud Detection
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 18.5 Autobaud Detection 18.5.1 General Operation Autobaud Detection provides a capability to recognize the mode and the baudrate of an asynchronous input signal at RxD. Generally, the baudrates to be recognized must be known by the application.
Page 171: Serial Frames For Autobaud Detection
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 18.5.2 Serial Frames for Autobaud Detection The Autobaud Detection is based on the serial reception of a specific two-byte serial frame. This serial frame is build up by the two ASCII bytes “at” or “AT” (“aT” or “At” are not allowed).
Page 172: Baudrate Selection And Calculation
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 7 Bit, Even Parity ‘A’ = 41 ‘T’ = 54 Start Parity Stop Start Parity Stop 7 Bit, Odd Parity ‘A’ = 41 ‘T’ = 54 Start Parity Stop...
Page 173 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) In general, the baudrate generator in Asynchronous Mode is build up by two parts (see also Figure 18-14): • The clock prescaler part which derives from • The baudrate timer part which generates the sample clock...
Page 174 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) According to Table 18-8 a baudrate of 9600 bit/s is achieved when register ASCx_BG is loaded with a value of 047 , assuming that has been set to 11.0592 MHz.
Page 175 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Non-Standard Baudrates Due to the relationship between Br0 to Br8 in Table 18-8 concerning the divide factor d other baudrates than the standard baudrates can be also selected. E.g. if a baudrate of 50 kbit/s has to be detected, Br2 is e.g.
Page 176: Overwriting Registers On Successful Autobaud Detection
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 18.5.4 Overwriting Registers on Successful Autobaud Detection With a successful Autobaud Detection some bits in registers ASCx_CON and ASCx_BG are automatically set to a value which corresponds to the mode and baudrate of the...
Page 177: Hardware Error Detection Capabilities
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 18.6 Hardware Error Detection Capabilities To improve the safety of serial data exchange, the serial channel ASC provides an error interrupt request flag to indicate the presence of an error, and three (selectable) error status flags in register ASCx_CON to indicate which error has been detected during reception.
Page 178: Interrupts
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 18.7 Interrupts Six interrupt sources are provided for serial channel ASC. Line TIR indicates a transmit interrupt, TBIR indicates a transmit buffer interrupt, RIR indicates a receive interrupt and EIR indicates an error interrupt of the serial channel.
Page 179 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Asynchronous Mode TBIR TBIR TBIR Idle Idle Synchronous Mode TBIR TBIR TBIR Idle Idle Asynchronous Modes Autobaud Detection ABSTIR ABDETIR ABDETIR Idle 1. Character 2. Character 1) Only if FCDETEN = 1...
Page 180 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) The two autobaud interrupt request lines (start of autobaud detection and end of autobaud detection) in each ASC module are ‘ORed’ together; the ‘ORed’ output signal is connected to the interrupt control register. This is shown in Figure 18-20.
Page 181 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Table 18-12 ASC Interrupt Sources (cont’d) Interrupt Signal Description Receive The interrupt is generated when the received frame is copied Interrupt from the receive shift register to the receive buffer register. If...
Page 182: Registers
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 18.8 Registers Table 18-13 shows all registers which are required for programming the ASC modules. It summarizes the ASC kernel registers and the interrupt control registers and lists their addresses.
Page 183 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Control Register The operating mode of the serial channel ASC is controlled by its control register CON. This register contains control bits for mode and error check selection, and status flags for error identification.
Page 184 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Field Bits Type Description Fractional Divider Enable Fractional divider disabled Fractional divider enabled and used as prescaler for baudrate generator (bit BRS is don’t care) Overrun Error Flag Set by hardware on an overrun/underflow error (OEN = 1).
Page 185 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Field Bits Type Description [2:0] Mode Control 000 8-bit-data for synchronous operation 001 8-bit-data for asynchronous operation 010 8-bit-data IrDA Mode for asynchronous operation 011 7-bit-data and parity for asynchronous...
Page 186 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Fractional Divider Register The ASC fractional divider register FDV contains the 9-bit divider value for the fractional divider (Asynchronous Mode only). It is also used for reference clock generation of the autobaud detection unit.
Page 187 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) IrDA Pulse Mode/Width Register The ASC IrDA pulse mode and width register PMW contains the 8-bit IrDA pulse width value and the IrDA pulse width mode select bit. This register is only required in the IrDA operating mode.
Page 188 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Transmitter Buffer Register The ASC transmitter buffer register TBUF contains the transmit data value in Asynchronous and Synchronous Mode. ASCx_TBUF Transmit Buffer Register (Table 18-13) Reset Value: 0000...
Page 189 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Receiver Buffer Register The ASC Receiver buffer register RBUF contains the transmit data value in Asynchronous and Synchronous Modes. ASCx_RBUF Receive Buffer Register (Table 18-13) Reset Value: 0000...
Page 190 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Autobaud Control Register The autobaud control register ABCON of the ASC module is used to control the autobaud detection operation. It contains its general enable bit, the interrupt enable control bits, and data path control bits.
Page 191 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Field Bits Type Description ABSTEN Start of Autobaud Detection Interrupt Enable Start of Autobaud Detection interrupt disabled Start of Autobaud Detection interrupt enabled AUREN Automatic Autobaud Control of CON.REN CON.REN is not affected during autobaud...
Page 192 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Autobaud Status Register The autobaud status register ABSTAT of the ASC module indicates the status of the autobaud detection operation. ASCx_ABSTAT Autobaud Status Register ESFR (Table 18-13) Reset Value: 0000...
Page 193 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Field Bits Type Description FCCDET First Character with Capital Letter Detected No capital ‘A’ character detected Capital ‘A’ character detected Bit is cleared by hardware when ABEN is set or if FCSDET or SCSDET or SCCDET is set.
Page 194 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Receive FIFO Control Register ASCx_RXFCON Receive FIFO Control Reg. ESFR (Table 18-13) Reset Value: 0100 RXFITL Field Bits Type Description RXFITL [11:8] Receive FIFO Interrupt Trigger Level Defines a receive FIFO interrupt trigger level. A...
Page 195 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Field Bits Type Description RXFFLU Receive FIFO Flush No operation Receive FIFO is flushed Note: Setting RXFFLU clears bitfield RXFFL in register FSTAT. RXFFLU is always read as 0.
Page 196 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Transmit FIFO Control Register ASCx_TXFCON Transmit FIFO Control Reg. ESFR (Table 18-13) Reset Value: 0100 TXFITL Field Bits Type Description TXFITL [11:8] Transmit FIFO Interrupt Trigger Level Defines a transmit FIFO interrupt trigger level. A...
Page 197 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Field Bits Type Description TXFFLU Transmit FIFO Flush No operation Transmit FIFO is flushed Note: Setting TXFFLU clears bitfield TXFFL in register ASCx_FSTAT. TXFFLU is always read as 0.
Page 198 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) FIFO Status Register ASCx_FSTAT FIFO Status Register ESFR (Table 18-13) Reset Value: 0000 TXFFL RXFFL Field Bits Type Description TXFFL [11:8] Transmit FIFO Filling Level 0000 Transmit FIFO is filled with zero bytes 0001 Transmit FIFO is filled with one byte …...
Page 199: Interfaces Of The Asc Modules
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) 18.9 Interfaces of the ASC Modules In the XC161 the ASC modules are connected to IO ports and other internal modules according to Figure 18-21 Figure 18-22. The input/output lines of ASC0 and ASC1 are connected to pins of Ports P3. The 6 interrupt request lines of each module are connected to the Interrupt Control Block.
Page 200 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Asynchronous/Synchronous Serial Interface (ASC) Note: In synchronous operating mode, the direction of the RxD pin is not automatically set by the ASC modules; it must be switched by software via the corresponding bit in register DP3, depending on the selected mode (receive or transmit data).
Page 201: High-Speed Synchronous Serial Interface (Ssc)
High-Speed Synchronous Serial Interface (SSC) High-Speed Synchronous Serial Interface (SSC) The XC161 contains two High-Speed Synchronous Serial Interfaces, SSC0 and SSC1. The following sections present the general features and operations of such an SSC module. The final section describes the actual implementation of the two SSC modules including their interconnections with other on-chip modules.
Page 202 XC161 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) MSCLK (Master Serial Shift Clock) or input via line SSCLK (Slave Serial Shift Clock). Both lines are connected to pin SCLK. These pins are alternate functions of port pins.
Page 203: Operating Mode Selection
XC161 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) MSCLK to Pin Baudrate Clock SSCLK SCLK Generator Control TIRQ Transmit Interrupt RIRQ Receive Interrupt Request Control Block EIRQ Error Interrupt Request Status Control to Pin Input/...
Page 204 XC161 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) SSC Control Register (SSCx_CON.EN = 0: Programming Mode) SSCx_CON SSC Control Register (Table 19-2) Reset Value: 0000 BEN PEN REN TEN LB Field Bits Type Description Enable Bit = 0 Transmission and reception disabled.
Page 205 XC161 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) Field Bits Type Description Clock Polarity Control Idle clock line is low, leading clock edge is low- to-high transition. Idle clock line is high, leading clock edge is high-to-low transition.
Page 206 XC161 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) Field Bits Type Description Busy Flag Set while a transfer is in progress. Do not write to!!! Baudrate Error Flag No error More than factor 2 or 0.5 between slave’s...
Page 207 XC161 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) The shift register of the SSC is connected to both, the transmit lines and the receive lines via the pin control logic (see block diagram in Figure 19-2).
Page 208: Full-Duplex Operation
XC161 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) the shift clock line in the idle state. Thus, for an idle-high clock, the leading edge is a falling edge, a 1-to-0 transition (see Figure 19-3). Shift Clock CON.
Page 209 XC161 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) Master Device #1 Device #2 Slave Shift Register Shift Register MTSR MTSR Transmit MRST MRST Receive SCLK SCLK Clock Clock Clock Symbols Device #3 Slave Shift Register...
Page 210 XC161 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) data on the receive line sent by the selected slave is avoided when all slaves not selected for transmission to the master only send ones (1). Because this high level is not actively driven onto the line, but only held through the pull-up device, the selected slave can pull this line actively to a low level when transmitting a zero bit.
Page 211: Half-Duplex Operation
XC161 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) 19.2.3 Half-Duplex Operation In a Half-Duplex configuration, only one data line is necessary for both, receiving and transmitting of data. The data exchange line is connected to both, the MTSR and MRST pins of each device, the shift clock line is connected to the SCLK pin.
Page 212: Continuous Transfers
XC161 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) 19.2.4 Continuous Transfers When the transmit interrupt request flag is set, it indicates that the transmit buffer SSCx_TB is empty and ready to be loaded with the next transmit data. If SSCx_TB has...
Page 213 XC161 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) Baudrate Timer/Reload Register The SSC Baudrate Timer/Reload Register SSCx_BR has a double function. While the SSC is disabled, it serves as the reload register for the baudrate timer. Writing to it loads the timer reload register with the written reload value.
Page 214: Error Detection Mechanisms
XC161 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) 19.2.6 Error Detection Mechanisms The SSC is able to detect four different error conditions. Receive Error and Phase Error are detected in all modes; Transmit Error and Baudrate Error only apply to Slave Mode.
Page 215 XC161 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) clock, changes between one cycle before and two cycles after the latching edge of the shift clock signal SCLK. This condition sets the error flag PE and, when enabled via bit PEN, the error interrupt request line EIRQ.
Page 216: Ssc Register Summary
XC161 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) 19.2.7 SSC Register Summary Table 19-2 SSC Module Register Summary Name Description SSC0 Reg. SSC1 Addresses Area Addresses 16-Bit 8-Bit 16-Bit 8-Bit SSCx_CON Control Register FFB2 FF5E...
Page 217: Port Configuration Requirements
XC161 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) 19.2.8 Port Configuration Requirements Table 19-3 shows the required register setting to configure the IO lines of the SSC modules for master or slave mode operation. Table 19-3...
Page 218: Interfaces Of The Ssc Modules
XC161 Derivatives Peripheral Units (Vol. 2 of 2) High-Speed Synchronous Serial Interface (SSC) 19.3 Interfaces of the SSC Modules In the XC161 the SSC modules are connected to IO ports and other internal modules according to Figure 19-8 Figure 19-9.
Page 219: Iic-Bus Module
One line is responsible for clock transfer and synchronization (SCL), the other is responsible for the data transfer (SDA). The on-chip IIC-Bus Module connects the XC161 to other external controllers and/or peripherals via the two-line serial IIC-Bus interface. The IIC-Bus Module provides communication at data rates of up to 400 kbit/s and features 7-bit addressing as well as 10-bit addressing.
Page 220: Overview
Monitor block. In addition, this block provides the port pin enable control for the three possible SCL/SDA signal pairs. Due to the feature that the IIC-Bus Module of the XC161 can control up to three SCL/SDA signal pairs, it is possible to build a system with separate IIC-buses as shown Figure 20-2.
Page 221 XC161 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module Note: Per definition, an IIC-Bus system is a Wired-AND configuration. The active (dominant) level is the low level, while the high level is not actively driven by the stations (or nodes), but held through external pull-up devices. For this purpose, the respective pin drivers must be switched to open drain mode.
Page 222 XC161 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module From the programmer’s point of view, the term ‘IIC-Bus Module’ refers to a set of registers which are associated with this peripheral, including the port pins which may be used for alternate input/output functions, and including their direction control bits.
Page 223: Register Description
XC161 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module 20.2 Register Description In the following, the registers of the IIC-Bus Module are described in detail. IIC_CON Control Register XSFR (E602 /--) Reset Value: 0000 STP IGE TRX INT RSC M10...
Page 224 XC161 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module Field Bits Type Description ACKDIS Acknowledge Pulse Disable An acknowledge pulse is generated for each received byte No acknowledge pulse is generated Note: ACKDIS is automatically cleared by a stop condition.
Page 225 XC161 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module IIC_ST Status Register XSFR (E604 /--) Reset Value: 0000 BB LRB SLA AL ADR Field Bits Type Description [10:8] Transmit Byte Counter Displays the number of correctly transferred bytes. Section 20.3.4 for details.
Page 226 XC161 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module Field Bits Type Description Last Received Bit Bit LRB represents the last bit (i.e. the acknowledge bit) of the last transferred byte. It is automatically cleared by a read/write access to the buffer RTB0 …...
Page 227 XC161 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module IIC_ADR Address Control Register XSFR (E606 /--) Reset Value: 0000 PREDIV Field Bits Type Description BRPMOD Baudrate Generator Mode Control Mode 0: Reciprocal Divider Mode 1: Fractional Divider PREDIV [14:13] rw...
Page 228 XC161 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module IIC_CFG Configuration Control Register XSFR (E600 /--) Reset Value: 0000 Field Bits Type Description [15:8] Baudrate Prescaler Value Determines the baudrate for the IIC-Bus module together with bit ADR.BRPMOD and bitfield ADR.PREDIV...
Page 229 XC161 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module IIC_RTBH Receive/Transmit Buffer High XSFR (E60A /--) Reset Value: 0000 RTB3 RTB2 IIC_RTBL Receive/Transmit Buffer Low XSFR (E608 /--) Reset Value: 0000 RTB1 RTB0 Field Bits Type Description RTBx [31:24], Receive/Transmit Buffer Bytes (x = 3 …...
Page 230: Iic-Bus Module Operation
20.3.2 Operation in Multimaster Mode In Multi-Master Mode, the XC161 is not the only master on the bus and must share IIC- Bus usage with other masters. This requires bus arbitration, as only one master may control the bus at a given time.
Page 231: Operation In Slave Mode
When the XC161 wants to use the IIC-Bus, it prepares to start a transfer as in Single- Master Mode. The next recommended step is to poll bit BB to check whether the bus is busy.
Page 232: Transmit/Receive Buffer
XC161 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module If the device has not been selected, it remains idle in Slave Mode. If the device has been selected, the read/write bit R/W, which has been received together with the address information, needs to be checked by software to determine the further actions.
Page 233: Baud Rate Generation
XC161 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module 20.3.5 Baud Rate Generation In order to give the user high flexibility in selection of CPU frequency and IIC-Bus baudrate without constraints to baudrate accuracy, a flexible baudrate generator has been implemented.
Page 234: Notes For Programming The Iic-Bus Module
XC161 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module Fractional Divider Mode (BRPMOD = 1) The resulting baudrate is: × × × <PREDIV> 3 × <BRP> 1024 ------------------------------------------------ - -------------------------------------------------------------------- - (20.2) × × <PREDIV> 1024 Table 20-2 IIC-Bus Baudrate Examples for Mode 1...
Page 235: Interrupt Request Operation
XC161 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module 20.4 Interrupt Request Operation The IIC-Bus Module can generate three different interrupt requests, each with its own request flag. However, due to the nature of these requests, it is sufficient to use only two interrupt nodes to process the requests.
Page 236 XC161 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module End-of-Data-Transmission Interrupt, IRQE This request is activated and the flag is set when the current data transfer is terminated either by a repeated start, by a stop, or by a missing acknowledge.
Page 237: Port Connection And Configuration
100 kbit/s, 2 k Ω for operation at 400 kbit/s). All pins of the XC161 that are to be used for IIC-Bus communication provide open-drain drivers, and must be programmed to output operation, and their alternate function must be enabled (by setting the respective port output latch to 1), before any communication can be established.
Page 238 XC161 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module Table 20-3 shows the required register setting to configure the IO lines of the IIC-Bus Module for master and slave mode operation. Please note that all lines must be configured for open-drain output operation. This is required, e.g., to enable a slave module to actively hold the SCL line low as long as it cannot accept further bus transactions.
Page 239: Interfaces Of The Iic-Bus Module
Peripheral Units (Vol. 2 of 2) IIC-Bus Module 20.6 Interfaces of the IIC-Bus Module In the XC161, the IIC-Bus Module is connected to IO ports and other internal modules according to Figure 20-7. The input/output lines of the module are connected to pins of Ports P9. The 2 interrupt request lines are connected to the Interrupt Control Block.
Page 240: Iic-Bus Overview
XC161 Derivatives Peripheral Units (Vol. 2 of 2) IIC-Bus Module 20.7 IIC-Bus Overview Figure 20-8 gives a brief overview of the major definitions of the IIC-Bus operation. Normal Data Transfer Data Stable Start and Stop Conditions Start Stop Address and Acknowledge...
Page 241: Twincan Module
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module TwinCAN Module 21.1 Kernel Description 21.1.1 Overview The TwinCAN module contains two Full-CAN nodes operating independently or exchanging data and remote frames via a gateway function. Transmission and reception of CAN frames is handled in accordance to CAN specification V2.0 part B (active). Each of the two Full-CAN nodes can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers.
Page 242 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module TwinCAN Module Kernel TxDCA Clock Control RxDCA Node A Node B Address Port Decoder Control TxDCB Message Object Buffer Interrupt RxDCB Control TwinCAN Control TwinCAN Control MCB05471 Figure 21-1 General Block Diagram of the TwinCAN Module...
Page 243 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module • Two separate CAN nodes, subdivided into a bit stream processor, a bit timing control unit, an error handling logic, an interrupt request generation unit and a node control logic: –...
Page 244: Twincan Control Shell
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 21.1.2 TwinCAN Control Shell 21.1.2.1 Initialization Processing After an external hardware reset or while it is bus-off, the respective CAN controller node is logically disconnected from the associated CAN bus and does not participate in any message transfer.
Page 245: Interrupt Request Compressor
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 21.1.2.2 Interrupt Request Compressor The CAN module is equipped with 32 × 2 message object specific interrupt request sources and 2 × 4 node control interrupt request sources. A request compressor condenses these 72 sources to 8 CAN interrupt nodes reporting the interrupt requests of the CAN module.
Page 246: Global Control And Status Logic
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 21.1.2.3 Global Control and Status Logic The receive interrupt pending register RXIPND contains 32 individual flags indicating a pending receive interrupt for the associated message objects. Flag RXIPNDn is set by hardware if the corresponding message object has correctly received a data or remote frame and the correlated interrupt request generation has been enabled by RXIEn = ‘10’.
Page 247: Can Node Control Logic
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 21.1.3 CAN Node Control Logic 21.1.3.1 Overview Each node is equipped with an individual node control logic configuring the global behavior and providing status information. The configuration mode is activated when the ACR/BCR register bit CCE is set to ‘1’.
Page 248 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module • bit BOFF is set when the transmit error counter exceeded the error limit of 255 and the respective CAN node controller has been logically disconnected from the associated CAN bus.
Page 249: Timing Control Unit
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 21.1.3.2 Timing Control Unit According to ISO-DIS 11898 standard, a CAN bit time is subdivided into different segments (Figure 21-4). Each segment consists of multiples of a time quantum . The...
Page 250 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Calculation of the Bit Time = (BRP + 1) / , if DIV8X = ‘0’ = (BRP + 1) / 8 × , if DIV8X = ‘1’ Sync = (TSEG1 + 1) ×...
Page 251: Bitstream Processor
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 21.1.3.3 Bitstream Processor Based on the objects in the message buffer, the bitstream processor generates the remote and data frames to be transmitted via the CAN bus. It controls the CRC generator and adds the checksum information to the new remote or data frame.
Page 252: Node Interrupt Processing
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 21.1.3.5 Node Interrupt Processing Each CAN node is equipped with 4 interrupt sources supporting the • global transmit/receive logic, • CAN frame counter, • error reporting system. LECIE TRINP TXOK >1...
Page 253: Message Interrupt Processing
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module register ACR/BCR is set to ‘1’, an interrupt request is generated on any modification of bits EWRN and BOFF. The associated interrupt node pointer is defined by bitfield EINP in control register AGINP/BGINP.
Page 254 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Interrupt Request Source IMR4 Mask Register INTID Value IMC34 IMC33 IMC32 TXOK >1 >1 Global RXOK Transmit INTD = 1 Receive Logic EWRN >1 BOFF MCA05477 Figure 21-7 INTID Mask for Global Interrupt Request Sources...
Page 255: Message Handling Unit
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 21.1.4 Message Handling Unit A message object is the basic information unit exchanged between the CPU and the CAN controller. 32 message objects are provided by the internal CAN memory. Each of these objects has an identifier, its own set of control and status bits and a separate data area.
Page 256: Arbitration And Acceptance Mask Register
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 21.1.4.1 Arbitration and Acceptance Mask Register The arbitration register MSGARn is used to filter the incoming messages and to provide the outgoing messages with an identifier. The acceptance mask register MSGAMRn may be used to disable some identifier bits of an incoming message for the acceptance test.
Page 257: Handling Of Remote And Data Frames
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 21.1.4.2 Handling of Remote and Data Frames Message objects can be set up for transmit or receive operation according to the selected value for control bit DIR. The impact of the message object type on the...
Page 258: Handling Of Transmit Message Objects
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 21.1.4.3 Handling of Transmit Message Objects A message object with direction flag DIR = ‘1’ (message configuration register MSGCFGn) is handled as transmit object. All message objects with bitfield MSGVAL = ‘10’ are operable and taken into account by the CAN node controller operation described below.
Page 259 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module If several valid message objects with pending transmission request are noticed by the associated CAN node controller, the contents of the message object with the lowest message number is transmitted first.
Page 260 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Bus Free Matching TXRQ = ‘10’ Remote Frame CPUUPD = ‘01’ Received NEWDAT := ‘01’ TXRQ := ‘10’ Copy Message to RMTPND := ‘10’ Bitstream Processor Send Message RXIE := ‘10’...
Page 261: Handling Of Receive Message Objects
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 21.1.4.4 Handling of Receive Message Objects A message object with direction flag DIR = ‘0’ (message configuration register MSGCFGn) is handled as receive object. In the initialization phase, the transmit request bitfield (TXRQ), the message lost bitfield (MSGLST) and the NEWDAT bitfield in register MSGCTR should be reset.
Page 262 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Bus Idle Matching TXRQ = ‘10’ Data Frame CPUUPD = ‘01’ Received NEWDAT := ‘01’ NEWDAT = ‘10’ Load Identifier and Control Bits into Bitstream Processor Send Remote Frame MSGLST := ‘10’...
Page 263: Single Data Transfer Mode
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 21.1.4.5 Single Data Transfer Mode The single data transfer mode is a useful feature in order to broadcast data over the CAN bus without unintended doubling of information. The single data transfer mode is selected via bit SDT in the FIFO/Gateway control register MSGFGCRn.
Page 264: Can Message Object Buffer (Fifo)
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 21.1.5 CAN Message Object Buffer (FIFO) In case of a high CPU load, it may be difficult to process an incoming data frame before the corresponding message object is overwritten with the next input data stream provided by the CAN node controller.
Page 265 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Table 21-2 Message Objects Providing FIFO Base Functionality Msg. Object n > … FIFO Size 2 stage FIFO 4 stage FIFO – – – – – – 8 stage FIFO –...
Page 266: Buffer Access By The Can Controller
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module according to the FIFO rules is allowed as long as the limit of 32 message objects is not exceeded. 21.1.5.1 Buffer Access by the CAN Controller The data transfer between the message buffer and the CAN bus is managed by the associated CAN controller.
Page 267: Buffer Access By The Cpu
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module message data is overwritten, which is indicated by flag MSGLST in the corresponding MSGCTR register. If the FIFO buffer was initialized with transmit message objects, the CAN controller starts the transfer with the contents of buffer element 0 (FIFO base object) and increments bitfield CANPTR in control register MSGFGCRn, pointing to the next element to be transmitted.
Page 268: Gateway Message Handling
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 21.1.6 Gateway Message Handling The CAN module supports an automatic information transfer between two independent CAN bus systems without CPU interaction. CAN Bus A CAN Bus B Node A Node B...
Page 269: Normal Gateway Mode
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module To FIFO To FIFO To FIFO To FIFO Object n Object n + 1 Object n + 2 Object n + 3 Source Bus Speed A Message 1 Message 2...
Page 270 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module • When bit IDC is set, the identifier of the source message object is copied to the <s> destination message object. Otherwise, the identifier of the destination message object is not modified.
Page 271 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module = ‘000’: <d> The operation with a standard message object on the destination side is illustrated in Figure 21-17. Source CAN Bus Destination CAN Bus Gateway Gateway Gateway Source Destination...
Page 272 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module = ‘100’: <d> The operation with a normal mode gateway message object for incoming (remote) frames on the destination side is illustrated in Figure 21-18. Source CAN Bus Destination CAN Bus...
Page 273: Normal Gateway With Fifo Buffering
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 21.1.6.2 Normal Gateway with FIFO Buffering = ‘01x’: <d> When the gateway destination object is programmed as FIFO buffer, bitfield CANPTR <s> is used as pointer to the FIFO element to be addressed as destination for the next copy process.
Page 274 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Source CAN Bus Destination CAN Bus Gateway Gateway Gateway Source Destination Node = <d> MMC<sl> = ‘011’ Pointer to CANPTR<sl> Base Node = <s> Node = <d> Object MMC = ‘100’...
Page 275 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module frame with matching identifier should initiate an interrupt service request for the addressed FIFO message object. The associated interrupt service routine may copy the message identifier and the data length code from the received remote frame to a receive message object linked with the source side CAN node.
Page 276: Shared Gateway Mode
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 21.1.6.3 Shared Gateway Mode In shared gateway mode, only one message object is required to implement a gateway functionality. The shared gateway object can be considered as normal message object,...
Page 277 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Bit SRREN determines, whether a remote frame, received on the destination side, is transferred through the gateway to the source node or is directly answered by a data frame generated on the destination side.
Page 278 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module When a shared gateway message object, set up as receive object on the source side (lower left state bubble in Figure 21-22), receives a data frame while GDFS is set to ‘1’,...
Page 279 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Impact of the transfer state transitions on the bitfields in the message object in shared gateway mode: Table 21-3 Shared Gateway State Transitions (Part 1 of 2) Bitfields Transition 1:...
Page 280: Programming The Twincan Module
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 21.1.7 Programming the TwinCAN Module A software initialization should be performed by setting bit INIT in the CAN node specific control register ACR/BCR to ‘1’. While bit INIT is set, all message transfers between the CAN controller and the CAN bus are disabled.
Page 281: Controlling A Message Transfer
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module register MSGCFGn. Message objects can be provided with a FIFO buffer. The buffer size is determined by bitfield FSIZE in the FIFO/Gateway control register MSGFGCRn. For transmit message objects, the object property assignment can be already finished by setting MSGVAL to ‘10’, before the corresponding data partition has been initialized.
Page 282 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Power Up (all bits written with reset values) MSGVAL = ‘01’ INTPND := ‘01’ RMTPND := ‘01’ TXRQ := ‘01’ NEWDAT := ‘01’ DIR := ‘1’ (transmit object) Message Initialization...
Page 283 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Power Up (all bits written with reset values) MSGVAL = ‘01’ INTPND := ‘01’ RMTPND := ‘01’ TXRQ := ‘01’ NEWDAT := ‘01’ DIR := 0 (receive object) Initialization MSGLST := ‘01’...
Page 284: Loop-Back Mode
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 21.1.8 Loop-Back Mode The TwinCAN module’s loop-back mode provides the means to internally test the TwinCAN module and CAN driver software. CAN driver software can be developed and tested without being connected to a CAN bus system.
Page 285: Single Transmission Try Functionality
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 21.1.9 Single Transmission Try Functionality Single transmission try functionality is controlled individually for each message object by bit STT in register MSGFGCRn. If the single transmission try functionality is enabled, the transmit request flag TXRQ is reset immediately after the transmission of a frame related to this message object has started.
Page 286: Module Clock Requirements
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 21.1.10 Module Clock Requirements The functionality of the TwinCAN module is programmable in several respects. In order to operate at a specific baudrate with a given functionality a certain minimum module clock frequency is required.
Page 287: Twincan Register Description
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 21.2 TwinCAN Register Description 21.2.1 Register Map Figure 21-26 shows all registers associated with the TwinCAN module kernel. CAN Node A CAN Node B CAN Message Global CAN Registers Registers...
Page 288 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Module Offset +000 Control Reg. Reserved Status Reg. Interrupt Pending Reg. +200 Bit Timing Reg. CAN Node A Node A Global INP Reg. Registers Frame Counter Reg. +240 INTID Mask 0 Reg.
Page 289: Can Node A/B Registers
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 21.2.2 CAN Node A/B Registers The Node Control Register controls the initialization, defines the node specific interrupt handling and selects an operation mode. Node A Control Register Reset Value: 0001...
Page 290 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Field Bits Type Description LECIE Last Error Code Interrupt Enable A last error code interrupt is generated when an error code is set in bitfield LEC in the status registers ASR or BSR.
Page 291 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module The Node Status Register reports error states and successfully ended data transmissions. This register has to be read in order to release the status change interrupt request. Node A Status Register...
Page 292 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Field Bits Type Description EWRN Error Warning Status No warning limit exceeded. One of the error counters in the Error Management Logic reached the error warning limit of 96. BOFF Bus-Off Status CAN controller is not in the bus-off state.
Page 293 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module The Interrupt Pending Register contains the identification number of the pending interrupt request with the highest priority. Node A Interrupt Pending Register Reset Value: 0000 0000 Node B Interrupt Pending Register...
Page 294 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Register AECNT/BECNT contains the values of the receive error counter and the transmit error counter. Some additional status/control bits allow for easier error analysis. AECNTH Node A Error Counter Register High...
Page 295 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Field Bits Type Description LETD Last Error Transfer Direction High The last error occurred while the corresponding CAN node was receiving a message (REC has been incremented). The last error occurred while the corresponding CAN node was transmitting a message (TEC has been incremented).
Page 296 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module The Bit Timing Register contains all parameters to adjust the data transfer baud rate and the bit timing. ABTRH Node A Bit Timing Register High Reset Value: 0000 ABTRL Node A Bit Timing Register Low...
Page 297 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Field Bits Type Description TSEG2 [14:12] Time Segment After Sample Point (TSEG2+1) time quanta after the sample point take into account a user defined delay and compensate a mismatch between transmitter and receiver clock phase.
Page 298 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module The Frame Counter Register controls the frame counter functionality and provides status information. AFCRH Node A Frame Counter Register High Reset Value: 0000 AFCRL Node A Frame Counter Register Low...
Page 299 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Field Bits Type Description CFCMD [3:0] Frame Count Mode High This bitfield defines the operation mode of the frame counter. This counter can work on frame base (frame count) or on time base (time stamp).
Page 300 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Field Bits Type Description [5:4], Reserved; read as ‘0’; should be written with ‘0’. [15:8] High 1) If the frame counter functionality has been selected (CFCMD.3 = ‘0’), bit CFCMD.0 enables or disables the counting of foreign frames.
Page 301 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module The Global Interrupt Node Pointer Register connects each global interrupt request source with one of the 8 available CAN interrupt nodes. AGINP Node A Global Interrupt Node Pointer Register Reset Value: 0000...
Page 302 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module The Interrupt Identification Mask Registers allow for disabling the identification notification of a pending interrupt request in the AIR/BIR register. The Interrupt Mask Registers AIMR0/BIMR0 are used to enable the message specific interrupt sources (correct transmission/ reception) for the generation of the corresponding INTID value.
Page 303 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module The Interrupt Mask Registers AIMR4/BIMR4 are used to enable the node specific interrupt sources (last error, correct reception, error warning/bussoff) for the generation of the corresponding INTID value. AIMR4 Node A INTID Mask Register 4...
Page 304: Can Message Object Registers
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 21.2.3 CAN Message Object Registers Each message object is provided with a set of control and data register. The corresponding register names are supplemented with a variable n running from 0 to 31 (e.g.
Page 305 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module The Message Data Register 4 contains the data bytes 4 to 7 of message object n. MSGDRHn4 (n = 31-0) Message Object n Data Register 4 High Reset Value: 0000...
Page 306 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Register MSGARn contains the identifier of message object n. MSGARHn (n = 31-0) Message Object n Arbitration Register High Reset Value: 0000 MSGARLn (n = 31-0) Message Object n Arbitration Register Low...
Page 307 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Register MSGAMRn contains the mask bits for the acceptance filtering of message object n. MSGAMRHn (n = 31-0) Message Object n Arbitration Mask Register High Reset Value: FFFF MSGAMRLn (n = 31-0)
Page 308 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Register MSGCTRn affects the data transfer between a CAN node controller and the corresponding message object n and provides a bitfield to store the captured value of the frame counter.
Page 309 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Field Bits Type Description MSGVAL [7:6] Message Object Valid The CAN controller only operates on valid message objects. Message objects can be tagged invalid while they are changed or if they are not used at all.
Page 310 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Field Bits Type Description RMTPND [15:14] Remote Pending Flag (used for transmit-objects) No remote node request for a message object data transmission. Transmission of the message object data has been requested by a remote node but the data has not yet been transmitted.
Page 311 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module The control and status element of the message control registers is implemented with two complementary bits (except the frame counter value). This special mechanism allows the selective setting or resetting of a specific element (leaving others unchanged) without requiring read-modify-write cycles.
Page 312 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Field Bits Type Description Transmit Message Object Remote Monitoring Mode Remote Monitoring mode is disabled. Remote Monitoring mode is enabled for this transmit message object. The identifier and DLC code of a remote frame with matching identifier are copied to this transmit message object in order to monitor incoming remote frames.
Page 313 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Field Bits Type Description RXINP [2:0] Receive Interrupt Node Pointer High Bitfield RXINP determines which interrupt node is triggered by a message object receive event, if bitfield RXIE in register MSGCTRn is set.
Page 314 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module MSGFGCRHn (n = 31-0) Message Object n FIFO/Gateway Control Register High Reset Value: 0000 MSGFGCRLn (n = 31-0) Message Object n FIFO/Gateway Control Register Low Reset Value: 0000 CANPTR STT SDT...
Page 315 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Field Bits Type Description GDFS Gateway Data Frame Send Specifies if a CAN data frame will be automatically generated on the destination side after new data has been transferred via gateway from the source to the destination side.
Page 316 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Field Bits Type Description Identifier Copy IDC controls the identifier handling during a frame transfer through a gateway. The identifier of the receiving object is not copied to the transmitting message object.
Page 317 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Field Bits Type Description FIFO Direction FD is only taken into account for a FIFO base object (the FD bits of all FIFO elements should have an identical value). It defines which transfer action (reception or transmission) leads to an update of the FIFO base object’s CANPTR.
Page 318 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Field Bits Type Description CANPTR [4:0] CAN Pointer for FIFO/Gateway Functions High Message object is configured in standard mode (MMC = ‘000’): No impact, CANPTR should be initialized with the respective message object number.
Page 319 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Field Bits Type Description [10:8] Message Object Mode Control High Bitfield MMC controls the functionality of message object n. Standard message object functionality FIFO functionality enabled (base object) FIFO functionality enabled (slave object)
Page 320: Global Can Control/Status Registers
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 21.2.4 Global CAN Control/Status Registers The Receive Interrupt Pending Register indicates the pending receive interrupts for message object n. RXIPNDH Receive Interrupt Pending Register High Reset Value: 0000 RXIPNDL Receive Interrupt Pending Register Low...
Page 321 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module The Transmit Interrupt Pending Register indicates whether a transmit interrupt is pending for message object n. TXIPNDH Transmit Interrupt Pending Register High Reset Value: 0000 TXIPNDL Transmit Interrupt Pending Register Low...
Page 322: Xc161 Module Implementation Details
TwinCAN module related interfaces such as port connections and interrupt control • all TwinCAN module related registers with its addresses and reset values 21.3.1 Interfaces of the TwinCAN Module In XC161 the TwinCAN module is connected to IO ports according to Figure 21-28. P4.4_rx Port 4 P4.4 Control P4.5_rx...
Page 323: Twincan Module Related External Registers
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 21.3.2 TwinCAN Module Related External Registers Figure 21-29 shows the module related external registers which are required for programming the TwinCAN module. Port Registers Interrupt Registers System Registers ALTSEL0P4 CAN_0IC...
Page 324: System Registers
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 21.3.2.1 System Registers Register CAN_PISEL allows the user to select the input pins for the two TwinCAN receive signals RXDCA and RXDCB. CAN_PISEL TwinCAN Port Input Select Register Reset Value: 0000...
Page 325: Port Registers
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 21.3.2.2 Port Registers The port registers required to program to TwinCAN operation are listed as follows. ALTSEL0P4 P4 Alternate Select Register 0 Reset Value: 0000 Field Type Description ALTSEL0 6, 7 P4 Alternate Select Register 0 bit y P4.y...
Page 326 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module ALTSEL0P7 P7 Alternate Select Register 0 Reset Value: 0000 Field Type Description ALTSEL0 7, 5 P7 Alternate Select Register 0 Bit y P7.y associated peripheral output is not selected as...
Page 327 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module ALTSEL0P9 P9 Alternate Select Register 0 Reset Value: 0000 Field Type Description ALTSEL0 3, 1 P9 Alternate Select Register 0 Bit y P9.y associated peripheral output is not selected as...
Page 328 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module P9 Direction Ctrl. Register Reset Value: 0000 Field Type Description DP9.y 3 … 0 Port Direction Register DP9 Bit y Port line P9.y is an input (high-impedance) Port line P9.y is an output Note: Shaded bits are not related to TwinCAN operation.
Page 329 XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module Table 21-9 shows the required register setting to configure the IO lines of the TwinCAN module for operation. Table 21-9 TwinCAN IO Selection and Setup Port Lines Alternate Select Port Input Select...
Page 330: Interrupt Registers
XC161 Derivatives Peripheral Units (Vol. 2 of 2) TwinCAN Module 21.3.2.3 Interrupt Registers The interrupts of the TwinCAN module are controlled by the following interrupt control registers: • CAN_0IC • CAN_1IC • CAN_2I • CAN_3I • CAN_4I • CAN_5IC •...
Page 331: Register Table
1) The 8-bit short addresses are not available for the TwinCAN module kernel registers. 2) In the XC161 device, the CAN interrupt node 7 is shared with the SDLM interrupt 1. In order to avoid mismatches if the CAN interrupt 7 is used by the TwinCAN module, the SDLM interrupt 1 should be mapped to a common SDLM interrupt 0 (see register SDLM_PISEL).
Page 332: Serial Data Link Module Sdlm
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM Serial Data Link Module SDLM 22.1 Overview The Serial Data Link Module (SDLM) provides serial communication to a J1850 based multiplexed bus via an external J1850 bus transceiver chip. The module is conform to the SAE Class B J1850 specification and compatible to class 2 protocol.
Page 333: Sdlm Kernel Description
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM 22.2 SDLM Kernel Description SDLM receive Input RXJ1850 Control SDLM Address Module Decoder (Kernel) transmit Output Interrupt TXJ1850 Control Control interrupts SDLM_I0 SDLM_I1 Figure 22-1 General Block Diagram of the SDLM Interface...
Page 334: Frame Format Basics
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM 22.2.1.1 Frame Format Basics This chapter summarizes the basic definitions of the SAE Standard Class B Data Communication Network Interface protocol. The general J1850 frame format is defined as: idle, SOF, DATA_0, …, Data_N, CRC, EOD, NB, IFR_1, …, IFR_N, EOF, IFS, idle...
Page 335 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM Table 22-1 Abbreviations Used Symbol Name Description Start of Frame The SOF mark is used to uniquely identify the start of a frame. SOF is not used for CRC error calculation.
Page 336: J1850 Bits And Symbols
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM 22.2.1.2 J1850 Bits and Symbols Active Data Bit `1' Passive Active Data Bit `0' Passive Active Start of Frame (SOF) Passive Active End of Frame (EOF) Passive...
Page 337: Frame Arbitration
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM 22.2.1.3 Frame Arbitration The frame arbitration in the J1850 compatible networks follows the concept of Carrier Sense Multiple Access (CSMA) with non-destructive message arbitration. When two nodes have access to the bus at the same time, the priority decision is made during transmission.
Page 338 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM Internal FPI Bus Interface Date Link Controller Data Link Control Interrupt Receive Receive Transmit Control Buffer 0 Buffer 1 Buffer Timing (11 Bytes) (11 Bytes) (11 Bytes)
Page 339: Mode
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM 22.2.2.1 4x Mode • If high speed mode is used, all J1850 nodes should be configured to 4x mode when supported. • Those nodes which do not support 4x mode need to tolerate high speed operation (no error sign).
Page 340: Interrupt Handling
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM 22.2.3 Interrupt Handling The SDLM module can generate the interrupts on the following events: • Protocol related interrupt conditions (combined to interrupt SDLM_I0): – End of frame detected –...
Page 341: Message Operating Mode
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM 22.2.3.1 Message Operating Mode Basically two receive buffers (11 byte each) and one 11 byte transmit buffer are available for data transfer. This allows the transfer of a complete J1850 frame without reloading data bytes.
Page 342: Transmit Operation
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM Register TRANSSTAT contains information about the receive operation: • HEADER: single byte or consolidated header is received (set after 1 or 3 received bytes) • MSGREC: indicates a complete frame reception 22.2.3.3 Transmit Operation...
Page 343: In-Frame Response (Ifr) Operation
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM 22.2.4 In-Frame Response (IFR) Operation The module supports automatic IFR transmission for type 1, 2 IFR for three-byte consolidated headers (no CPU load required). If the IFRs are handled via the transmit buffer, TxCPU indicates the number of bytes to be transmitted.
Page 344: Block Mode
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM 22.2.5 Block Mode In Block Mode, the SDLM supports transfer of frames of unlimited length (application specific). Block mode is selected by BMEN = 1. In this case, only one receive buffer and the transmit buffer are available.
Page 345 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM In order to monitor the status of the bus during transmission, the SDLM always reads on the bus, even while transmitting. As a result, the user can check whether the message sent is equal to the message on the bus (test for arbitration).
Page 346: Bus Access In Fifo Mode
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM 22.2.6 Bus Access in FIFO Mode In FIFO mode (block mode or normal mode), the FIFOs are byte-oriented. In order to avoid mismatch in case of word accesses, the LSB of the pointers on CPU side select which byte of the word is taken into account.
Page 347: Flowcharts
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM 22.2.7 Flowcharts 22.2.7.1 Overview START Configure J1850 GLOBCON:=19H J1850 module is enabled CLKEN is enabled CLKDIV:=84H DIVIDER 5MHz crystal frequency) FIFO Mode is disabled BUFFCON:=00 TxCPU will not be incremented, bytes in buffer have to be addressed.
Page 348: Transmission Control
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM 22.2.7.2 Transmission Control Transmission of a Standard Message in FIFO Mode Bit TxINCE in register BUFFCON has to be set in order to provide FIFO functionality. Bitfield TxCPU is incremented after each write operation to TxD0. The transmit buffer is filled by multiple write actions to TxD0.
Page 349 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM Transmission of a Standard Message in Random Mode Start The transmit buffer should not be modified while the module is TIP=1 ? transmitting. The transmission request (if...
Page 350 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM Transmission in Block Mode Block mode is selected by BMEN = 1 in register GLOBCON. In block mode, FIFO access is automatically enabled (not dependent on RxINCE or TxINCE). The transmit buffer in block mode is 8 bytes long.
Page 351: Read Operations
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM 22.2.7.3 Read Operations Read of the Receive FIFO in Normal Mode Bit RxINCE in register BUFFCON has to be set in order to provide FIFO functionality. Register RxCPU is incremented after each read operation from RxD00. The receive buffer is read out by multiple read actions from RxD00.
Page 352 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM Read Operation in Block Mode Block mode is selected by BMEN = ‘1’ in register GLOBCON. In block mode, FIFO access is automatically enabled (not dependent on RxINCE or TxINCE). The receive buffer in block mode is 16 bytes long.
Page 353: Ifr Handling
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM 22.2.8 IFR Handling 22.2.8.1 IFR Types 1, 2 via IFRVAL The HEADER bit is automatically set by hardware after reception of the complete header (1 or 3 bytes) in the receive buffer on bus side. This buffer can be accessed at the consecutive relative addresses starting at base + 50 .
Page 354: Sdlm Register Description
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM 22.3 SDLM Register Description System Registers Globel Kernel Data Buffer Control Registers Control Registers PISEL GLOBCON TXCNT CLKDIV TXCPU TXDELAY RXCNT RXCPU BUFFSTAT RXCNTB TRANSSTAT SOFPTR BUSSTAT...
Page 355: Global Control And Timing Registers
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM 22.3.1 Global Control and Timing Registers The Global Control Register contains bits to select different transfer modes and to determine the message handling. GLOBCON Global Control Register...
Page 356 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM Field Bits Type Description OVWR Overwrite Enable Overwrite action of the receive buffer on SDLM side in case of an incoming frame and a full receive buffer on bus side (RBB = 1) disabled.
Page 357 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM Register CLKDIV allows for configuration of the internal timings. CLKDIV Clock Divider Register Reset Value: 0000 Field Bits Type Description [5:0] Clock Divider Bits This bitfield defines the value of the clock divider. In...
Page 358 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM Register TxDELAY allows for the compensation of the transceiver delay. TxDELAY Transceiver Delay Register Reset Value: 0014 RINV Field Bits Type Description [5:0] Transceiver Delay Bits This bitfield defines the transceiver delay, which is taken into account by the J1850 bitstream processor.
Page 359 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM Register IFR contains the IFRVAL bitfield, which can be sent out as source ID in case of an one-byte IFR (automatic transmission or triggered by SW). In-Frame Response Value Register...
Page 360: Control And Status Registers
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM 22.4 Control and Status Registers Register BUFFSTAT contains the buffer-related status flags. BUFFSTAT Buffer Status Register Reset Value: 0000 RBC RBB Field Bits Type Description Transmission in Progress...
Page 361 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM Field Bits Type Description Receive Buffer on Bus Side Full RBB = ‘1’ indicates that the receive buffer on J1850 side is full. In case of a new incoming message, this buffer is declared empty (RBB = 0) and overwritten by the new data if bit OVWR = ‘1’.
Page 362 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM Register TRANSSTAT contains transmission-related status flags and monitors three functional bits of the header of the currently received frame. TRANSSTAT Transmission Status Register Reset Value: 0000 Field...
Page 363 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM Field Bits Type Description Arbitration Lost ARL is set after the arbitration for transmission has been lost. It is reset by software or by hardware if the arbitration has been won or the transmission has been aborted.
Page 364 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM Register BUSSTAT contains bus-related status bits. BUSSTAT Bus Status Register Reset Value: 0000 IDLE EOD SOF Field Bits Type Description Start Of Frame Detected Indicates the detection of SOF; bit is reset by BUSRST.
Page 365 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM Register ERRSTAT contains error bits. The bits in this register have to be reset by SW. ERRSTAT Error Status Register Reset Value: 0000 Field Bits Type Description...
Page 366 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM Register BUFFCON contains the transfer-related control bits, including IFR control and FIFO control. BUFFCON Buffer Control Register Reset Value: 0000 INCE INCE Field Bits Type Description TXIFR...
Page 367 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM Field Bits Type Description CRCEN CRC Enable No CRC generation for type IFR via TxBuffer CRC enabled for IFR via TxBuffer If IFR is sent from IFRVAL, no CRC is generated (even if CRCEN = 1).
Page 368 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM Register FLAGRST contains the control bits to reset the error flags, the bus-related flags and the transfer-related status bits. FLAGRST Flag Reset Register Reset Value: 0000 Field...
Page 369 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM Register INTCON contains all interrupt enable bits. INTCON Interrupt Control Register Reset Value: 0000 Field Bits Type Description TRAIE Enable Transmit Interrupt The transmission interrupt is disabled.
Page 370: Transmission Related Registers
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM 22.4.1 Transmission Related Registers Register TXCNT contains the number of bytes of the transmit buffer, which have already been sent out on the bus. TXCNT Bus Transmit Byte Counter Register...
Page 371 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM Register TXCPU contains the pointers to the next empty byte in the transmit buffer (= number of bytes in the transmit buffer). TXCPU CPU Transmit Byte Counter Register...
Page 372 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM The transmit data registers contain the data bytes in the transmit buffer. In random mode mode, all data bytes can be directly accessed via their addresses, whereas in FIFO mode, only TXD0 should be used.
Page 373 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM TXD6 Transmit Data Register 6 Reset Value: 0000 TXDATA7 TXDATA6 Field Bits Type Description TXDATA6 [7:0] Transmit Buffer Data Byte 6 TXDATA7 [15:8] rw Transmit Buffer Data Byte 7...
Page 374: Reception Related Registers
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM 22.4.2 Reception Related Registers Register RXCNT contains the number of bytes received in this buffer. RXCNT Bus Receive Byte Counter Register (on CPU side) Reset Value: 0000...
Page 375 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM Register RXCPU contains the number of bytes already read out from this buffer. RXCPU CPU Receive Byte Counter Register (on CPU side) Reset Value: 0000 RxCPU Field...
Page 376 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM The receive data registers contain the data bytes in the receive buffer. In random mode mode, all data bytes can be directly accessed via their addresses, whereas in FIFO mode, only RXD00 should be used.
Page 377 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM RXD04 Receive Data Register 04 (on CPU side) Reset Value: 0000 RXDATA05 RXDATA04 Field Bits Type Description RXDATA04 [7:0] Receive Buffer 0 Data Byte 4 RXDATA05 [15:8] rh...
Page 378 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM RXD010 Receive Data Register 010 (on CPU side) Reset Value: 0000 RXDATA010 Field Bits Type Description RXDATA010 [7:0] Receive Buffer 0 Data Byte 8 [15:8] – Reserved; returns ‘0’ if read.
Page 379 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM Register SOFPTR contains the bitfield indicating the value of RXCNT after the last ENDF detection in block mode. SOFPTR Start-of-Frame Pointer Register Reset Value: 0000 SOFCNT Field...
Page 380 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM RXD12 Receive Data Register 12 (on bus side) Reset Value: 0000 RXDATA13 RXDATA12 Field Bits Type Description RXDATA12 [7:0] Receive Buffer 1 Data Byte 2 RXDATA13 [15:8] rh...
Page 381: Sdlm Module Register Table
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM RXD18 Receive Data Register 18 (on bus side) Reset Value: 0000 RXDATA19 RXDATA18 Field Bits Type Description RXDATA18 [7:0] Receive Buffer 1 Data Byte 8 RXDATA19 [15:8] rh...
Page 382: Xc161 Module Implementation Details
SDLM module related interfaces such as port connections and interrupt control • all SDLM module related registers with its addresses and reset values 22.6.1 Interfaces of the SDLM Module In XC161 the SDLM module is connected to Port pins according to Figure 22-18. Port 4 P4.4_rx Control P4.4...
Page 383 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM The SDLM module kernel has two interrupt request lines. The interrupt request line SDLM_I1 can share a interrupt node with SDLM_I0, or alternatively with the TwinCAN interrupt request line 7. The selection is controlled via bitfield I1SEL in the SDLM_PISEL register.
Page 384: Sdlm Module Related External Registers
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM 22.6.2 SDLM Module Related External Registers Figure 22-20 shows the module related external registers which are required for programming the SDLM module. Port Registers Interrupt Registers ALTSEL0P4...
Page 385: System Registers
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM 22.6.2.1 System Registers Register PISEL allows the user to select an input pin for the SDLM receive signal. Furthermore, the interrupt functionality of SDLM_I1 is defined. SDLM_PISEL...
Page 386: Port Registers
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM 22.6.2.2 Port Registers The interconnections between the SDLM module and the IO lines is controlled in the port logic of Port 4, Port 7 and Port 9. To configure the TxD output, the respective alternate select registers must be set accordingly.
Page 387 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM P4 Direction Ctrl. Register Reset Value: 0000 Field Type Description DP4.y 7, 6, 4 Port Direction Register DP4 Bit y Port line P4.y is an input (high-impedance) Port line P4.y is an output...
Page 388 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM P7 Direction Ctrl. Register Reset Value: 0000 Field Type Description DP7.y 7, 6 Port Direction Register DP7 Bit y Port line P7.y is an input (high-impedance) Port line P7.y is an output...
Page 389 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM ALTSEL1P9 P9 Alternate Select Register 1 Reset Value: 0000 Field Type Description ALTSEL1 P9 Alternate Select Register 1 Bit y P9.y associated peripheral output is not selected as...
Page 390 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM Table 22-3 shows the required register setting to configure the IO lines of the SDLM module for operation. Table 22-3 SDLM IO Selection and Setup Port Lines...
Page 391: Interrupt Registers
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Serial Data Link Module SDLM 22.6.2.3 Interrupt Registers The interrupt of the SDLM module is controlled by interrupt control register SDLM_IC. SDLM_IC SDLM Interrupt Ctrl. Reg. ESFR (F19A Reset Value: - - 00...
Page 392: Register Set
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Register Set This chapter summarizes all the kernel and module related external registers of the peripherals. The register list is organized into two parts - the first for PD+BUS peripherals and the second for LXBUS peripherals.
Page 393 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-1 PD+BUS Register Listing (cont’d) Short Name Address Description Reset Value Physical 8-bit Area ASC1_ F0BC ESFR ASC1 Autobaud Status Register 0000 ABSTAT ASC1_BG FEBC ASC1 Baud Rate Generator...
Page 394 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-1 PD+BUS Register Listing (cont’d) Short Name Address Description Reset Value Physical 8-bit Area GPT12E_ FF46 GPT12E Timer 5 Control Register 0000 T5CON GPT12E_ FF48 GPT12E Timer 6 Control Register 0000...
Page 395 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-1 PD+BUS Register Listing (cont’d) Short Name Address Description Reset Value Physical 8-bit Area CC1_SEM FE2C CAPCOM1 Single Event Mode 0000 Register CC1_DRM FF5A CAPCOM1 Double Register Mode 0000...
Page 396 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-1 PD+BUS Register Listing (cont’d) Short Name Address Description Reset Value Physical 8-bit Area Capture / Compare Unit 2 (CAPCOM2) CC2_M4 FF22 CAPCOM2 Mode Control Register 0000 CC2_M5 FF24...
Page 397 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-1 PD+BUS Register Listing (cont’d) Short Name Address Description Reset Value Physical 8-bit Area CC2_CC23 FE6E CAPCOM 2 Register 23 0000 CC2_CC24 FE70 CAPCOM 2 Register 24 0000 CC2_CC25...
Page 398 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-1 PD+BUS Register Listing (cont’d) Short Name Address Description Reset Value Physical 8-bit Area SDLM_ E910 – Global Control Register 0000 GLOBCON SDLM_ E914 – Clock Divider Register 0000...
Page 399 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-1 PD+BUS Register Listing (cont’d) Short Name Address Description Reset Value Physical 8-bit Area SDLM_ E94C – Bus Receive Byte Counter (CPU) 0000 RXCNT SDLM_ E94E – CPU Receive Byte Counter (CPU) 0000...
Page 400 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-1 PD+BUS Register Listing (cont’d) Short Name Address Description Reset Value Physical 8-bit Area Interrupt Control SSC0_TIC FF72 SSC0 Transmit Interrupt Control 0000 Register SSC0_RIC FF74 SSC0 Receive Interrupt Control...
Page 401 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-1 PD+BUS Register Listing (cont’d) Short Name Address Description Reset Value Physical 8-bit Area GPT12E_ FF60 GPT12E Timer 2 Interrupt Control 0000 T2IC Register GPT12E_ FF62 GPT12E Timer 3 Interrupt Control...
Page 402 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-1 PD+BUS Register Listing (cont’d) Short Name Address Description Reset Value Physical 8-bit Area CC1_CC5IC FF82 CAPCOM Register 5 Interrupt 0000 Control Register CC1_CC6IC FF84 CAPCOM Register 6 Interrupt...
Page 403 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-1 PD+BUS Register Listing (cont’d) Short Name Address Description Reset Value Physical 8-bit Area CC2_CC21IC F16A ESFR CAPCOM Register 21 Interrupt 0000 Control Register CC2_CC22IC F16C ESFR CAPCOM Register 22 Interrupt...
Page 404 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-1 PD+BUS Register Listing (cont’d) Short Name Address Description Reset Value Physical 8-bit Area CAN_0IC F196 ESFR TwinCAN Interrupt Control 0000 Register 0 CAN_1IC F142 ESFR TwinCAN Interrupt Control...
Page 405 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-1 PD+BUS Register Listing (cont’d) Short Name Address Description Reset Value Physical 8-bit Area DP0L F100 ESFR P0L Direction Control Register 0000 DP0H F102 ESFR P0H Direction Control Register...
Page 406 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-1 PD+BUS Register Listing (cont’d) Short Name Address Description Reset Value Physical 8-bit Area FFD2 P7 Direction Control Register 0000 ODP7 F1D2 ESFR P7 Open Drain Control Register 0000...
Page 407: Lxbus Peripherals
XC161 Derivatives Peripheral Units (Vol. 2 of 2) Register Set 23.2 LXBUS Peripherals Note: The address space for LXBUS peripherals is assigned to Segment 32; it may be changed by user SW. Table 23-2 LXBUS Register Listing Short Name Physical...
Page 408 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-2 LXBUS Register Listing (cont’d) Short Name Physical Description Reset Address Value CAN_BECNTL 20’0260 Node B Error Counter Register Low 0000 CAN_BECNTH 20’0262 Node B Error Counter Register High...
Page 409 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-3 Base Address of Message Objects (cont’d) Message Object Number Base Address Message Object 9 20’0420 Message Object 10 20’0440 Message Object 11 20’0460 Message Object 12 20’0480 Message Object 13 20’04A0...
Page 410 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Register Set Table 23-4 Offset Address of Message Object Registers Short Name Offset Description Reset Address Value CAN_ Message Object n Data Register 0 Low 0000 MSGDRLn0 CAN_ Message Object n Data Register 0 High...
Page 411: Keyword Index
Keyword Index Keyword Index This section lists a number of keywords which refer to specific details of the XC161 in terms of its architecture, its functional units or functions. This helps to quickly find the answer to specific questions about the XC161.
Page 412 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Keyword Index Configuration 6-19 [1] Clock Calibration 16-17 [2] generation 2-29 [1] generator modes 6-18 [1] acceptance filtering 21-16 [2] output signal 6-39 [1] analysing mode 21-7 [2] Command sequences arbitration 21-16 [2]...
Page 413 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Keyword Index Data SRAM 3-9 [1] Bus 2-13 [1] Default startup configuration 6-23 [1] Fast interrupts 5-37 [1] Development Support 1-8 [1] Interrupt pulses 5-40 [1] Direction Interrupt source control 5-37 [1]...
Page 414 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Keyword Index Arbitration 5-4 [1] during sleep mode 5-39 [1] Hardware Enable/Disable 5-29 [1] Traps 5-43 [1] External 5-35 [1] Fast external 5-37 [1] input timing 5-40 [1] I2C 20-1 [2] Jump Table Cache 5-16 [1]...
Page 415 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Keyword Index Areas (Program) 3-10 [1] PEC pointers 3-7 [1] DPRAM 3-9 [1] PECCx 5-19 [1] DSRAM 3-9 [1] PECISNC 5-27 [1] External 3-14 [1] PECSEGx 5-23 [1] Flash 3-11 [1] Peripheral Program Flash 3-16 [1] Event Controller -->...
Page 416 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Keyword Index program/data 3-11 [1] IIC 2-26 [1], 20-1 [2] status after reset 6-7 [1] J1850 2-24 [1] Real Time Clock (->RTC) 2-20 [1], 15-1 [2] SDLM 22-1 [2] Register Areas 3-4 [1]...
Page 417 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Keyword Index T2, T3, T4 14-29 [2] initialization 21-40 [2] T2CON 14-15 [2] interrupts T2IC, T3IC, T4IC 14-30 [2] indication/INTID 21-13 [2], T3CON 14-4 [2] 21-53 [2] T4CON 14-15 [2] node pointer/request compressor...
Page 418 XC161 Derivatives Peripheral Units (Vol. 2 of 2) Keyword Index interrupt pending 21-53 [2] MSGDRL0 21-64 [2] INTID mask 21-62 [2] MSGDRL4 21-65 [2] status 21-51 [2] MSGFGCRHn 21-74 [2] single transmission 21-45 [2] MSGFGCRLn 21-74 [2] single-shot mode 21-23 [2]...
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Infineon Technologies XC161 User Manual

13 Device Specification

The General Purpose Timer Units

Table of Contents

Real Time Clock

The Analog/Digital Converter

Capture/Compare Units

Table of Contents

Asynchronous/Synchronous Serial Interface (ASC)

High-Speed Synchronous Serial Interface (SSC)

Table of Contents

IIC-Bus Module

Twincan Module

Table of Contents

Serial Data Link Module SDLM

Table of Contents

Register Set

Keyword Index

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Summary of Contents for Infineon Technologies XC161