Infineon Technologies XC161 Manuals

Manuals and User Guides for Infineon Technologies XC161. We have 1 Infineon Technologies XC161 manual available for free PDF download: User Manual

Infineon Technologies XC161 User Manual

Infineon Technologies XC161 User Manual (419 pages)

16-Bit Single-Chip Microcontroller with C166SV2 Core

Brand: Infineon Technologies | Category: Controller | Size: 5.82 MB

Table of Contents

Table of Contents
9
13 Device Specification

15
The General Purpose Timer Units

15
Table of Contents

53
Real Time Clock

70
- Defining the RTC Time Base
  71
- RTC Run Control
  74
- RTC Operating Modes
  76
- 48-Bit Timer Operation
  79
- System Clock Operation
  79
- Cyclic Interrupt Generation
  80
- RTC Interrupt Generation
  81
The Analog/Digital Converter

83
- Mode Selection
  85
- Compatibility Mode
  85
- Enhanced Mode
  87
- ADC Operation
  90
- Fixed Channel Conversion Modes
  93
- Auto Scan Conversion Modes
  94
- Wait for Read Mode
  95
- Channel Injection Mode
  96
- Automatic Calibration
  99
- Conversion Timing Control
  100
- A/D Converter Interrupt Control
  103
- Interfaces of the ADC Module
  104
Capture/Compare Units

105
- The CAPCOM Timers
  108
- CAPCOM Timer Interrupts
  113
- Capture/Compare Channels
  114
- Capture Mode Operation
  117
- Compare Mode Operation
  118
- Compare Mode 0
  119
- Compare Mode 1
  119
- Compare Mode 2
  122
- Compare Mode 3
  122
- Double-Register Compare Mode
  126
- Compare Output Signal Generation
  129
- Single Event Operation
  131
Table of Contents

133
- Staggered and Non-Staggered Operation
  133
- CAPCOM Interrupts
  138
- External Input Signal Requirements
  140
- Interfaces of the CAPCOM Units
  141
Asynchronous/Synchronous Serial Interface (ASC)

144
- Operational Overview
  146
- Asynchronous Operation
  148
- Asynchronous Data Frames
  149
- Asynchronous Transmission
  152
- Transmit FIFO Operation
  152
- Asynchronous Reception
  155
- Receive FIFO Operation
  155
- FIFO Transparent Mode
  158
- Irda Mode
  159
- Rxd/Txd Data Path Selection in Asynchronous Modes
  160
- Synchronous Operation
  162
- Synchronous Transmission
  163
- Synchronous Reception
  163
- Synchronous Timing
  163
- Baudrate Generation
  165
- Baudrate in Asynchronous Mode
  165
- Baudrate in Synchronous Mode
  169
- Autobaud Detection
  170
- General Operation
  170
- Serial Frames for Autobaud Detection
  171
- Baudrate Selection and Calculation
  172
- Overwriting Registers on Successful Autobaud Detection
  176
- Hardware Error Detection Capabilities
  177
- Interrupts
  178
- Registers
  182
- Interfaces of the ASC Modules
  199
High-Speed Synchronous Serial Interface (SSC)

201
- Introduction
  201
- Operational Overview
  201
- Operating Mode Selection
  203
- Full-Duplex Operation
  208
- Half-Duplex Operation
  211
- Continuous Transfers
  212
- Baudrate Generation
  212
- Error Detection Mechanisms
  214
- SSC Register Summary
  216
Table of Contents

217
- Port Configuration Requirements
  217
- Interfaces of the SSC Modules
  218
IIC-Bus Module

219
- Overview
  220
- Register Description
  223
- IIC-Bus Module Operation
  230
- Operation in Single-Master Mode
  230
- Operation in Multimaster Mode
  230
- Operation in Slave Mode
  231
- Transmit/Receive Buffer
  232
- Baud Rate Generation
  233
- Notes for Programming the IIC-Bus Module
  234
- Interrupt Request Operation
  235
- Port Connection and Configuration
  237
- Interfaces of the IIC-Bus Module
  239
- IIC-Bus Overview
  240
Twincan Module

241
- Kernel Description
  241
- Overview
  241
- Twincan Control Shell
  244
- Initialization Processing
  244
- Interrupt Request Compressor
  245
- Global Control and Status Logic
  246
- CAN Node Control Logic
  247
- Overview
  247
- Timing Control Unit
  249
- Bitstream Processor
  251
- Error Handling Logic
  251
- Node Interrupt Processing
  252
- Message Interrupt Processing
  253
- Interrupt Indication
  253
- Message Handling Unit
  255
- Arbitration and Acceptance Mask Register
  256
- Handling of Remote and Data Frames
  257
- Handling of Transmit Message Objects
  258
- Handling of Receive Message Objects
  261
- Single Data Transfer Mode
  263
- CAN Message Object Buffer (FIFO)
  264
- Buffer Access by the CAN Controller
  266
- Buffer Access by the CPU
  267
- Gateway Message Handling
  268
Table of Contents

269
- Normal Gateway Mode
  269
- Normal Gateway with FIFO Buffering
  273
- Shared Gateway Mode
  276
- Programming the Twincan Module
  280
- Configuration of CAN Node A/B
  280
- Initialization of Message Objects
  280
- Controlling a Message Transfer
  281
- Loop-Back Mode
  284
- Single Transmission Try Functionality
  285
- Module Clock Requirements
  286
- Twincan Register Description
  287
- Register Map
  287
- CAN Node A/B Registers
  289
- CAN Message Object Registers
  304
- Global CAN Control/Status Registers
  320
- XC161 Module Implementation Details
  322
- Interfaces of the Twincan Module
  322
- Twincan Module Related External Registers
  323
- System Registers
  324
- Port Registers
  325
- Interrupt Registers
  330
- Register Table
  331
Serial Data Link Module SDLM

332
- Overview
  332
- SDLM Kernel Description
  333
- J1850 Concept
  333
- Frame Format Basics
  334
- J1850 Bits and Symbols
  336
- Frame Arbitration
  337
- Block Diagram
  337
- Mode
  339
- Break Operation
  339
- Interrupt Handling
  340
- Message Operating Mode
  341
- Receive Operation
  341
- Transmit Operation
  342
- In-Frame Response (IFR) Operation
  343
- Block Mode
  344
- Bus Access in FIFO Mode
  346
- Flowcharts
  347
- Overview
  347
- Transmission Control
  348
Table of Contents

351
- Read Operations
  351
- IFR Handling
  353
- IFR Types 1, 2 Via IFRVAL
  353
- SDLM Register Description
  354
- Global Control and Timing Registers
  355
- Control and Status Registers
  360
- Transmission Related Registers
  370
- Reception Related Registers
  374
- SDLM Module Register Table
  381
- XC161 Module Implementation Details
  382
- Interfaces of the SDLM Module
  382
- SDLM Module Related External Registers
  384
- System Registers
  385
- Port Registers
  386
- Interrupt Registers
  391
Register Set

392
- PD+BUS Peripherals
  392
- LXBUS Peripherals
  407
Keyword Index

411

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