ITech IT6322 Manual page 10

Structure of condition register as following:
condition event
CAL CAL
UNR UNR
CV CV
CC CC
Operation status sub register(channel 1)
condition event
INST1 INST1
INST2 INST2
INST3 INST3
Operation status register
condition event
OPC OPC
QYE QYE
DDE DDE
EXE EXE
CME CME
PON PON
Standard event register
condition event
OV OV
OT OT
Quest condition register
enable condition
CAL CAL
UNR UNR
or
CV CC
CC CV
Operation status sub register(channel 2)
enable
INST1
INST2
o
INST3
r
enable
OPC
QYE
or
DDE
EXE
CME
PON
enable
OV
OT
or
event enable
CAL CAL
UNR UNR
o
CC CC
r
CV CV
Operation status sub register(channel 3)
event
QUES
ESB
RQS
OPER
Status byte register
Note:
The bit array of each
register is as right
table:
10
condition event enable
CAL CAL CAL
UNR UNR UN
R
CV CV CV
CC CC CC
enable
or
QUES
ESB
RQS
OPER
Lowest bit: 0
First bit: 1
Second bit: 2
Third bit: 3
Forth bit: 4
Fifth bit: 5
Sixth bit: 6
Highest bit: 7
o
r