.
1st
VCO
Receive frequency
[MHz]
VCO
select
signal
VCO
components
VCO
frequency
[MHz]
0.5-
199.9999
VII
Q621, Q622,
D621
429.6
-
629.0999
200.0-
533.2999
V12
Q641, D641
629.1
-
799.9999
533.3
-
609.9999
V13
Q661, D661,
D662
800.0
-
876.6999
610.0-
895.7999
VII
Q621.Q622,
D621
343.3
-
629.0999
895.8-
999.9999
V12
Q641, D641
629.1
-733.2999
1000.0-1058.1999
VII
0621,0622,
D621
570.9
-
629.0999
1058.2-1229.0999
V12
0641, D641
629.1
-799.9999
1229.1
-
1300.0000
V13
0661, D661,
D662
800.0-
870.9000
4-2-5
2ND LO
PLL CIRCUIT
(MAIN
UNIT)
The
2ND
LO
PLL
circuit
generates
the
2nd
LO
frequency
for
the
main band
(receive
signal)
and sub-band
(band
scope
and
SIGNAVI
functions).
Signals from the
2ND
VCO
unit
pass
through the
buffer
amplifier
(0531
for
main
band,
0551
for
the
sub-band)
and
are applied
to
the
PLL
1C
(IC501;
pin 2
and
pin
19
respectively)
and
prescaled
in
the
PLL
1C
based on
the
divided
ratio
(N-data).
The PLL
1C detects the out-of-step
phase
using the reference
frequency
and
outputs
it
from
pins
8
and
13.
The
output
signal
from
pin
8
is
passed
through
the loop
filter
(R51
1
,
R51
2,
R51
4,
C51
1
,
C51
2),
and
is
then applied
to
the
2ND
VCO
circuit for
the
main
band
(2ND
VCO
unit)
via
the 21
LV
terminal
(2ND
VCO
unit;
J601)
as
the lock
voltage.
The
output
signal
from
pin
13
is
passed
through the
loop
filter
(R521-R523, C521,
C522),
and
is
then applied
to
the
2ND
VCO
circuit for
the
sub-band
(2ND
VCO
unit)
via
the
22LV
terminal
(2ND
VCO
unit;
J601
)
as
the
lock voltage.
band
(0411)
after
being
amplified
at
the
buffer amplifier
(0552).
The
switching
transistors
(0601
and 0701)
shift
the
oscillating
frequencies
via
the "IFH"
signal
from
the
RF
unit.
4-3
POWER
SUPPLY
CIRCUITS
VOLTAGE
LINE (LOGIC UNIT)
Line
Description
HV
The
voltage
coming
from
the external
DC
jack.
VCC
The same
voltage
as
the
installed
battery
cells
or
HV
line
passed
through the
charge
control
circuit
(Q101.D104).
+3CPU
Common
3
V
for
the
CPU
(ICl)
produced
at
the
+3CPU
regulator 1C (IC81).
The
circuit
outputs
the voltage regardless
of
the
power
ON/OFF
condition.
+3S
Common
3
V
converted from the
VCC
line
by
the
+3S
regulator
circuit
(Q121,
Q122)
using a
control signal
(+3SC) from
the
CPU.
+3C
Common
3
V
converted from the
VCC
line
by
the
+3C
regulator
circuit
(Q111,
Q112)
using a
control signal
(3LCON)
from
the
CPU.
+3L
Common
3
V
converted from
the
VCC
line
by
the
+3L
regulator
circuit
(Q91
,
Q92)
using
a
control
signal
(3LCON)
from the
CPU.
+15
Common
15
V
converted from
the
+3L
line
by
the
DC-DC
convertor iC
(ICl 51).
4-2-6
VXO
CIRCUIT (MAIN
UNIT)
The
VXO
(Variable Crystal
Oscillator)
circuit
(IC501,
X501
and D501)
generates
a
12.8
MHz
2nd
reference frequency.
The 2nd
reference frequency
is
stabilized within
the
temperature range
-10°C
(+14°F)
to
+50°C
(+122°F).
For
tuning the
100
Hz
frequency
step,
the
VXO
circuit
changes
the capacitance
of
a
varactor
diode (D501
)
via
the voltage
of
the
"VXO"
line
from
the
CPU
(LOGIC
unit;
IC1),
and
controls
the
2nd
reference frequency.
4-2-7
2ND
VCO
CIRCUIT (2ND
VCO
UNIT)
The
2ND
VCO
unit
contains
two
VCO
circuits
for
the
main
band and
sub-band.
The
VCO
circuit
for
the
main
band
consists
of
0602,
0604
and D601
,
and
the
VCO
circuit
for
the
sub-band
consists
of
Q702,
0704
and D701. The
oscillated signal
is
amplified
at
the
buffer amplifiers
(0603
for
the
main
band,
0703
for
the sub-band).
Then
the
2nd
LO
signal
for
the
main band
is
applied
to
the
2nd
mixer
(ICl
1
,
pin 3) via
the
buffer amplifier
(0532),
and
the
2nd
LO
signal
for
the
sub-band
is
input to
the
2nd
mixer
for
the sub-
4-5
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