Pll Circuits - Icom IC-R10 Service Manual

4-1-11
AGC
CIRCUIT (MAIN UNIT)
The
AGC
(Auto
Gain
Control)
circuit
reduces IF/RF amplifier
gain
to
keep the audio output
at
a constant
level.
The
receiver gain
is
determined by the voltage on the
IF-AGC
line
(Q182
collector)
and
RF-AGC
line
(RF
unit;
Q901
collector).
The
3rd
IF
signals
from
the 3rd IF
amplifier (Q161) are
detected
at
the
AM
detector (Q171).
A
portion of
the
detected
signals
is
applied
to
the
AGC
amplifiers
(Q182 and
RF
unit;
Q901) as the
AGC
control voltage.
The
AM
detector (Q171)
is
used
for
the
AGC
detector
in
the
AGC
circuit.
When
receiving strong signals,
the detected voltage
increases
and
the
AGC
voltage
decreases
via
the
AGC
amplifiers
(Q182 and
RF
unit;
Q901).
As
the
AGC
voltage
is
used
for
the bias voltage
of
the IF/RF amplifiers,
IF/RF
amplifier
gain
is
decreased.
4-1-12
NOISE
BLANKER
CIRCUIT (MAIN UNIT)
The
noise blanker
circuit
detects pulse-type noise,
and
stops
IF
amplifier
operation during detection.
A
portion of
the
2nd
IF
signals
from
the
2nd
IF
amplifier for
the
sub-band (Q421)
is
amplified
at
the noise amplifier
circuit
(Q801, Q802).
The
amplified signal
is
recified at
the
noise detector
circuit
(Q805)
for
conversion
into
DC
voltage.
The
DC
voltage
is
applied
to
the
NB
control circuit
(Q806,
Q807) to control the
NB
switch (Q810).
Some
DC
voltage
is
fed
back
to
the noise amplifier circuit
(Q801
,
Q802)
via
the
DC
amplifier (Q808).
The
DC
amplifier
functions
as an
AGC
circuit to
reduce averaged
noise.
Therefore, the noise blanker function
shuts
off
pulse-type
noise
only.
4-2
PLL CIRCUITS
4-2-1
GENERAL
1ST/2ND LO PLL
circuits
(RF/MAIN
units)
provide stable
oscillation of
the receive
LO
frequencies.
The PLL
circuit
consists
of
the
PLL
1C
(IC501
on
the
RF/MAIN
units),
charge
pump,
loop
filter
and
reference oscillator
and
employs a
pulse
swallow counter.
4-2-2
1ST
LO PLL CIRCUIT
(RF UNIT)
Signals from the
1ST
VCO
unit
pass through the
buffer
amplifier
(Q551) and are prescaled
in
the
PLL
1C (IC501,
pin 10)
based on
the divided ratio
(N-data).
The PLL
1C
detects the out-of-step
phase using the reference
frequency
and
outputs
it
from
pin 6.
The
output signal
is
passed
through the
charge
pump
(Q521
,
Q522) and
is
applied
to
the loop
filter
(R527,
C527)
to
be converted
into
DC
voltage
as a
PLL
lock voltage.
The PLL
lock
voltage
is
applied
to
the
1
ST
VCO
unit
via the
VI
L
line.
A
portion of
the signal from the loop
filter
(R527,
C527)
is
amplified
at
the
buffer amplifier (Q502)
and
is
then applied
to
the
CPU
(LOGIC
unit;
IC1) as the lock
voltage
information (LVI).
The
CPU
(pin 6)
outputs
a
"TUNE"
signal
based on the lock voltage; the voltage
is
amplified
at
the
buffer amplifiers
(LOGIC
unit;
Q181, 0182) and
is
then
applied
to
the
RF
unit
as the tunable
bandpass
filter
control
signal
(VTUNE).
This signal
(VTUNE)
is
used
for
the
RF
tunable
bandpass
filters to
match
the
filter's
center
frequency
to
the desired receive frequency.
4-2-3
REFERENCE OSCILLATOR CIRCUIT
(RF UNIT)
The
reference oscillator circuit
(X501, IC501) generates a
10.245
MHz
reference
frequency which
is
stabilized within
the
temperature range
-10°C (+14T)
to
+50°C
(+122°F).
The
reference
frequency
is
applied
to
the
PLL
1C
and
also
applied
to
the
MAIN
unit
as the 3rd
LO
signal via the buffer
amplifier (0531).
4-2-4
1ST
VCO
CIRCUIT
(1ST
VCO
UNIT)
The 1ST
VCO
circuit
contains three
separate
VCO
circuits
depending on
the receive frequency.
The
oscillated signal
at
one
of
the three
VCO
circuits
is
applied
to
the buffer
amplifier (0601).
The
amplified signal
is
applied to
the
RF
unit
via
the VI
O
line
and
is
then
applied
to
the
1st
mixer
circuit
(RF
unit;
IC271,
pin
3
)
as the
1st
LO
signal after
being amplified
at
the buffer amplifier
(RF
unit;
0552).
A
portion of
the signal from the
VI
O
terminal
(1ST
VCO
unit;
J601)
is
amplified
at
the buffer amplifier (0551)
and
is
then
fed
back
to
the
PLL
1C
(IC501,
pin 10)
as the
comparison
signal.
•
1st
LO PLL
circuit
(RF
unit)
4-4