Chipset Features Setup Menu - Leadtek WinFast 6000ABX User Manual

4-4 Chipset Features Setup Menu

This section allows you to configure the system based on the specific features of the installed
chipset. This chipset manages bus speeds and access to system memory resources, such as
DRAM and the external cache. It also coordinates communications between the conventional
ISA bus and the PCI bus. It must be stated that these items should never need to be altered. The
default settings have been chosen because they provide the best operating conditions for your
system. The only time you might consider making any changes would be if you discovered that
data was being lost while using your system.
ROM PCI/ISA BIOS (6000ABX) ROM PCI/ISA BIOS (6000ABX)
ROM PCI/ISA BIOS (6000ABX) ROM PCI/ISA BIOS (6000ABX)
SDRAM TRCD SDRAM TRCD / / / / TRP TRP of DIMM0: : : : 3/3 CLKs of DIMM0
SDRAM TRCD SDRAM TRCD TRP TRP of DIMM0 of DIMM0
SDRAM CAS Latency of DIMM SDRAM CAS Latency of SDRAM CAS Latency of SDRAM CAS Latency of DIMM0 0 0 0 : : : : 3 3 3 3 clocks DIMM DIMM
SDRAM TRCD / / / / TRP SDRAM TRCD SDRAM TRCD SDRAM TRCD TRP TRP TRP of DIMM1: : : : 3/3 CLKs of DIMM1 of DIMM1 of DIMM1
SDRAM CAS Latency of DIMM1 SDRAM CAS Latency of DIMM1: : : : 3 3 3 3 clocks
SDRAM CAS Latency of SDRAM CAS Latency of DIMM1 DIMM1
SDRAM TRCD / / / / TRP SDRAM TRCD SDRAM TRCD SDRAM TRCD TRP TRP TRP of DIMM2 2 2 2 : : : : 3/3 CLKs of DIMM of DIMM of DIMM
SDRAM CAS Latency of DIMM2 SDRAM CAS Latency of DIMM2: : : : 3 3 3 3 clocks
SDRAM CAS Latency of SDRAM CAS Latency of DIMM2 DIMM2
Auto Configuration Auto Configuration
Auto Configuration Auto Configuration
AT Bus Clock AT Bus Clock AT Bus Clock AT Bus Clock
ECC/EC Option ECC/EC Option
ECC/EC Option ECC/EC Option
Local In Local In Local In Local In- - - - Order Order Order- - - - Queue Depth: 1 Order Queue Depth: 1 Queue Depth: 1 Queue Depth: 1
Passive_Release_Feature Passive_Release_Feature Passive_Release_Feature Passive_Release_Feature
DRAM Data Integrity Mode DRAM Data Integrity Mode
DRAM Data Integrity Mode DRAM Data Integrity Mode
ISA Line Buffer ISA Line Buffer ISA Line Buffer ISA Line Buffer
I/O Recovery Period I/O Recovery Period
I/O Recovery Period I/O Recovery Period
System BIOS Cacheable System BIOS Cacheable
System BIOS Cacheable System BIOS Cacheable
VGA Frame Buffer VGA Frame Buffer VGA Frame Buffer VGA Frame Buffer
Video BIOS Cach Video BIOS Cacheable eable
Video BIOS Cach Video BIOS Cach eable eable
Video RAM Cacheable Video RAM Cacheable Video RAM Cacheable Video RAM Cacheable
AGP 2x Mode support AGP 2x Mode support AGP 2x Mode support AGP 2x Mode support
SDRAM TRCD / TRP of DIMM0/DIMM1/DIMM2
TRCD ( RAS to CAS Delay): When DRAM is refreshed, both rows and columns are addressed
separately. This setup item allows you to determine the timing of the transition from RAS (row
address strobe) to CAS (column address strobe).
TRP (RAS Precharge Time): The precharge time is the number of cycles it takes for the RAS
to accumulate its charge before DRAM refreshes. If insufficient time is allowed, refresh may be
incomplete and the DRAM may fail to retain data.
SDRAM CAS Latency of DIMM0/DIMM1/DIMM2
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends on
the DRAM timing. Do not reset this field from the default value specified by the system
.
designer
The Choice: 2 clocks, 3 clocks.
Auto Configuration
Auto Configuration selects predetermined optimal values of chipset parameters. When Disabled,
chipset parameters revert to setup information stored in CMOS. Many fields in this screen are
not available when Auto Configuration is Enabled.
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WinFast 6000ABX User's Manual
C C C C HIPSET FEATURES HIPSET FEATURES SETUP SETUP
HIPSET FEATURES HIPSET FEATURES SETUP SETUP
AWARD SOFTWARE, INC. AWARD SOFTWARE, INC. AWARD SOFTWARE, INC. AWARD SOFTWARE, INC.
3/3 CLKs AGP Aperture Size (MB) AGP Aperture Size (MB)
3/3 CLKs 3/3 CLKs AGP Aperture Size (MB) AGP Aperture Size (MB)
clocks clocks clocks Memory Hole 15M- - - - 16M Memory Hole 15M Memory Hole 15M Memory Hole 15M
3/3 CLKs 3/3 CLKs 3/3 CLKs Spread Spectrum Spread Spectrum Spread Spectrum Spread Spectrum
clocks CPU Host Clock (CPU/PCI): Default CPU Host Clock (
clocks clocks CPU Host Clock ( CPU Host Clock (
3/3 CLKs 3/3 CLKs 3/3 CLKs SDRAM Loading SDRAM Loading SDRAM Loading SDRAM Loading
clocks
clocks clocks
: Disabled : Disabled
: Disabled : Disabled
: 7.16MHz : 7.16MHz : 7.16MHz : 7.16MHz
: No ECC/EC : No ECC/EC
: No ECC/EC : No ECC/EC
: Disabled : Disabled : Disabled : Disabled
: Disabled : Disabled
: Disabled : Disabled
ESC : Quit ESC : Quit
: Disabled : Disabled : Disabled : Disabled ESC : Quit ESC : Quit
: 1 us : 1 us F1 F1 F1 F1 : Help : Help : Help : Help
: 1 us : 1 us
: Disabled : Disabled F5 F5 F5 F5 : Old Values : Old Values : Old Values : Old Values
: Disabled : Disabled
: Disabled : Disabled : Disabled : Disabled F6 F6 F6 F6 : Load Basic : Load Basic : Load Basic : Load Basic
: Disabled : Disabled F7 F7 F7 F7 : Load Best Defaults : Load Best Defaults : Load Best Defaults : Load Best Defaults
: Disabled : Disabled
: Disabled : Disabled : Disabled : Disabled
: Disabled : Disabled : Disabled : Disabled
: : 16 MB 16 MB
: : 16 MB 16 MB
16M 16M 16M : Disabled : Disabled : Disabled : Disabled
: Disabled : Disabled : Disabled : Disabled
CPU/PCI): Default
CPU/PCI): Default CPU/PCI): Default
: Light : Light : Light : Light
↑↓← ↑↓← → → → → : Select Item : Select Item
↑↓← ↑↓← : Select Item : Select Item
PU/PD/+/ PU/PD/+/ PU/PD/+/ PU/PD/+/- - - - : Modify : Modify : Modify : Modify
(Shift)F2 : Color (Shift)F2 : Color (Shift)F2 : Color (Shift)F2 : Color
Defaults Defaults Defaults Defaults
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