Denon ADV-1000 Service Manual page 37

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AK4527BVQ (MA: IC721)
AK4527BVQ Terminal Function
Pin
Port Name
No.
1 SDOS
2 I2C
3 SMUTE
4 BICK
5 LRCK
6 SDTI1
7 SDTI2
8 SDTI3
TE
L 13942296513
9 SDTO
10 DAUX
11 DFS
12 NC
13 DZFE
14 TVDD
15 DVDD
16 DVss
17 PDN
18 TST
19 NC
20 ADIF
21 CAD1
22 CAD0
23 LOUT3
24 ROUT3
25 LOUT2
26 ROUT2
27 LOUT1
28 ROUT1
29 LIN-
30 LIN+
31 RIN-
32 RIN+
33 DZF2/OVF
34 VCOM
35 VREFH
36 AVDD
37 AVss
38 DZF1
www
39 MCLK
40 P/S
DIF0
41
CSN
DIF1
.
42
SCL/CCLK
LOOP0
43
SDA/CDTI
44 LOOP1
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SDOS 1
I2C 2
SMUTE 3
BICK 4
LRCK 5
SDTI1 6
SDTI2 7
SDTI3 8
SDTO 9
DAUX 10
DFS 11
I/O
I SDTO source select pin, L: Internal ADC output, H: DAUX input
I Serial control mode select pin, L: 3-core serial, H: I
I Soft mute pin, H: Soft mute start, L: Release
I Audio serial data clock pin
I Input channel clock pin
I DAC1 audio serial data input pin
I DAC2 audio serial data input pin
I DAC3 audio serial data input pin
O Audio serial data output pin
I Auxiliary audio serial data input pin
I Double speed sampling mode pin, L: Normal, H: Double

No connection
I Zero input detect function activate pin, L: Mode 7 at parallel, H: Mode 0

Power pin for output buffer, 2.7V~5.5V

Digital power pin, 4.5V~5.5V

Digital GND pin, 0V
I Power down & reset pin, L: Powered-down and register initialized, Reset with PDN when switching CAD0-1
I Test pin, connect to DVSS

No connection
I Analog input type select pin, H: Differential, L: Single-end
I Chip address-1 pin
I Chip address-0 pin
O DAC3L channel analog out pin
O DAC3R channel analog out pin
O DAC2L channel analog out pin
O DAC2R channel analog out pin
O DAC1L channel analog out pin
O DAC1R channel analog out pin
I L-ch analog inverted input pin
I L-ch analog non-inverted input pin
I R-ch analog inverted input pin
I R-ch analog non-inverted input pin
O 0 input detect 2 pin, H: Input data of G2 is 8192 times "0" in a raw or RSTN bit "0", L: When P/S= "0" /Analog input overflow detect pin
O Common V-out pin, AVDD/2, connect large capacitor to avoid noise
I Ref. V input pin, AVDD

Analog GND pin, 4.5V~5.5V

Analog GND pin, 0V
O 0 input detect pin, H: Input data of G1 is 8192 times "0" in a raw or RSTN bit "0", L: When P/S= "0"
I Master clock input pin
I Parallel/Serial select pin, L: Serial control
x ao
I Audio data I/F format 0 pin (parallel control)
y
I Chip select pin (3-wire serial control), connect to DVDD when I
I Audio data I/F format 1 pin (parallel control)
i
I Control data clock pin (serial control), I
I Loop back mode 0 pin (parallel control), effects digital loop back ADC to all DAC
I/O Control data input pin (serial control), I
I Loop back mode 1 pin, from SDT1 to all DAC
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8
33
32
31
30
AK4527BVQ
29
28
Top View
27
26
25
24
23
Function
2 C bus
Q Q
3 6 7 1 3
u163
2
C bus control
.
2 C="L": CCLK (3-wire serial), I 2
2
C="L": CCTI (3-wire serial), I2C="H" SDA (I
2 9 9 4 2 8
DZF2/OVF
RIN+
RIN-
LIN+
LIN-
ROUT1
LOUT1
ROUT2
LOUT2
ROUT3
LOUT3
1 5 0 5 8 2 9 9 4
m
co
C="H": SCL (I 2 C bus)
2
C bus)
ADV-1000
9 9
2 8 9 9
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