Denon ADV-1000 Service Manual page 28

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3 7 63 1515 0
16M SDRAM (TSOP)-8 (DM: IC103, 104)
K4S161622D-TC80
W981616AH-8
Terminal Function
Pin No. Pin Name
1 V
DD
2 DQ
0
3 DQ
1
4 V
SSQ
5 DQ
2
6 DQ
3
7 V
DDQ
8 DQ
4
9 DQ
5
10 V
SSQ
11 DQ
6
12 DQ
7
TE
L 13942296513
13 V
DDQ
14 L DQM
15 WE
16 CAS
17 RAS
18 CS
19 BA
20 A /AP
10
21 A
0
22 A
1
23 A
2
24 A
3
25 V
DD
26 V
SS
27 A
4
28 A
5
29 A
6
30 A
7
31 A
8
32 A
9
33 N. C
34 CKE
35 CLK
36 U DQM
37 N. C/RFU
38 V
DDQ
39 DQ
8
40 DQ
9
41 V
SSQ
42 DQ
10
www
43 DQ
11
44 V
DDQ
45 DQ
12
46 DQ
13
.
47 V
SSQ
48 DQ
14
49 DQ
15
50 V
SS
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Symbol
Power Supply/Ground Power and ground for the input buffer and the core logic
Data Input/Output Data input/output are mutiplexed on the same pin
Data Input/Output Data input/output are mutiplexed on the same pin
Data Output Power/Ground Isolated power supply and ground for the output buffer
Data Input/Output Data input/output are mutiplexed on the same pin
Data Input/Output Data input/output are mutiplexed on the same pin
Data Output Power/Ground Isolated power supply and ground for the output buffer
Data Input/Output Data input/output are mutiplexed on the same pin
Data Input/Output Data input/output are mutiplexed on the same pin
Data Output Power/Ground Isolated power supply and ground for the output buffer
Data Input/Output Data input/output are multiplexed on the same pin
Data Input/Output Data input/output are multiplexed on the same pin
Data Output Power/Ground Isolated power supply and ground for the output buffer
Data Input/Output Mask Blocks data input when active
Write Enable Enables write operation and row precharge
Column Address Strobe Latches column address on the positive going edge of the CLK at low
Row Address Strobe Latches row address on the positive going edge of the CLK at low
Disables or enables device operation by masking or enabling all
Chip Select
inputs except CLK, CKE, and LDQM
Bank Select Address Selects bank to be activated during row address latch time
Address Row/column addresses are multiplexed on the same pin
Address Row/column addresses are multiplexed on the same pin
Address Row/column addresses are multiplexed on the same pin
Address Row/column addresses are multiplexed on the same pin
Address Row/column addresses are multiplexed on the same pin
Power Supply/Ground Power and ground for the input buffer and the core logic
Power Supply/Ground Power and ground for the input buffer and the core logic
Address Row/column addresses are multiplexed on the same pin
Address Row/column addresses are multiplexed on the same pin
Address Row/column addresses are multiplexed on the same pin
Address Row/column addresses are multiplexed on the same pin
Address Row/column addresses are multiplexed on the same pin
Address Row/column addresses are multiplexed on the same pin
No Connection No connect pin
Clock Enable Masks system clock to freeze operation from the next clock cycle
System Clock Active on the positive going edge to sample all inputs
Data Input/Output Mask Blocks data input when active
NC/Reserved No connect pin
Data Output Power/Ground Isolated power supply and ground for the output buffer
Data Input/Output Data input/output are multiplexed on the same pin
Data Input/Output Data input/output are multiplexed on the same pin
Data Output Power/Ground Isolated power supply and ground for the output buffer
Data Input/Output Data input/output are multiplexed on the same pin
Data Input/Output Data input/output are multiplexed on the same pin
Data Output Power/Ground Isolated power supply and ground for the output buffer
x ao
y
Data Input/Output Data input/output are multiplexed on the same pin
Data Input/Output Data input/output are multiplexed on the same pin
i
Data Output Power/Ground Isolated power supply and ground for the output buffer
Data Input/Output Data input/output are multiplexed on the same pin
Data Input/Output Data input/output are multiplexed on the same pin
Power Supply/Ground Power and ground for the input buffer and the core logic
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2 9 9 4 2 8
Function
1 5 0 5 8 2 9 9 4
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ADV-1000
9 9
2 8 9 9
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