Denon ADV-1000 Service Manual page 22
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Also See for ADV-1000:
- Operating instructions manual (172 pages) ,
- Specifications (2 pages) ,
- Operating instructions manual (95 pages)
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Pin
Port Name
No.
72
D14/P16
73
D13/P15
74
D12/P14
75
D11/P13
76
D10/P12
77
D9/P11
78
D8/P10
79
D7/P07
80
D6/P06
81
D5/P05
82
D4/P04
83
D3/P03
84
D2/P02
85
D1/P01
86
D0/P00
87
P107
88
P106
89
P105
90
P104
91
P103
92
P102
93
P101
94
AVSS
95
P100
96
VREF
TE
L 13942296513
97
AVCC
98
P96
99
P97
100
P95
LC72720NM (MA: IC511)
1
24
VREF
2
MPXIN
23
3
22
Vdda
4
21
Vssa
5
FLOUT
20
6
19
COIN
7
18
T1
8
17
T2
9
16
T3
10
15
T4
11
14
T5
12
13
XOUT
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Symbol
89055 CSFLAG
REMOTE
/SYR
INTREQ IN
4932 CE
4932 RST
4527 CE
ROM/RAM
ROM2
ROM3
ROM30
ERR MUTE
SEL CLK
4527 RST
89055 CE
96 DET
89055 ERR
89055 RST
P .ON/OFF
AAC
MODE1
KEY 0
(VSS)
KEY 1
(VCC)
(VCC)
89055 DO, 4932 DO
89055 DIN, 4527 DIN, 4932 DIN
89055 CLK, 4527 CLK, 4932 CLK
3
4
SYR
REFERENCE
CE
1
VOLTAGE
SC-BANDPASS
D1
FILTER
ANTI-
(57kHz)
CL
ALIASING
2
FILTER
D0
RDS-1D
SYNC
8
T7
7
T6
Vddd
Vssd
26 BIT SHIFT
XIN
REGISTER x 2
18
16
SYNDROME REGISTER
AND ERROR CORRECTION
17
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y
SOFT DECISION
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2 9
8
Signal change detect input from DIR
IR remote control input
Reset output to RDS IC of tuner
Open drain operation (L: output, H: switch to input)
Serial comm. chip enable output to surround DSP
Reset output to surround DSP
Serial comm. chip enable output to CODEC(AD/DA)
ROM/RAM used surround DSP select output
ROM address used surround DSP select output
ROM address used surround DSP select output
ROM address used surround DSP select output
Digital mute output when error
Data clock select output
Reset output to CODEC
Serial comm. enable output to DIR
96kHz sampling signal detect input from DIR
Error input from DIR
Reset output to DIR
Whole unit's power ON/OFF (standby) output
AAC function on/off select input
Unit's operation spec select input
Button operation detect input
GND
Button operation detect input
Ref. V input for A/D conversion
Q Q
3
6 7
1 3
1 5
Power supply
Serial data input from DIR/CODEC/DSP
Serial data output to DIR/CODEC/DSP
Serial clock output to DIR/CODEC/DSP
5
6
19
RDS
DETECTOR
COMPARATOR
SMOOTHING
FILTER
GROUP
AND
BUFFER RAM (24 BLOCK)
BLOCK
SYNC DET
DATA RAM
FRAG RAM
16 BIT
16 BIT
co
.
9 4
2 8
Function
0 5
8
2 9
9 4
15
14
ARI
BIPHASE
DIFFRENTIAL
S
DETECTOR
DECODER
DECODER
W
D (Ð 90°)
CLOCK
RECOVERY
(D-YCO)
D-PLL
PC
(D-YCO)
D (Ð 0 °)
TIMING
XTAL OSC
GENERATOR
AND
AND SYSTEM
DIVIDER
CONTROLLER
m
CCB
INTERFACE
PARALLEL TO SERIAL
POWER ON
RESET
ADV-1000
9 9
2 8
9 9
11
10
9
13
12
20
21
22
23
24
22
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