Denon ADV-1000 Service Manual page 26

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Pin No. Pin Name
56 DMA 3
57 DMA 4
58 DMA 5
59 Vcc
60 Vss
61 DMA 6
62 DMA 7
63 DMA 8
64 DMA 9
65 DMA 10
66 DMA 11
67 Vss
68 Vcc
69 DCAS#
DOE#
70
DSCK_EN
71 DWE#
72 DRAS 0#
73 DRAS 1#
74 DRAS 2#
75 Vcc
76 Vss
77 DB 0
78 DB 1
TE
L 13942296513
79 DB 2
80 DB 3
81 DB 4
82 DB 5
83 Vcc
84 Vss
85 DB 6
86 DB 7
87 DB 8
88 DB 9
89 DB 10
90 DB 11
91 Vss
92 Vcc
93 DB 12
94 DB 13
95 DB 14
96 DB 15
97 DCS 1#
98 Vss
99 Vcc
100 DCS 0#
101 DQM
www
102 DSCK
103 Vss
104 Vcc
.
105 DCLK
106 YUV 0
107 YUV 1
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I/O Function
O DRAM address bus
O DRAM address bus
O DRAM address bus
I 3.6V power supply
I GND
O DRAM address bus
O DRAM address bus
O DRAM address bus
O DRAM address bus
O DRAM address bus
O DRAM address bus
I GND
I 3.6V power supply
O Column address strobe, active low
O Output enable, active low
I Clock enable, active low
O DRAM write enable, active low
O Row address strobe, active low
O Row address strobe, active low
O Row address strobe, active low
I 3.6V power supply
I GND
I/O DRAM data bus
I/O DRAM data bus
I/O DRAM data bus
I/O DRAM data bus
I/O DRAM data bus
I/O DRAM data bus
I 3.6V power supply
I GND
I/O DRAM data bus
I/O DRAM data bus
I/O DRAM data bus
I/O DRAM data bus
I/O DRAM data bus
I/O DRAM data bus
I GND
I 3.6V power supply
I/O DRAM data bus
I/O DRAM data bus
I/O DRAM data bus
I/O DRAM data bus
O SDRAM chip select [1], active low
I GND
I 3.6V power supply
O SDRAM chip select [0], active low
O Data input/output mask
O Clock to SDRAM
I x GND ao
y
I 3.6V power supply
i
I Clock input (27MHz)
O 8-bit YUV output
O 8-bit YUV output
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8
Pin No. Pin Name
108 YUV 2
109 YUV 3
110 YUV 4
111 Vcc
112 Vss
113 YUV 5
114 YUV 6
115 YUV 7
116 PCLK2XSCN
117 PCLKQSCN
118 VSYNCH#
119 HSYNCH#
120 Vss
121 Vcc
122 HD 0
123 HD 1
124 HD 2
125 HD 3
126 HD 4
127 HD 5
Q Q 128 HD 6
3 6 7 1 3
129 Vss
130 Vcc
131 HD 7
132 HD 8
133 HD 9
134 HD 10
135 HD 11
136 HD 12
137 HD 13
138 Vss
139 Vcc
140 HD 14
141 HD 15
142 HWRQ#
143 HRDQ#
144 HIRQ
145 HRST#
146 HIORDY
147 Vss
148 Vcc
HWR#
149
HWR#/DCI_ACK#
150 HRD#/DCI_CLK
151 HIOCS16#
u163
152 HCS1FX#
.
153 HCS3FX#
154 HA 0
155 HA 1
2 9 9 4 2 8
I/O Function
O 8-bit YUV output
O 8-bit YUV output
O 8-bit YUV output
I 3.6V power supply
I GND
O 8-bit YUV output
O 8-bit YUV output
O 8-bit YUV output
I/O 2X pixel clock
I/O Pixel clock
Vertical sync for screen video interface,
I/O programmable for rising or falling edge,
active low
Horizontal sync for screen video
I/O interface, programmable for rising or
falling edge, active low
I GND
I 3.6V power supply
I/O Host data bus
I/O Host data bus
I/O Host data bus
I/O Host data bus
I/O Host data bus
I/O Host data bus
I/O Host data bus
1 5 0 5 8 2 9 9 4
I GND
I 3.6V power supply
I/O Host data bus
I/O Host data bus
I/O Host data bus
I/O Host data bus
I/O Host data bus
I/O Host data bus
I/O Host data bus
I GND
I 3.6V power supply
I/O Host data bus
I/O Host data bus
O Host write request
O Host read request
I/O Host interrupt
O Host reset
I Host I/O ready
I GND
I 3.6V power supply
O Host write request
Host write / DCI interface acknowledge
I, I
signal, active low
m
I, I Host read / DCI interface clock
I Device 16-bit data transfer
co
O Host select 1
O Host select 3
I/O Host address bus
I/O Host address bus
ADV-1000
9 9
2 8 9 9
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