Denon ADV-1000 Service Manual page 30

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Pin No. Pin Name
27 XSSBAD
166 XSPDIREF
167 XSFDIREF
169 XSPLLFTR2
171 XSFDO
172 XSFTROPI
173 XSVR_PLL
174 XSPDOFTR2
175 XSVREFO
176 XSAWRCVCO
29 XSDFCT
30 XSCSJ
31 XSCLK
32 XSDATA
33 XSLDC
34 XSFGIN
35 XSSPDON
36, 37, 38, 39 XSFLAG[3:0]
48, 51, 52 XGPIO[2:0]
40 XMP1_7
41 XMP1_6
43 XMP1_5
44 XMP1_4
45 XMP1_3
47 XMP1_2
49 XMP1_1
57 XMP1_0
46 XMFSCSJ
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L 13942296513
54 XMPSENJ
56 XMALE
70 XMCSJ
71 XMRDJ
72 XMWRJ
73 XMINT1J
74, 75, 77, 78,
79, 80, 81, 82,
XMA[15:0]
83, 84, 85, 86,
87, 89, 90, 91
62, 63, 64, 65,
XMD[7:0]
66, 67, 68, 69
163 XTPLCK
164 XTSLRF
59 XOSC1
60 XOSC2
53 XCRSTJ
94 XHCS1J
93 XHCS3J
103 XHIORJ
104 XHIOWJ
105 XHDRQ
101 XHDACKJ
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99 XHCS16J
50 XHRSTJ
.
100 XHINT
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Type
I/A Sub-beam addition signal input
Phase detector reference current generator. Connect a resistor between this pin and
I/A
ground to set reference current
Frequency detector reference current generator. Connect a resistor between this pin and
I/A
ground to set reference current
I/A Data PLL loop filter pin#2
O/A Output node of frequency detector charge pump circuit
I/A Input node of loop filter OP circuit
I/A PLL reference voltage input
I/A Phase detector filter pin#1
O/A Reference voltage output
I/A Auto Wide Range Control of VCO input pin. For enlarge VCO range in CAV mode
I Detect detection signal input
O Chip select signal for accessing control registers
O Clock output for accessing control registers
I/O Registers data input/output pin
O Laser diode on/off control output for both CD/DVD
I Motor Hall sensor input
O Spindle motor on output
O These pins are used to monitor some status of servo control block
1. These pins are used as general purpose I/O bus
I/O
2. When use internal microcontroller, XGPIO[2] can be used as programmable I/O port 3.6.
I/O Internal microcontroller programmable I/O port 1.7.
I/O Internal microcontroller programmable I/O port 1.6.
I/O This pin is now changed to be NC.
I/O Internal microcontroller programmable I/O port 1.4.
I/O Internal microcontroller programmable I/O port 1.3.
I/O Internal microcontroller programmable I/O port 1.2.
I/O Internal microcontroller programmable I/O port 1.1.
Internal microcontroller programmable I/O port 1.0.
I/O
This pin is default used as the A16 (microcontroller address line 16)
I/O Output chip select connected to external flash ROM chip enable pin
I/O Output program store enable connected to external ROM PSENJ pin.
I/O This signal is used as address latch signal in address/data mux mode
1. This signal must be asserted for all microcontroller accesses to the register of this chip
I/O
2. When use internal microcontroller, this signal can be used as programmable I/O port 3.1
1. This signal is used as the Read Strobe signal
I/O
2. When use internal microcontroller, this signal can be used as programmable I/O port 3.0
I/O This signal is used as the Wire Strobe signal
1. This signal is an interrupt line to the microcontroller
I/O
2. When use internal microcontroller, this signal can be used as programmable I/O port 3.7
I/O These pins are used as address bus
These pins are used as data bus for the 16-bit processor mode, or the address/data mux
I/O
bus for the 8-bit processor mode.
I/O PLCK test pin
I/O SLRF test pin
I Crystal input/System clock. The input frequency from outside crystal or oscillator is 33.8688MHz
O Crystal output
Chip Reset. As asserted low input generates a component reset that stops all operations within
I
the chip and deasserts all output signals. All input/output signals are set to input.
I This pin is used to select the command block task file registers
I This pin is used to select the control block task file registers
I Asserted by the host during a host I/O read operation
I Asserted by the host during a host I/O write operation
1. DMA request. This pin is configured as the DMA request signal, and is used during DMA transfer
between the host and the controller. This pin is tri-stated when DMA transfers are not enabled.
O
2. MPEG acknowledge. This pin is used as the ACKJ signal when MPEG interface mode is selected.
1. DMA acknowledge. This pin is configured as DACKJ, and is used as the DMA acknowledge
signal during DMA data transfers.
I
2. MPEG request. This pin is used as the REQ signal when MPEG interface mode is selected
1. 16-bit data select. This signal indicates that a 16-bit data transfer is active on the host data
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bus. This pin is open-drain tri-state output.
O
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2. MPEG clock. This pin is used as the CLOCK signal when MPEG interface mode is selected.
I Host Reset. The reset of ATA bus
i
1. Host interface request. This tri-state pin is the host interrupt request, and is asserted to
indicate to the host that the controller needs attention.
O
2. MPEG begin. This pin is used as the BEGIN signal when MPEG interface mode is selected
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Description
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ADV-1000
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