Table of Contents
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Index
timing connections, 4-14 to 4-24
acquisition timing connections,
4-15 to 4-18
CONVERT* signal, 4-17
EXTSTROBE* signal, 4-18
PFI0/TRIG1 (EXT_TRIG) signal,
4-16
PFI1/TRIG2 (PRETRIG) signal,
4-17
typical posttriggered acquisition
(figure), 4-15
typical pretriggered acquisition
(figure), 4-16
general-purpose timing signal
connections, 4-19 to 4-24
FREQ_OUT signal, 4-24
GPCTR0_GATE signal, 4-20
GPCTR0_OUT signal, 4-20
GPCTR0_SOURCE signal, 4-19
GPCTR0_UP_DOWN signal, 4-20
GPCTR1_GATE signal, 4-21 to 4-22
GPCTR1_OUT signal, 4-22
GPCTR1_SOURCE signal, 4-21
GPCTR1_UP_DOWN signal,
4-22 to 4-24
programmable function input
connections, 4-14 to 4-15
waveform generation timing connections,
4-18
UPDATE* signal, 4-18
WFTRIG signal, 4-18
timing I/O specifications, A-8 to A-9
timing signal routing, 3-11 to 3-12
device and RTSI clocks, 3-11 to 3-12
programmable function inputs, 3-11
traceable recalibration, 5-3
transfer characteristic specifications
analog input, A-2
analog output, A-6
PCI-4451/4452 User Manual
triggers
analog, 3-6 to 3-9
above-high-level triggering mode
(figure), 3-8
below-low-level triggering mode
(figure), 3-7
high-hysteresis triggering mode, 3-8
inside-region triggering mode
(figure), 3-8
low-hysteresis triggering mode, 3-9
specifications, A-9
digital, specifications, A-9
RTSI triggers, 3-9 to 3-10
specifications, A-9
U
unipolar input/output. See polarity selection.
unpacking PCI-4451/4452, 1-2
update clock frequency, selecting, 3-12
update rate, and device configuration, 3-13
UPDATE* signal
digital I/O pin assignments (table), 4-7
digital I/O signal summary (table), 4-8
timing connections, 4-18
V
VirtualBench software, 1-3
voltage output specifications, A-6
W
waveform generation timing connections, 4-18
UPDATE* signal, 4-18
WFTRIG signal, 4-18
WFTRIG signal, 4-18
wiring considerations, 4-24 to 4-25
I-8
© National Instruments Corporation
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