National Instruments AutoCode NI MATRIX Reference page 218

Chapter 8 AutoCode Sim Cdelay Scheduler
AutoCode Reference
Now the inherent problem in the standard scheduler is clear. From launch
to output posting, you suffer a two-cycle delay for triggered tasks, and a
three-cycle delay for enabled tasks, instead of the standard unit cycle delay
present on real-time hardware for free-running periodic tasks. Your goal
will be to reduce both of these latencies to single-cycle delays. The
scheduler pipeline stages in the Sim Cdelay AutoCode scheduler are shown
in Figure 8-4.
A
B
C
D
E
F
G
H
I
Figure 8-4. Scheduler Pipeline Stages in the Sim Cdelay AutoCode Scheduler
Reset DataStore
Writers to Low
Priority
Read External
Inputs
Write DataStores
from External
Inputs
Identify Outputs
to Post
Post Outputs
Queue Tasks
Identify Outputs
to Post
Post Outputs
Dispatch Tasks
8-8
ATR tasks
ANC tasks
ni.com