Evaluation Board Hardware; Power Supplies; Input Signals; Audio Amplifier Output Signal - Analog Devices EVAL-SSM4567Z User Manual

UG-704

EVALUATION BOARD HARDWARE

POWER SUPPLIES

The SSM4567 requires two power supplies, VBAT and IOVDD.
VBAT voltages can be between 2.5 V and 5.0 V. The IOVDD
power supply must be 1.8 V. The
external dc power supply connections: VBAT (J3), VDD_REG
(J2), and EXT_IOVDD (J5). The
regulators on the board that can be isolated or bypassed to allow
for current measurements only for the SSM4567. Note that
VBAT supply currents may exceed 2 A, depending on supply
voltage and load impedance.
The VBAT input can be configured to supply all the voltages
required for the evaluation board to function.
VDD_REG is used to provide on-board 3.3 V and 1.8 V power
supply by LDOs (ADP1711). It can share the input with VBAT
by shorting J23, but VBAT must be higher than 3.5 V. If VBAT
input is lower than 3.5 V, VDD_REG should be provided
independently and be between 3.5 V and 5.0 V. The 1.8 V
output from the on-board LDO can supply IOVDD for the
SSM4567 or the EXT_IOVDD terminal, J5, can supply IOVDD.
J8 is used to select between the internal LDO or the external
terminal J5.
Note that the 3.3 V regulator is used to supply power to the
SPDIF input circuitry. There are on-board level shifters to
translate the signals to 1.8 V levels.
Figure 3. Power Input Terminals and Default Jumper Settings. VBAT Only
Using Internal Regulators for IOVDD and 3.3 V.

INPUT SIGNALS

On the right side of the PCB are two 10-pin headers: J25 and J26.
One header is used to connect the digital input audio signals
to the amplifier and the other can be used to connect to other
EVAL-SSM4567Z boards to enable the testing of multichip mode.
EVAL-SSM4567Z has three
EVAL-SSM4567Z has voltage
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EVAL-SSM4567Z User Guide
The two connectors are wired together in parallel so that they can
be used interchangeably (see Figure 4).
Figure 4. Jumper Configuration for Clock and Data Input from J25 and J26
For a direct connection from an external circuit using the I
headers, J25 and J26, the logic level inputs are at 1.8 V. A level
shifter is required at the sending circuit for these inputs to
operate at a different level.
The EVAL-SSM4567Z board also supports I
optical fiber port using the SPDIF format. The jumpers on J16
select the digital input from either the internal SPDIF interface or
the external I
2 S signals from J25/J26 (see Figure 5).
Figure 5. Jumper Configuration for Clock and Data Input from the SPDIF

AUDIO AMPLIFIER OUTPUT SIGNAL

The amplifier output is available at two 2-pin 0.100" headers:
J10 and J11. The speaker is connected in bridge-tied load (BTL)
configuration, and the output pins are labeled with their
polarity. For example, OUTP indicates the noninverting
terminal (see Figure 6).
S
2
2 S input from an
Receiver