Real Time Devices AD1200 User Manual page 99

intef
82C54
IIIODE 1: HARDWARE RETRTGGERABLE
ONE-SHOT
OUT will be initially high. OUT will go low on the CLK
pulse following a trigger to begin the one-shot pulse,
and will remain low until the Counter reaches zero.
QUT will then go high and remain high untilthe CLK
pulse atter the next trigger.
After writing the Control Word and initial count, the
Counter is armed. A trigger results in loading the
Counter and setting OUT low on the next CLK pulse'
thus starting the one-shot pulse. An initial count of N
will result in a one-shol pulse N CLK cycles in dura'
tion. The one-shot is retriggerable, hence OUT will
remain low for N CLK pulses after any trigger. The
one-shot pulse can be repeated without rewriting the
same count into the counter. GATE has no etfect on
OUT.
ll a new count is written to the Counter during a one-
shot pulse, the current one-shot is not affected un-
less the Counter is retriggered. In that case, the
Counter is loaded with the new count and the one-
shot pulse continues until the new count expires.
MODE 2: RATE GENERATOR
This Mode functions like a divide-by-N counter. lt is
typicially used to generate a Real Time Clock inter'
rirpt. OUf will initially be high. When the initial count
has decremented to 1, OUT goes low for one CLK
pulse. OUT then goes high again, the Counter re-
ioads the initial count and the process is repeated'
Mode 2 is periodic; the same sequence is repeated
indefinitely. For an initial count of N, the sequence
repeats every N CLK cYcles.
GATE :
1 enables counting; GATE : 0 disables
counting. lf GATE goes low during an output pulse,
OUT is set high immediately. A trigger reloads the
Counter with the initial count on the next CLK pulse;
OUT goes low N CLK pulses after the trigger. Thus
the GATE input can be used to synchronize the
Counter.
After writing a Control Word and initial count, the
Counter wili be loaded on the next CLK pulse. OUT
ooes low N CLK Pulses afier the initial count is writ-
ien. This allows the Counter to be synchronized by
software also.
w-t
c t x
oArc
oul
WF
c l x
oltE
our
9F
c r x
Gltt
our
l - i . I x l r i r I I i : l 3 i : [ l f f l : l 3 |
231244-9
Figure 16. Mode 1
WF
cl(
oltt
out
WT
clx
o^lE
oul
l ,. l - l - l -l : l l ll l 3 l l I i l : I
C w r l l l E l r a
L S l . 5
. W r
cLx
GATE
our
l- 1.1. 1. 1: l 3i : l l l ll : l3l
231244-'.lo
NOTE:
A GATE transition should not occur one clock prior to
terminal count.
Flgure 17. Mode 2
3-92