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A"/D Conversions
The following paragraphs walk you through the programming steps for performing A,/D conversions. Detailed
information about the conversion modes is presented in this section. You can follow these steps on the flow dia-
gums at the end of ttris chapter and in our example programs included with the board. In this discussion, BA refers
to the base address.
. Initializing the 8255 PPI
The eight Port B lines of the 8255 PPI control the channel selection, programmable IRQ, and external nigger
and DMA enable. Port B is programmed at I/O address location BA + 5:
D7
D6
D5
D4
D3
D2
D1
DO
Enable
;abled
rabled
Analog lnput
Channel Select
0000 = channel 1
0001 = channel 2
0 0 1 0 = c h a n n e l 3
IRQ Enabl
0 = IRQ disabled
1 = IRQ enabled
External Trigger Enable
0 = Disabled
1 = Enabled
0 0 1 0 = c h a n n e l 3
0 0 1 1 = c h a n n e l 4
01 00 = channel 5
0101 = channel 6
01 10 = channel 7
0 1 1 1 = c h a n n e l S
1 000 = channel 9
1 0 0 1 = c h a n n e l 1 0
1 0 1 0 = c h a n n e l 1 1
1 0 1 1 = c h a n n e l 1 2
1't 00 = channel 13
1 1 0 1 = c h a n n e l 1 4
1 1 1 0 = c h a n n e l 1 5
1 1 1 1 = c h a n n e l 1 6
B A + 5
To use Port B for these control functions, the 8255 must be initialized so that Port B is set up as a Mode 0
output port. This is done by writing this data to the PPI control word at VO address BA + 7 (X = don't care):
D7
D6
D5
D4
D3
D2
D1
DO
. Clearing the Board
It is good practice to sta$ your program by reseuing the 1200 board. You can do this by writing to the RESET
port located at BA + Z.The actual value you write to this port is irelevanl After resetting the board following
power-up, it is a good idea to take an AlD reading and throw it away to make sure the converter is initialized and
contains no unwanted data.
. Selecting a Channel
To select a conversion channel, you must assign values to bits 0 through 3 in the PPI Port B port at BA + 5. The
table below shows you how to determine the bit settings.
x
x
x
x
cH3
cH2
cHl
cH0
Channel
cH3
cH2
cH1
cH0
Channel
cH3
cH2
cH1
cH0
1
I
0
0
0
0
I
1
0
0
0
2
0
0
0
1
1 0
1
0
0
1
3
0
0
1
0
1 1
1
0
1
0
4
0
0
I
a
I
1 2
1
0
1
1
5
1
0
1 3
{
I
I
0
0
b
0
1
0
1
1 4
1
1
0
t
I
7
1
I
0
1 5
1
1
1
0
t'
0
1
1
1
1 6
I
1
1
4 - 1 1
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