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82C54
Writing a new count while counting does not atfect
the cunent counting sequence. lt a trigger is re-
ceived after writing a new count but before the end
of the cunent period, the Counter will be loaded with
the new count on the next CLK pulse and counting
will continue from the new count. Othenvise, th6
new count will be loaded at the end of the current
counting cycle. In mode 2, a COUNT of 1 is illegal.
MODE 3: SQUARE WAVE MODE
Mode 3 is typically used for Baud rate qeneration.
Mode 3 is similar to Mode 2 except for thJduty cycle
of OUT. OUT wiil initialty be high. When hatf ina ini_
tial count has expired, OUT goes low for the remain-
der of the count. Mode 3 is-periodic; the sequence
above is repeatad indefinitely. An initial count of N
results in a sguare wave with a period of N CLK
cycles.
GATE : 1 enables counting; GATE = 0 disables
coulling. lf GATE goes low white OUT is tow, OUT is
set high immediately; no CLK pulse is required. A
trigger reloads the Counter with the initial count on
the next CLK pulse. Thus the GATE input can be
used to synchronize the Counter
Atter writing a Control Word and initial count, the
Counter will be loaded on the next CLK pulse. This
allows the Counter to be synchronized by software
also.
Writing a new count while counting does not atfect
the current counting sequence. lf a trigger is re-
ceived after writing a new count but befo-r6 the end
of the cunent half-cycle of the square wave, the
Counter will be loaded with the new count on the
next CLK pulse and counting will continue lrom the
new count. Otherwise, the new count will be loaded
at the end of the current half-cycle.
Mode 3 is implemented as follows:
Even counts: OUT is initially high. The initialcount is
loaded on one CLK pulse and then is decremented
by two on succeeding CLK pulses. When the count
expires OUT changes value and the Counter is re_
loaded with the initial count. The above process is
repeated indefinitely.
Odd counts: OUT is initiaily high. The initiat count
minus one (an even number) is loaded on one CLK
pulse and then is decremenled by two on succeed_
ing CLK pulses. One CLK gulse after the count ex-
pires, OUT goes low and the Counter is reloaded
with the initial count minus one. Succeeding CLK
pulses decrement the count by two. When the count
expires, OUT goes high again and the Counter is
reloaded with the initial count minus one. The above
process is repeated indefinitely. So for odd counts,
OUT will be high for (N + 1)/2 counts and low for
(N -1)/2 counts.
IIODE 4: SOFTWARE TRtccERED STROBE
OUT will be initiaily high. When the initiat count ex-
pirgq, OUT will go low for one CLK pulse and then
go high again. The counting s€quence is,.triggered,,
by writing the initial count.
GATE : 1 enables counting; GATE : O disables
counting. GATE has no effect on OUT.
Atter writing a Control Word and initial count, the
Counter will be loaded on the next CLK pulse. This
CLK pulse does not decrement the couni, so for an
initial count of N, OUT does not strobe iow until
N + 1 CLK pulses after the initial count is written.
ff a new count is wriilen during counting, it wilt be
loaded on the next GLK pulse and countiig wiil con_
tinue from the new count. lf a two-byte corjnt is writ
ten, the following happens:
3-93
m
ctl
orra
0t
9t
c!i
oAr:
our
9I
cu
olt:
oul
NOTE:
A GATE transition should not occur one clock prior to
l€rminal count.
l - l . l * l . i :
l : l : i : i I t l : l :
l | ! l
231244-11
Flgure 18. Mode 3
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