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inqef
82C54
cs
RD WR A r Ao
0
1
0
0
0
Write into Counter 0
0
1
0
0
1
Write into Counter 1
0
1
0
1
0
Write into Counter 2
0
1
0
1
1
Write ControlWord
0
0
'l
0
0
Read from Counter 0
0
0
1
0
1
Read from Counter 1
0
0
1
1
0
Read from Counter 2
0
0
1
1
1
No-Qperation (3-State)
1
x
X
X
X
No-Operation (3-State)
0
1
1
X
X
No-Operation (3-State)
Flgure 14. Read/Wrlte Operailons Summary
This allows the counting sequence to be synchroniz_
ed by^gottware.
Again, OUT does not go high untit N
+ 1 CLK pulses afier the new count ot tt is written.
lf an initial count is written while GATE : 0, it will
still be loaded on the next CLK pulse. When GATE
goes high, OUT witt go high N CLK putses tater; no
CLK pulse is needed to load the Counter as this has
already been done.
Mode Definitions
The following are defined for use in describing the
operation of the 82C54.
CLK PULSE:a rising edge, then a failing edge, in
that order, of a Counter,s CLK input.
TRIGGER: a rising edge of a Counter's GATE in-
put.
COUNTER LOADTNG:
the transfer of a count from
the CR to the CE (refer to
the "Functional Descrip-
tion")
MODE 0: INTERBUPT ON TERMTNAL COUNT
Mode 0 is typically used for event countinq. After the
Control Word is written, OUT is initially lo-w, and will
remain low untilthe Counter reaches zero. OUT then
goes high and remains high until a new count or a
new Mode 0 Control Word is written into the Coun-
ter.
GATE : 1 enables counting; GATE : 0 disables
counting. GATE has no etfect on OUT.
After the Control Word and initial count are written to
a Counter, the initial count will be loaded on the next
CLK pulse. This CLK pulse does not decrement the
count, so for an initial count of N, OUT does not go
high until N + 1 CLK putses after the initiat count is
written.
ll a new count is written to the Counter, it will be
loaded on the next CLK pulse and counting will con.
tinue from the new count. lf a two-byte count is writ_
ten, the following happens:
1) Writing the first byte disabtes counting. OUT is set
low immediately (no clock pulse required).
2) Writing the second byte allows the new count to
be loaded on the next CLK pulse.
3-91
| - l " l * | * | I I ! I I I i I s l f f l F [ l
C W . l 0
t ! ! r t
l "l -l *l * l3 l : I I l l lt l ; l t :l
231244-8
NOTE:
The Following Conventions Apply To All Mode Timing
Diagrams:
1. Counters. are_programmed for binary (not BCD)
golllins and for Reading/Writing teast signiiicant byte
(LSB) only.
2. The counter is always selected (G always low).
3. CW stands for "Control Word"; CW : iO mein" a
control word of 10, hex is written to the counter.
4. LSB stands for "Least Significant Byte" of count.
5. Numbers below diagrams are count values.
The lower number is the least signiticant byte.
The upper number is the most signilicani byte. Since
the counter is. programmed to Read/Write LSB only,
the most signilicant byte cannot be read.
N stands for an undelined count.
Vertical lines show transitions between count values.
l " l - l - l - l 3l t lt l ! i ? l s l r: l
Figure 15. Mode 0
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