Real Time Devices AD1200 User Manual page 104

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82C54
A.C. CHARACTERISTICS (continued)
WRITE CYCLE
EXTENDED TEMPERATURE
= -40oC to *85oC for Extended T
2' ln Modes 1 and 5 trigg€rs are sampled on each rising clock edge. A second
trigger within .t20 ns (70 ns for the g2c54-2'
of the rising clock edge may not be det€cted.
3' Low'going glitches that violate tpwx, tpwt may cause errors requiring
count€r reprogramming.
4. Except ror Exrended remp., see enendb? Tehp. A.c. ctraraa6risiics olro*.
5. Sampled not 100o/o tested. T1 : 25.C.
6' It cLK present at rvvg min lhen count equals N+2 cLK pulses, Tryg max
equals counl N+1 cLK pulse. Twc min to
Tryg max, count will be either N * 1 or N + 2 CLK Dulses.
7' ln Modes 1 and 5, if GATE is present when wriiing a new count value,
al Tyy6 min counter will not be triggered, at Try6
max Counter will be triggered.
8' lf cLK present when writing a counter Latch or ReadBack command,
at Tq min cLK will be reflected in counl value
latched, at T61 max cLK will not be reflected in the counl value latched. writing
a counter Latch or ReadBack command
between Tg; min and Try; max will result in a latched count vallue wtricn is +
one teast significant bit.
Symbol
Parameter
82C54
82C54-2
Unlts
Min
Max
Min
Itlar
tew
Address Stable Before WR- J
0
0
ns
tsw
6stabte BeforeWF'J
0
0
ns
twn
Address Hold Time After WFI f
0
0
ns
tww
WR Pulse Width
1 5 0
95
ns
tow
Data Setup Time Before WFI f
120
95
ns
two
Data Hold Time After WFI f
0
0
ns
tnv
Command RecoveryTime
200
1 6 5
ns
CLOCK AND GATE
Symbol
Parameter
82C54
82C54-2
Units
Min
Max
Mln
Max
tcr-r
Clock Period
125
DC
100
DC
ns
tpwx
High Pulse Width
60(3)
30(3)
ns
tpwt
Low Pulse Width
60(3)
50(3)
ns
Tn
Clock Rise Time
25
25
ns
tp
Clock FallTime
25
25
ns
tew
Gate Wdth High
50
5 0 .
ns
tet
Gate Width Low
50
50
ns
tes
9ate Setup Time to CLK f
50
40
ns
tox
Gate Hold Time After CLK 1
50(2)
50(2)
ns
Too
Output Delay from CLK J
1 5 0
1 0 0
ns
tooo
Output Delay from Gate J
120
1 0 0
ns
twc
__qLK Delay for Loading(a)
0
55
0
55
ns
twc
Gate Delay for Sampling(a)
- 5
50
- 5
40
ns
two
OUT Delayfrom Mode Write
260
240
ns
tcl
CLK Set Up for Count Latch
-40
45
-40
40
ns
NOTES:
3-97

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