Real Time Devices AD1200 User Manual page 111

82C55A
Table 1. Pln Descrlpilon
Symbol
Pln Number
Dlp PLCC
Type
Name and Functlon
PAs-o
1 - 4 2-5
vo
PORT A, PINS 0-3: Lower nibbte of an g-bit data output latch/
butfer and an 8-bit data input latch.
FE
5
6
I READ CONTROL: This input is tow during CpU read operations.
es
6 7
I CHIP SELECT: A low on this input enables the 82C55A to
respond to FiE and WF signals. R-D and WR are ignored
otherwise.
GND
7
I System Ground
Ar-o
8 - 9
9 - 1 0 ADDRESS: These input signals, in conjunction FE and WF[,
control the selection of one of the three ports or the control
word registers.
A r
As
m
WR
F
Input Operailon (Read)
0 0
0
1
0
PortA-DataBus
0
1 0
1 0 PortB-DataBus
1 0 0
1 0
PortC-DataBus
1
1
0
1 0
ControlWord - Data Bus
Output Oplratlon (Wrtte)
0
0
1 0
0
Data Bus - Poit A
0
1
1 0 0
Data Bus - Port B
1 0
1
0
0
Data Bus - Port C
1
1
1
0
0
Data Bus - Control
Disable Functlon
x
X
X X
1 D a t a B u s - 3 - S t a t e
X
X
1 1 0 D a t a B u s - 3 - S t a t e
PCt-c
1 0 - 1 3
1 1 , 1 3 - 1 5
vo
PORT C, PINS 4-Z: Upper nibbte of an 8-bit data output latch/
buffer and an 8-bit data input butfer (no ratch for rnpui). This port
can be divided into two 4-bit ports under the mode control. Each
4-bit port contains a 4-bit latch and it can be used for the control
signaloutputs and status signal inputs in conjunction with ports
A and B.
Pco-g
14-17
1 6 - 1 9
vo
PORT C, PINS 0-3: Lower nibble of port C.
PBo-z
't8-25
20-22,
24-28
t/o
PORT B, PINS 0-Z: An 8-bit data output latch/butfer and an 8-
bit data input butfer.
Vcc
26
29
SYSTEITI POWER: * 5V powerSupply.
Dz-o
27-34 30-33,
35-38
vo
DATA BUS: Bi-directional, tri-state data bus lines, connected to
system data bus.
RESET
35
39
I
RESET: A high on this input clears the control register and atl
ports are set to the input mode.
WR
36
40
WRITE CONTRO|: This input is tow during CpU write
operations.
PAt-t
37-40
41-44
vo
PORT A, PINS 4-7: Upper nibble of an 8_bit data output latch/
lgttqr and an 8-bit data input tatch.
NC
1 , 1 2 ,
23,94
No Connect