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Your 1200 board can intemtpt the processor when a variety of conditions arc met. By using these intemrpts,
you can write software that effectively deals with real world events.
. Interrupt Request Lines
To allow different peripheral devices to generate intemrps on t}re same comput€r, the PC bus has eight different
intempt request (IRQ) lines. A nansition from low to high on one of these lines generates an interrupt, request
which is handled by the PC's interrupt controller. The intemrpt controller checks to see if intemtpts are to be
acknowledged from that IRQ and, if another intemrpt is already in progress, it decides if the new request should
supersede the one in progress or if it has to wait until the onein progress is done, This prioritizing allows an
intemrpt to be intemrpted if the second request has a higher priority. The priority level is based on the number of the
IRQ; IRQ0 has the highest priority, IRQI is second-highest, and so on through IRQ?, which has the lowest. Many of
the IRQs are used by the standard system resources. IRQ0 is used by the system timer,IRQ1 is used by the key-
board, IRQ3 by COM2, IRQ4 by COMI, and IRQ6 by the disk drives. Therefore, it is imporranr for you !o know
which IRQ lines are available in your system for use by tie 1200 board.
. 8259 Programmable Interrupt Controller
The chip responsible for handling interrupt requests in the PC is the 8259 Programmable Intemrpt Controller.
To use intemrpts, you need to know how to read and set the 8259's intemrpt mask register (IMR) and how to send
the end-of-interrupt (EOI) command to the 8259.
. Interrupt Mask Register (IMR)
Each bit in the interrupt mask register (IMR) contains the mask status of an IRQ line; bit 0 is for IRQ0, bit 1 is
for IRQI, and so on. If a bit is set (equal to 1), then the corresponding IRQ is masked and it will not generate an
interrupl If a bit is clear (equal to 0), then the corresponding IRQ is unmasked and can generate intemrpts. The
IMR is programmed through port 21H.
IRQT IRQ6 IRQ5 IRQ4
IRQ3
rR02
IRQl
IRQO
l/O Port 21H
For all bits:
0 = IRQ unmasked (enabled)
1 = IRQ masked (disabled)
. End-of-Interrupt (EOI) Command
After an intenupt service routine is complete, the 8259 intemrpt controller must be notified. This is done by
writing the value 20H to I/O port 20H.
. What Exactly Happens When an Interrupt Occurs?
Understanding the sequence of events when an intemrpt is riggered is necessary to properly write software
intemrpt handlers. When an intemrpt request line is driven high by a peripheral device (such as the 1200), the
intemrpt controller checks to see if intemrpts are enabled for that IRQ, and then checks CI see if other inremrpts are
active or requested and determines which intemrpt has priority. The intemrpt controller then intemtpts the proces-
sor. The curent code segment (CS), instruction pointer (IP), and flags are pushed on the stack for storage, and a new
CS and IP are loaded from a table that exists in the lowest 1024 bytes of memory. This table is refened to as the
intenupt vector table and each entry is called an intemrpt vector. Once the new CS and Ip are loaded from the
intemrpt vector table, the processor begins executing the code located at CS:IP. When the intemrpt routine is
completed, the CS, IP, and flags that were pushed on the stack when the intemrpt occurred are now popped from the
stack and execution resumes from the point where it was intemrpted.
. Using lnterrupts in Your Programs
Adding intenupts to your software is not as difficult as it may seem, and what they add in terms of performance
is often worth the effort. Note, however, that alttrough it is not that hard to use inierrupts, the smallest misake will
often lead !o a system hang that requires a reboot. This can be both frusuating and time-consuming. But, after a few
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